UC2842A /3A/4A/5A standard high performance current mode PWM controller

. Edge Cut Oscillator Discharge Current

. Current Mode Operation to 500kHz

. Automatic feedforward compensation

. Cycle-by-cycle lock PWM

Limiting

. Internally trimmed references

undervoltage lockout

. High current totem pole output

. Undervoltage Lockout with Hysteresis

. Low startup current (<0.5mA)

. Double Pulse Suppression

illustrate

The UC384xA family of control chips provides the necessary features to implement off-line or DC-to-DC fixed-frequency current-mode control schemes with minimal external parts count. Internal implementation circuitry includes a trimmed oscillator for precise duty cycle control under voltage lock, featuring a startup current of less than 0.5mA, and a trimmed accuracy reference for precision amplifier inputs under error to ensure latched operation. logic, a pulse width modulated comparator also provides current limit control, and a totem pole output stage or sinks high peak current. The output stage, suitable for driving N-channel mosfets, is low in the off state.

The differences between members of this family are the undervoltage lockout threshold and maximum duty cycle range. The UC3842A and UC3844A have ideal UVLO thresholds of 16V (on) and 10V (off) for offline applications, the corresponding thresholds for the UC3843A and UC3845A are 8.5 V, and 7.9V. The UC3842A and UC3843A can operate to near 100% duty cycle. From zero to <50% by UC3844A and UC3845A by adding an internal flip-flop, which can make blank output every other clock cycle.

Open loop test circuit.

Careful grounding techniques are required. Timing bypass capacitors should be connected tightly to a single point ground in pin 5. A transistor and a 5 KΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.

Figure 2: Oscillator Frequency vs Timing Resistance

Figure 3: Maximum Duty Cycle vs Timing Resistor

Figure 4: Oscillator discharge current versus Tem temperature.

Figure 5: Error amplifier open-loop gain and

Figure 6: Current sense input threshold versus error amplifier output voltage.

Figure 7: Reference voltage variation vs.

Figure 8: Reference short circuit current vs.

Figure 9: Output Saturation Voltage vs Load

Figure 10: Supply Current vs Supply Voltage

Figure 11: Output waveform.

Figure 12: Output Cross Conduction

Figure 13: Oscillator and output waveforms

Figure 14: Error Amplifier Configuration

Figure 15: Undervoltage Lockout

Figure 16: Current sensing circuit.

The peak current (is) is determined by the following formula

1.0V is the maximum value ≈RS

A small RC filter may be required to suppress switching transients.

Figure 17: Slope compensation technique.

Figure 18: Isolated MOSFET drive and current transformer sensing.

Figure 19: Locked shutdown.

Figure 20: Error Amplifier Compensation

Figure 21: External clock synchronization.

Figure 22: External duty cycle clamping and multi-unit synchronization.

Figure 23: Soft-start circuit

Figure 24: Soft-start and error amplifier output duty cycle clamping.