Summary

High-performance 32-bit digital signal processor for audio, medical, military, graphics, imaging, and communications; Super Harvard architecture—4 independent buses for dual data fetch, instruction fetch and non-intrusive, zero-overhead I/ O; Backward compatible assembly source code level compatible with ADSP-2106x DSPs; single instruction, multiple data (SIMD) computing architecture Two 32-bit IEEE floating point computing units, each with a multiplier, ALU , shifter and register files; integrated peripherals integrated I/O processor, 4M-bit on-chip dual port SRAM, glueless multiprocessing functions and ports (serial, link, external bus and JTAG).

feature

100 MHz (10 ns) core instruction rate ( ADSP-21160N ); single-cycle instruction execution, including SIMD operations in two compute units; dual-data address generator with modulo reverse addressing; zero-overhead loops and single-cycle loops setup, providing efficient program sequencing; IEEE 1149.1jtag standard test access port and on-chip emulation; 400-ball 27mm × 27mm PBGA package; lead-free (RoHS compliant) packaging; 200 million fixed-point MACs sustained performance (ADSP-21160N); Single Instruction Multiple Data (SIMD) architecture provides; two computational processing units; concurrent execution each processing element executes the same instructions, but operates on different data; code compatibility at the assembly level, using the same as the ADSP-2106x SHARC DSPs instruction set; parallelism in bus and compute unit allows; single-cycle execution (with or without SIMD) of multiply operations, arithmetic operations, dual memory reads and writes, and instruction fetches; up to 4 transfers between memory and core ;32-bit floating-point or fixed-point words per cycle; multiply, add and subtract to accelerate FFT butterfly operations; memory attributes; 4M-bit on-chip dual-port SRAM, independently accessible by core processor, host, and DMA; 4G for off-chip memory Word address range; memory interface supports programmable wait state generation and page mode for off-chip memory; DMA controller support; 14 zero-overhead DMA channels for ADSP-21160x internal and external memory, external peripherals, host processor , transfers between serial ports, or link ports; parallel with full-speed processor, 64-bit background DMA transfers at core clock speed; host processor interface for 16-bit and 32-bit microprocessors; multiprocessing support provided; available Glueless connections for extended DSP multiprocessing fabric; distributed on-chip bus arbitration for 6 ADSP-21160x processors plus host parallel bus connections; 6 link ports for point-to-point connections and array multiprocessing; serial ports provided; two 1 synchronous serial port with companding hardware; independent transmit and receive functions; TDM support for T1 and E1 interfaces; 64-bit wide synchronous external port available; glueless connection of asynchronous and SBSRAM external memory.

General Instructions

The ADSP-21160x SHARC family of digital signal processors has two members: ADSP-21160M and ADSP-21160N. The ADSP-21160M is fabricated in a 0.25-micron CMOS process. The ADSP-21160N is fabricated in a 0.18-micron CMOS process. The ADSP-21160N has higher performance and lower power consumption than the ADSP-21160M. For ease of portability, the ADSP-21160x is an application source code compatible with the first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. In order to take advantage of the SIMD (Single Instruction, Multiple Data) capabilities of the processor, some code changes are required. Like other SHARC DSPs, the ADSP-21160x is a 32-bit processor optimized for high-performance DSP applications. The ADSP-21160x includes a core running up to 100 MHz, a dual-port on-chip SRAM, an integrated I/O processor that supports multiprocessing, and multiple internal buses to eliminate I/O bottlenecks.

Table 1 shows the main differences between the ADSP-21160M and ADSP-21160N processors.

The ADSP-21160x introduces single-instruction, multiple-data (SIMD) processing. Using two computational units (the ADSP-2106x SHARC DSP has one), the ADSP-21160x can double the performance of the ADSP-2106x on a range of digital signal processing algorithms.

The ADSP-21160N is fabricated using the most advanced high-speed, low-power CMOS process with an instruction cycle of 10ns. The SIMD computing hardware of the ADSP-21160N runs at 100mhz and can perform 600 million mathematical operations per second (ADSP-21160M can perform 480 million operations in 12.5ns instruction cycle time).

Table 2 shows the performance benchmarks for the ADSP-21160x.

These benchmarks provide single-channel extrapolation of measured dual-channel (SIMD) processing performance. For more information on benchmarking and optimizing DSP code for single- and dual-channel processing, see the Analog Devices website ().

The ADSP-21160x continues the SHARC family's industry-leading standard in DSP integration, combining a high-performance 32-bit DSP core with integrated system-on-chip functionality. These features include 4M-bit dual-port SRAM memory, a host processor interface, an I/O processor supporting 14 DMA channels, two serial ports, six link ports, an external parallel bus, and glueless multiprocessing.

The functional block diagram of the ADSP-21160x (Figure 1 on page 1) illustrates the following architectural features:

• Two processing elements, each consisting of an ALU, pliers, shifters and data register files

• Data Address Generator (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data transfers between memory and core per core processor cycle

• Interval timer

• On-chip SRAM (4M bits)

• External ports that support:

• Interface with off-chip memory peripherals

• Glueless multiprocessing support for six ADSP-21160x SHARC DSPs

• host port

• DMA controller

• Serial and link ports

• JTAG test access port

Figure 2 shows a typical uniprocessor system. The multiprocessing system is shown in Figure 3 on page 6.

ADSP-21160X Series Core Architecture

The ADSP-21160x processors contain the following architectural features at the core of the ADSP-2116x family. The ADSP-21160x is code compatible with the ADSP-2106x and ADSP-21161 at the assembly level.

SIMD computing engine

The ADSP-21160x contains two computational processing elements that operate as single-instruction, multiple-data (SIMD) engines. The processing elements are called PEX and PEY, and each element contains an ALU, multiplier, shifter, and register file. PEX is always active and PEY can be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instructions are executed in both processing elements, but each processing element operates on different data. The architecture can efficiently execute math-intensive DSP algorithms.

Entering SIMD mode also affects how data is transferred between memory and processing elements. In SIMD mode, twice the data bandwidth is required to maintain computational operations in the processing unit. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and processing elements. When transferring data using DAGs in SIMD mode, two data values are transferred each time the memory or register file is accessed.

Independent parallel computing unit

Within each processing unit is a set of computational units.

Computational units include arithmetic/logic units (ALUs), multipliers, and shifters. These units execute single-cycle instructions. The three units in each processing unit are arranged in parallel to maximize computational throughput. A single multifunction instruction performs parallel arithmetic unit and multiplier operations. In SIMD mode, parallel ALU and multiplier operations occur simultaneously in both processing units. These computational units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats.

data register file

A general purpose data register file is included with each processing element. The register file transfers data between the computational unit and the data bus and stores intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2116x enhanced Harvard architecture, allow for unconstrained data flow between the compute unit and internal memory. The registers in PEX are called R0–R15, and the registers in PEY are called S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The processor employs an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers instructions and data (see Functional Block Diagram 1). With the ADSP-21160x digital signal processors' separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands and one instruction (from cache) in one cycle.

instruction cache

The ADSP-21160x includes an on-chip instruction cache that supports triple bus operations to fetch one instruction and four data values. The cache is selective and only caches instructions whose fetches conflict with PM bus data accesses. This cache allows full-speed execution of the core, providing loop operations such as digital filter multiply-accumulate and FFT butterfly processing.

Data address generator with hardware circular buffer

The two data address generators (DAGs) of the ADSP-21160x digital signal processors are used for indirect addressing and implement circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required for digital signal processing, typically used in digital filters and Fourier transforms. The product's two DAGs contain enough registers to create up to 32 circular buffers (16 primary, 16 secondary). DAGs automatically handle wrapping address pointers, reducing overhead, improving performance, and simplifying implementation. A circular buffer can start and end at any memory location.

Flexible instruction set

The 48-bit instruction word accommodates various parallel operations for concise programming. For example, a processor can conditionally perform multiplication, addition, and subtraction in two processing elements, while branches are all performed in one instruction.

Memory and I/O Interface Capabilities

Expanding the core of the ADSP-2116x series, the ADSP-21160x adds the following architectural features.

Dual-port on-chip memory

The ADSP-21160x contains 4 Mbits of on-chip SRAM divided into 2 blocks per Mbit that can be configured into different combinations of code and data storage (Figure 4). Each memory block is dual-ported and independently accessed by the core processor and the I/O processor in a single cycle. The dual-port memory combines three independent on-chip buses, allowing two data transfers from the core and the I/O processor in one cycle. The ADSP-21160x memory can be configured for up to 128K words of 32-bit data, 256K words of 16-bit data, 85K words of 48-bit instructions (or 40-bit data), or a combination of different font sizes up to 4 megabits. All memory can be accessed as 16-bit, 32-bit, 48-bit or 64-bit words. A 16-bit floating-point storage format is supported, effectively doubling the amount of data that can be stored on-chip. Conversion between 32-bit floating-point and 16-bit floating-point formats is done in one instruction. Although each memory block can store a combination of code and data, when one block stores data, the DM bus is used for transmission, and when another block stores instructions and data, the PM bus is used for transmission, and the access efficiency is the highest. Using the DM bus and PM bus in this way, each memory block has a dedicated bus, ensures single-cycle execution of two data transfers. In this case, the instruction must be available in the cache.

Off-Chip Memory and Peripheral Interfaces

The external ports of the ADSP-21160x digital signal processors provide the interface between the processor and off-chip memory and peripheral devices. The 4G word off-chip address space is contained in the processor's unified address space. Separate on-chip buses for PM address, PM data, DM address, DM data, I/O address, and I/O data are multiplexed on external ports to create a single 32-bit address bus and a single 64-bit data bus the external system bus. The lower 32 bits of the external data bus are connected to even addresses, and the upper 32 bits of the 64 bits are connected to odd addresses. Each access to external memory is based on taking the address of a 32-bit word, whereas with a 64-bit bus, two address locations can be accessed simultaneously. When an instruction is fetched from external memory, two 32-bit data locations are accessed (16 bits are unused). Figure 5 shows the alignment of various accesses to external memory.

External ports support asynchronous, synchronous, and synchronous burst access. ZBT synchronous burst SRAM can be glueless. Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate bank select signals. To simplify addressing of page-mode DRAMs, separate control lines are also generated. The ADSP-21160x provides programmable memory wait states and external memory acknowledgement control, allowing interfacing with DRAM and peripherals with variable access, hold, and disable time requirements.

DMA controller

The on-chip DMA controller of the ADSP-21160x DSPs allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisible to the processor core, allowing DMA operations to occur while the cores are executing their program instructions concurrently. DMA transfers can occur between the processor's internal memory and external memory, external peripherals, or the host processor. DMA transfers can also occur between the product's DSP internal memory and its serial or link ports. Perform external bus packing of 16, 32, 48, or 64-bit words during DMA transfers. The ADSP-21160x-6 provides 14 DMA channels through the link port, 4 through the serial port, and 4 through the processor's external port (for host processor, other ADSP-21160x processors, memory, or I/O transfers ). Programs can be downloaded to the processor using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels (DMAR1-2, DMAG1-2) using the DMA request/grant lines. Other DMA functions include generating interrupts on completion of DMA transfers, 2D DMA, and DMA chained auto-chained DMA transfers.

multiprocessing

The ADSP-21160x offers powerful features tailored for multiprocessing DSP systems, as shown in M. External ports and link ports provide integrated glueless multiprocessing support.

The external ports support a unified address space (see Figure 4), allowing direct inter-processor access to each processor's internal memory. Distributed bus arbitration logic is included on-chip for simple, glue-free connection of systems containing up to six ADSP-21160x processors and one host processor. The main processor switch incurs only one cycle of overhead. Bus arbitration can choose between fixed priority or rotating priority. Bus locks allow an indivisible read-modify-write sequence of semaphores. Provides vectored interrupts for interprocessor commands. On the external port, the maximum throughput of data transfer between processors is 400 Mbytes/sec (ADSP-21160N). Broadcast Write allows simultaneous data transfer to all ADSP-21160x DSPs and can be used to implement reflected semaphores.

Six link ports provide a second method of multiprocessing communication. Each link port can support communication with another ADSP-21160x, using these links to build a large multiprocessor system in two or three dimensions. The system can use link ports and cluster multiprocessing simultaneously or independently.

link port

The processor has six 8-bit link ports that provide additional I/O capabilities. Each link port supports 100Mbytes/second (ADSP-21160N) and has the ability to run at 100MHz. Link port I/O is particularly useful for point-to-point interprocessor communication in multiprocessing systems. Link ports can work independently at the same time. Link port data is packed into 48-bit or 32-bit words that can be read directly by the core processor or transferred to on-chip memory. Each link port has its own double-buffered input and output registers. The clock/ack handshake controls link port transfers. Transmissions can be programmed to send or receive.

serial port

The processor has two synchronous serial ports that provide an inexpensive interface to a variety of digital and mixed-signal peripherals. The serial ports operate at half the core clock rate, with a maximum data rate of 50 Mbit/s per port (ADSP-21160N). Separate transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred between on-chip memories via dedicated DMA. Each serial port provides TDM multi-channel mode. Serial ports can use little-endian or big-endian transfer formats, and word lengths can be selected from 3 to 32 bits. They offer selectable synchronization and transmission modes and selectable μ-law or A-law companding. Serial port clock and frame synchronization can be generated internally or externally.

host processor interface

The ADSP-21160x host interface allows easy connection to standard 16-bit and 32-bit microprocessor buses without additional hardware. The host interface is accessed through the external ports of the ADSP-21160x digital signal processors and stored in a unified address space. The host interface has four DMA channels; code and data transfers are done with low software overhead. The host processor passes the Host Bus Request (HBR), Host Bus Grant (HBG), Ready (REDY), Acknowledge (ACK) and Chip Select (CS) signals. The host can directly read and write the processor's internal memory, and can access the DMA channel settings and mailbox registers. Vectored interrupt support provides efficient execution of host commands.

The host-processor interface can be used for multiprocessor or uniprocessor systems. For multiprocessor systems, host access to SHARC requires low drive address pins ADDR17, ADDR18, ADDR19 and ADDR20. It is not enough to connect these pins to ground through a resistor (for example, 10 k). These pins must be driven with sufficient drive strength (10 to 50) to overcome the SHARC retainer latch on these pins. If the drive provided is not strong enough, data access failures may occur.

For uniprocessor SHARC systems using this host access feature, address pins ADDR17, ADDR18, ADDR19, and ADDR20 may be constrained low (for example, through 10 kΩ resistors), driven by buffers/drivers, or left floating. Either option is sufficient.

program start

The internal memory of the ADSP-21160x can be accessed from an 8-bit EPROM, the host processor, or through one of the link ports at system power-up. Boot source selection is controlled by the BMS (boot memory select), EBOOT (EPROM boot) and LBOOT (link/host boot) pins. 32-bit and 16-bit host processors are available for booting.

phase locked loop

The processor uses an on-chip phase-locked loop to generate the internal clock for the core. Ratios of 2:1, 3:1 and 4:1 are supported between the core and CLKIN. The CLK U CFG pin is used to select the ratio. CLKIN rate is the rate at which the synchronous external port operates.

power supply

The processor has separate power connections for internal (VDDINT), external (VDDEXT) and analog (AVDD and AGND) power supplies. Internal and analog supplies must meet VDDINT and AVDD requirements. The external power supply must meet the 3.3V requirement. All external power pins must be connected to the same power supply.

The PLL filter shown in Figure 6 must be added to each ADSP-21160x in the system. VDDINT is the digital core power supply. It is recommended to use a short thick wire to connect the capacitor directly to AGND. It is recommended to place capacitors as close as possible to AVDD and AGND. The connection from AGND to the (digital) ground plane should be made after the capacitor. It is reasonable to use a thick trace for a GND because the PLL is a relatively low power circuit and it will not work with any other ADSP-21160x GND connections.

development tools

Analog Devices supports its processors through a comprehensive suite of software and hardware development tools, including integrated development environments (including CrossCore Embedded Studio and/or VisualDSP++), evaluation products, simulators, and various software plug-ins.

Integrated Development Environment (IDE)

For C/C++ software writing and editing, code generation and debugging support, the emulation device provides two IDEs.

The latest IDE, CrossCore Embedded Studio, is based on the Eclipse framework. It supports most analog device processor families and is the IDE of choice for future processors, including multi-core devices. CrossCore Embedded Studio seamlessly integrates available software plug-ins to support real-time operating systems, file systems, TCP/IP stacks, USB stacks, algorithm software modules and evaluation hardware board support packages. For more information, visit /cces. trademark

The other analog device IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore Embedded Studio. The IDE includes a simulated device VDK real-time operating system and an open-source TCP/IP protocol stack. For more information, visit /visualdsp. Note that VisualDSP++ will not support future analog device processors.

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices offers a wide range of EZ-KIT Lite evaluation boards. Including the processor and key peripherals, the evaluation board also supports evaluation and development features such as on-chip emulation capabilities. Various EZ expanders are also available, which are daughter cards that provide additional specialized functions, including audio and video processing. For more information, visit and search for "ezkit" or "ezextender".

EZ-KIT Lite Evaluation Kit

For a more cost-effective way to learn about analog device processors, Analog Devices offers a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-kit Lite evaluation board, instructions for downloading an available IDE evaluation version, USB cable and power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user's PC, enabling the selected IDE evaluation kit to emulate the on-board processor in the circuit. This allows customers to download, execute and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of on-board flash memory devices to store user-specific boot codes for stand-alone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKit or any custom system using a supported analog device processor.

Software Add-in for CrossCore Embedded Studio

Analog Devices offers software plug-ins that integrate seamlessly with CrossCore Embedded Studio to extend its functionality and reduce development time. Plug-ins include board support packages for evaluating hardware, various middleware packages, and algorithm modules. Documentation, help, configuration dialogs, and coding examples in these add-ins are available through the CrossCore Embedded Studio IDE after the add-in is installed.

Board Support Package for Evaluation Hardware

Software support for the EZ-KIT Lite Evaluation Board and EZ-Expansion Daughter Cards is provided by a software add-on called a Board Support Package (BSP). The bsp contains the required drivers, associated release notes, and select sample code for a given evaluation hardware. Download links for specific BSPs are located on the webpages of the relevant EZ-KIT or EZExtender products. The link is in the product download area of the product webpage.

middleware package

The emulated devices respectively provide middleware plugins such as RTOS, file system, USB stack and TCP/IP stack. For more information, see the following web pages:

•/ucos3

•/ucfs

•/ucusbd

•/lwip

Algorithm module

To speed up development, Analog Devices provides plug-ins that execute popular audio and video processing algorithms. These are available with CrossCore Embedded Studio and VisualDSP++. For more information, visit and search for "Blackfin Software Modules" or "SHARC Software Modules".

Design a simulator-compatible DSP board (target)

For the testing and debugging of embedded systems, Simulation Devices provides a series of simulators. On each JTAG DSP, the analog device provides an IEEE 1149.1jtag Test Access Port (TAP). Using this JTAG interface allows for easy in-circuit emulation. The emulator accesses the processor's internal features through the processor's TAP, allowing developers to load code, set breakpoints, and view variables, memory, and registers. The processor must stop to send data and commands, but once the simulator completes an operation, the DSP system is set to run at full speed without affecting system timing. The emulator requires the target board to contain a header that supports connecting the DSP's JTAG port to the emulator.

For detailed information on target board design issues, including mechanical layout, uniprocessor connections, signal buffering, signal termination, and emulator pod logic, see the application note (EE-68) "JTAG Emulation Technical Reference for Analog Devices" (/EE- 68). This documentation is regularly updated to keep up with improvements in emulator support.

Additional Information

This data sheet provides an overview of the ADSP-21160x architecture and features. For more information on the core architecture and instruction set of the Blackfin family, see the ADSP-21160 SHARC DSP Hardware Reference and the ADSP-21160 SHARC DSP Instruction Set Reference. For more information on the development tools for this processor, see the VisualDSP++ User's Guide.

Related Signal Chains

A signal chain is a series of signal conditioning electronics that receive input (either from sampling real-time phenomena or from stored data) and provide the output of one part of the chain to the next.

Signal chains are often used in signal processing applications to collect and process data or to apply system control based on real-time phenomenon analysis.

Analog devices simplify the development of signal processing systems by providing signal processing components designed to work well together. A tool is available on the website to view the relationship between a specific application and related components.

The Application Signal Chain page in Circuits from the lab site (http:\\\Circuits) provides:

• Signal chain graphic circuit block diagrams for various circuit types and applications

• Drill down to selection guides and application information from components in each chain

• Reference designs using best practice design techniques

Pin function description

The ADSP-21160x pin definitions are shown below. Inputs to be recognized as synchronous must meet timing requirements related to CLKIN (or to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asynchronously asserted as CLKIN (or TCK for TRST).

Connect or pull unused inputs to VDD or GND, except in the following cases:

• Address 31–0, Data 63–0, Page Number, BRST, CLKOUT (ID2–0

=00x) (Note: These pins have logic level hold circuits enabled on the ADSP-21160x digital signal processors with ID2–0=00x.)

• PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx (ID2–0=00x) (Note: These pins have pull-ups enabled on the ADSP-21160x with ID2–0=00x.)

• LxCLK, LxACK, LxDAT7–0 (LxPDRDE=0) (Note: See Link Port Buffer Control Register Bit Definitions in the ADSP-21160 SHARC Digital Signal Processor Hardware Reference.)

• DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI (Note: These pins have pull-ups.)

The following symbols appear in the Type column of Table 3:

A=Asynchronous, G=Ground, I=Input, O=Output, P=Power, S=Sync, (A/D)=Active Drive, (O/D)=Open Drain, T=Three states (when when SBTS is asserted, or when the ADSP-21160x is a bus slave).

Absolute Maximum Ratings

Stresses listed in Table 9 (ADSP-21160M) and Table 10 (ADSP-21160N) or above may cause permanent damage to the product. These are stress ratings only; functional operation of the product under the conditions described in the operating section of this specification or any other conditions above is not implied. Prolonged operation beyond maximum operating conditions may affect product reliability.

package information

The information shown in Figure 7 provides details on the package brand of the ADSP-21160M/ADSP-21160N processors. See the Ordering Guide on page 58 for a complete list of product availability.

Timing Specifications

The internal clock switching frequency of the ADSP-21160x digital signal processors is higher than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clock minimizes the skew between the system clock (CLKIN) signal and the DSP's internal clock (clock source for external port logic and I/O boards).

The internal clock (multiple of CLKIN) of the ADSP-21160x digital signal processors provides the clock signal for timing the internal memory, processor core, link ports, serial ports, and external ports (required for read/write strobes in asynchronous access mode) . During reset, use the CLK_CFG3–0 pins to program the ratio between the DSP’s internal clock frequency and the external (CLKIN) clock frequency. Even if the internal clock is the clock source for the external port, the external port clock always switches at the CLKIN frequency. To determine the switching frequency of the serial and link ports, the internal clock is divided using programmable divider controls for each port (TDIVx/RDIVx for serial ports and LxCLKD1–0 for link ports).

Note the following definitions of different clock periods for the CLKIN function and appropriate ratio control:

•tCCLK=(tCK)/CR

•tLCLK=(tCCLK)×LR

•tSCLK=(tCCLK)×SR, where:

• LCLK = link port clock

• SCLK = serial port clock

• tCK = clock period

• tCCLK = (processor) core clock cycle

• tLCLK = link port clock period

• tSCLK = serial port clock period

• CR = core/core ratio (2, 3 or 4:1, determined by the core/core ratio CFG3–0 at reset)

• LR = link port/core clock ratio (1, 2, 3 or 4:1, determined by LxCLKD)

• SR = serial port/core clock ratio (wide range, determined by CLKDIV)

Use the given precise timing information. Don't try to get arguments from other addition and subtraction operations. While addition or subtraction will yield meaningful results for a single device, the values given in this data sheet reflect statistical variation and worst-case scenarios. So it doesn't make sense to add parameters to get longer.

Test conditions for voltage reference levels are shown in Figure 33 on page 49.

The toggle attribute specifies how the processor changes its signals. Circuits external to the processor must be designed to be compatible with these signal characteristics. Switch characteristics describe what the processor will do in a given environment. Use the switch feature to ensure that any timing requirements of devices connected to the processor, such as memory, are met.

Timing requirements apply to signals controlled by circuits external to the processor, such as data inputs for read operations. Timing requirements ensure that the processor works properly with other devices.

During processor reset (reset pin low) or software reset (SRST bit in SYSCON register = 1), de-assertion (MS3–0, HBG, DMAGx, RDx, WRx, CIF, PAGE, BRST) and tri-state ( FLAG3-0, LxCLK, LxACK, LxDAT7-0, ACK, REDY, PA, TFSx, RFSx, TCLKx, RCLKx, DTx, BMS, TDO, EMU, DATA) timing is different. These occur asynchronously to CLKIN and may not conform to the specifications published in the Timing Requirements and Switching Characteristics table. The maximum delay for deassertion and three states is one tCK from RESET pin assertion low or setting the SRST bit in SYSCON. The DSP will not respond to SBTS, HBR and MMS accesses during reset. The HBR asserted before reset will be recognized, but the DSP will not return HBG until reset is released and the DSP has completed bus synchronization.

All timing specifications (timing requirements and switching characteristics) listed on pages 21 through 46 apply to the ADSP-21160M and ADSP-21160N unless otherwise noted.

power-on sequence

See Table 12 and Figure 8 for the power-up sequence. During the power-up sequence of the DSP, the difference in rise rate and activation time between the two supplies can cause current to flow in the I/O ESD protection circuit. To prevent this damage to the ESD diode protection circuit, analog devices recommend including a bootstrap Schottky diode (see Figure 9). A bootstrap Schottky diode connected between the VDDINT and VDDEXT supplies protects the ADSP-21160x from partially powering the VDDEXT supply. Including Schottky diodes will shorten the delay between power supply ramps, preventing damage to the ESD diode protection circuit. Using this technique, if the VDDINT rail is higher than the VDDEXT rail, the Schottky diode pulls the VDDEXT rail along the VDDINT rail.

clock input

See Table 13 and Figure 10 for clock inputs.

reset

Reset see Table 14 Figure 11

interrupt

For interrupts see Table 15 Figure 12

timer

The timers are shown in Table 16 and Figure 13.

banner

See Table 17 Figure 14 for flags.

Memory read bus master

In addition to the ACK pin requirements listed in Note 6, use these specifications for asynchronous interfacing with memory (and memory-mapped peripherals) without reference to CLKIN Table 18. These specifications apply when the ADSP-21160x is a bus master accessing external memory space in asynchronous access mode.

memory write bus master

In addition to the ACK pin requirements listed in Note 1, use these specifications for asynchronous interfacing to memory (and memory-mapped peripherals) without reference to CLKIN Table 19. These specifications apply when the ADSP-21160x is a bus master accessing external memory space in asynchronous access mode.

Synchronous read and write bus master

See Table 20 and Figure 17. Use these specifications to connect to external memory systems that require CLKIN relative timing, or to access slave ADSP-21160x (in the multiprocessor memory space). These synchronous switching features are also valid during asynchronous memory reads and writes unless otherwise noted (see Memory Reads - Bus Mastering on page 26 and Memory Writes - Bus Mastering on page 28).

When accessing the slave ADSP-21160x, these switch characteristics must meet the timing requirements for slave synchronous read/write (see Synchronous Read/Write - Bus Slave on page 32). The slave ADSP-21160x must also meet the (bus master) timing requirements for data and acknowledge setup and hold times.

Synchronous read and write bus slave

See Table 21 and Figure 18. Use these specifications for ADSP-21160x bus master access to slave IOP registers or internal memory (in the multiprocessor memory space). The bus master must meet these (bus slave) timing requirements.

Multiprocessor Bus Requests and Host Bus Requests

See Table 22 and Figure 19. Use these specifications to pass bus masters (BRx) or host processors, synchronous and asynchronous (HBR, HBG) between multiprocessing ADSP-21160x DSPs.

Asynchronous read and write host to ADSP-21160x

Using these specifications (Table 23, Table 24, Figure 20, and Figure 21) to access the ADSP-21160x, the host has asserted CS and HBR (low).

When the ADSP-21160x returns to the HBG, the host can drive the RDx and WRx pins to access the DSP internal memory or IOP registers of the ADSP-21160x. HBR and HBG are assumed to be low at this time point.

state timing bus master-slave

See Table 25 and Figure 22. These specifications show how the memory interface can be disabled (stop driving) or enabled (resume driving) with respect to the CLKIN and SBTS pins. This timing applies to the bus master conversion cycle (BTC) and host conversion cycle (HTC) and SBTS pins.

DMA handshake

See Table 26 and Figure 23. These specifications describe three DMA handshake modes. In these three modes, DMARx is used to initiate transfers. For handshake mode, DMAGx controls the locking or enabling of external data. For external handshake mode, data transfers are signaled by ADDR31–0, RDx, WRx, PAGE, MS3–0, ACK, and DMAGx. For Paced Master mode, control data transfers go through ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAGx). For Paced Master mode, the Master Timing Specifications for the Memory Read Bus Master, Memory Write Bus Master, and Synchronous Read/Write Buses ADDR31–0, RDx, WRx, MS3–0, page, Data 63–0, and Acknowledge also apply.

Link port receive, transmit

See Table 27, Table 28, Figure 24, and Figure 25 for link ports. To determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK, the link receiver data setup and hold relative to the link clock needs to be calculated. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK (Setup skew=tLCLKTWH minimum–tDLDCH–tSLDCL). Hold skew is the maximum delay introduced in LCLK relative to LDATA (hold skew = tLCLKTWL min + tHLDCH – tHLDCL). Calculations made directly from speed specifications result in unusually small twist times because they include multiple tester protection zones.

Note that there is a two cycle impact delay between the link port enable command and the DSP that enables the link port.

Output drive current-ADSP-21160M

Figure 29 shows the typical IV characteristics of the ADSP-21160M output driver. The curve represents the current drive capability of the output driver as a function of output voltage.

Output Drive Current - ADSP-21160N

Figure 30 shows the typical IV characteristics of the ADSP-21160N output driver. These curves represent the current drive capability of the output driver as a function of output voltage.

Power consumption

There are two parts to the total power dissipation: one is due to the internal circuitry and the other is due to the switching of the external output driver.

Internal power consumption depends on the instruction execution sequence and the number of data operands involved. Using current specifications (IDD-INPEAK, IDD-INHIGH, IDD-INLOW, and IDD-IDLE) from Electrical Characteristics-ADSP-21160M Open Electrical Characteristics-ADSP-21160N with current and operating information, engineers can estimate the ADSP for a specific application based on the following equations -21160x DSP internal power supply (VDDINT) input current:

% Peak  IDD-INPEAK

% High  IDD-INHIGH

% Low  IDD-INLOW

+ % Peak  IDD-IDLE= IDDINT

The external component of the total power dissipation is caused by toggling of the output pins. Its size depends on:

• Number of output pins toggled per cycle (O)

• Maximum frequency of switching (f)

• Load capacitance (C)

• Its voltage fluctuation (VDD) is calculated by the following formula:

The load capacitance should include the package capacitance (CIN) of the processor. The switching frequency consists of driving the load up and down again. Address and data pins can be driven high and low at a maximum rate of 1/(2tCK). The write strobe can toggle every cycle at a frequency of 1/tCK. The select pin switches at 1/(2tCK), but the select can be turned on every cycle.

ADSP-21160N example: Estimate PEXT based on the following assumptions:

• Systems with a set of external data memory asynchronous RAM (64-bit)

• Uses 4 64K x 16 RAM chips, each with a load of 10 pF

• External data memory writes occur every other cycle at a rate of 1/(2 tCK) with 50% of pin toggling

• The bus cycle time is 50 MHz (tCK=20 ns).

As shown in Table 38, the PEXT equation is calculated for each type of pin that can be driven.

Typical power dissipation under these conditions can now be calculated by adding the typical internal power dissipation:

• PEXT from Table 38

• PINT is IDDINT × 1.9 V, using the calculated IDDINT listed in Power Consumption on page 47

• Using AIDD values listed in Electrical Characteristics-ADSP-21160M on page 16 and Electrical Characteristics-ADSP-21160N on page 18, the PPLL is AIDD × 1.9V

Note that the conditions that lead to a worst-case PEXT are not the same as the conditions that lead to a worst-case PINT. The maximum pin count cannot occur when 100% of the output pins switch from all 1s to all 0s. Also note that it is not uncommon for applications to switch 100% or even 50% of the output at the same time.

Test conditions

Test conditions for timing parameters that appear on page 17 of the ADSP-21160x specification include output disable time, output enable time, and capacitive loading.

Output disable time

When output pins stop driving, go into a high impedance state, and begin to decay from the high or low voltage they output, they are considered disabled. The voltage decay time V on the bus depends on the capacitive load CL and the load current IL. This decay time can be approximated by the following equation:

The output disable time, tDIS, is the difference between tMEASURED and tDECAY, as shown in Figure 31. The measured time t is the time interval from the reference signal switching until the output voltage decays V from the measured output high voltage or output low voltage. tDECAY is calculated using the test loads CL and IL, and ΔV is equal to 0.5 V.

Output enable time

An output pin is considered enabled when it transitions from a high-impedance state to start driving. The output enable time, tENA, is the interval from when the reference signal reaches a high or low voltage level until the output reaches the specified high or low trip point, as shown in the output enable/disable diagram (Figure 31). If multiple pins are enabled (such as a data bus), the measurement is the measurement of the first pin to start driving.

System Hold Time Calculation Example

To determine the data output hold time in a particular system, first calculate tDECAY using the formula given above. V is chosen to be the difference between the output voltage of the ADSP-21160x DSP and the input threshold of the device requiring hold time. A typical ∏V will be 0.4 V. CL is the total bus capacitance (per data line) and IL is the total leakage or tristate current (per data line). The hold time is tDECAY plus the minimum disable time (ie, tDATRWH for the write cycle).

capacitive load

Output delay and hold are based on standard capacitive loading: 30 pF on all pins (see Figure 32). Figure 34, Figure 35, Figure 37, and Figure 38 show how the output rise time varies with capacitance. Figure 36 and Figure 39 graphically show how output delay and hold vary with load capacitance. (Note that this graph or derating does not apply to output disable delay; see Output Disable Time on page 48.) The graphs of Figure 34 through Figure 39 may not be linear outside the ranges shown.

environmental conditions

Thermal characteristics

The ADSP-21160x DSPs are housed in a 400-ball PBGA (Plastic Ball Grid Array) package.

The ADSP-21160x is specified for case temperature (TCASE). To ensure that the TCASE data sheet specification is not exceeded, a heat sink and/or airflow source may be used. Center block using ground pins (for ADSP-21160M, PBGA ball: H8-13, J8-13, K8-13, L8-13, M8-13, N8-13; for ADSP-21160N, PBGA ball: F7-14 , G7-14, H7-14, J7-14, K7-14, L7-14, M-14, N7-14, P7-14, R7-15) provide a thermal path to the ground plane of the printed circuit board. The heat sink should be connected to the ground plane (as close to the thermal path as possible) using thermal adhesive.

• TCASE = case temperature (measured on top of package)

• Ambient temperature

• PD = Power Loss (W) (this value depends on the specific application; the method for calculating PD is shown under Power Loss).

• θ = value from Table 39.

• θ=6.46°C/W junction box.

Dimensions

The ADSP-21160x processors are

27 mm x 27 mm, 400-ball PBGA lead-free package.

Surface Mount Design

The following table is provided as an aid to PCB design. See IPC-7351 General Requirements for Surface Mount Design and Ground Pattern Standards for industry standard design recommendations.