Optimized for Offline and DC-to-DC

converter

Low startup current (<1mA)

Automatic feedforward compensation

Pulse-by-Pulse Current Limiting

Enhanced load response characteristics

Undervoltage Lockout with Hysteresis

double pulse suppression

High current totem pole output

Internally trimmed bandgap reference

500 KHz operation

Low Roll Amplifier

illustrate

The UC3842 /3/4/5 control family provides implementation of off-line or DC-to-DC fixed frequency current mode control schemes. With minimal external parts count, the internal implementation circuitry includes a start-up current of less than 1 mA at the error amplifier input. Accuracy trims precision references, logic to ensure latching operation, pulse width modulated comparator stages that provide current limit control, and output stages designed to source or sink high peak currents. Output stage, suitable for driving N-channel mosfet, islow is off. The differences between members of this family are the undervoltage lockout threshold and the maximum duty cycle range. The UC3842 and UC3844 have ideal UVLO thresholds of 16V (on) and 10V (off) suitable for offline applications . The UC3843 and UC3845 have thresholds of 8.5 V and 7.9V. The UC3842 and UC3843 can operate with a duty cycle close to 100%. A series of outputs are output every other clock cycle through the UC3844 and UC3845 by adding an InternalToggleFlip flip-flop.

Error Amplifier Configuration

undervoltage lockout.

During undervoltage lockout, the output driver tends to draw a small amount of current. Pin 6 should be shunted to ground with a bleed resistor to prevent activation of the power switch with additional leakage current.

current sensor

The peak current (is) is determined by the following formula

1.0V is the maximum value ≈RS

A small RC filter may be required to suppress switching transients.

Open loop test circuit.

Careful grounding techniques are required. Timing bypass capacitors should be connected tightly to a single point ground in pin 5. A transistor and a 5 KΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.

close technology

Shutting down the UC2842 can be done in two ways; either boost pin 3 above 1V or unplug the pin and both diodes drop to ground when the voltage is below 1. Either way will result in an excessively high output from the PWM component (see block diagram). This PWM latch is in a reset dominant state, so the output will remain low for the next clock cycle after pins 1 and/or 3 are turned off.

For example, an external locking shutdown can be achieved by adding a thyristor that will be reset while riding a bicycle underneath. Point to referenceturnsof here, allowing to reset SCRto.

Offline Flyback Regulator

Slope compensation.

A fraction of the oscillator ramp can be summed by the resistor with the current sensed signal to provide over 50% of the ramp compensation period for converters requiring a load. Note that capacitor C forms a filter whose R2 to su push down the leading edge switching spike.