Summary

High-performance signal processor for communications, graphics and imaging applications; super Harvard architecture; four independent buses for dual data fetch, instruction; fetch and non-intrusive I/O; 32-bit IEEE floating point arithmetic unit multiplier, ALU and Shifter; Dual Port On-Chip SRAM and Integrated I/O Peripherals-a; Complete System-on-Chip; Integrated Multiprocessing; Main Feature-Processor Core; 50mips, 20ns Instruction Rate, Single Cycle Instruction Execution; 120 MFLOPS Peak, 80 MFLOPS sustained performance; dual data address generator with modulo reverse addressing; efficient program sequencing with zero overhead loops: single loop loop setup; IEEE JTAG Standard 1149.1 test access port and on-chip emulation; 32-bit single precision and 40 Bit-extended precision IEEE; floating-point data format or 32-bit fixed-point data format; 240-lead MQFP package, thermally enhanced MQFP, 225-ball; Plastic Ball Grid Array (PBGA) lead-free package.

General Instructions

The ADSP-21061 SHARC Super Harvard Architecture Computer is a signal processing microcomputer that offers a new level of functionality and performance. The ADSP-21061 SHARC is a 32-bit processor optimized for high performance digital signal processor applications. The ADSP-21061 uses the ADSP-21000 digital signal processor as the core to form a complete system-on-chip, adding a dual-port on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

The instruction cycle of ADSP-21061 is 20ns, and the working speed is 50mips. With the on-chip instruction cache, the processor can execute each instruction in one cycle. Table 1 shows the performance benchmarks of the ADSP-21061/ADSP-21061L.

The ADSP-21061 SHARC represents a new signal computer integration standard that combines a high-performance floating-point digital signal processor core with integrated system-on-chip functions, including 1M-bit SRAM memory, host processor interface, DMA controller, Serial ports and parallel bus connections for glueless DSP multiprocessing.

The ADSP-21061 continues SHARC's industry-leading DSP integration standard, combining a high-performance 32-bit DSP core with integrated system-on-chip functionality.

The block diagram on page 1 illustrates the following architectural features:

• Computational units (ALUs, multipliers and shifters) with shared data register files

• Data Address Generator (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data transfers between memory and core per core processor cycle

• Interval timer

• On-chip SRAM

• External ports for connecting off-chip memory and peripherals

• Host ports and multiprocessor interfaces

• DMA controller

• Serial port

• JTAG test access port

SHARC family core architecture

The ADSP-21061 includes the following architectural features of the ADSP-21000 series core. The ADSP-21061 processor is code and function compatible with the ADSP-21020, ADSP-21060 and ADSP-21062 SHARC processors.

Independent parallel computing unit

The arithmetic/logic unit (ALU), multiplier, and shifter all execute single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. A single multifunction instruction performs parallel arithmetic unit and multiplier operations. These computational units support IEEE 32-bit single-precision floating-point, extended-precision 40-bit floating-point, and 32-bit fixed-point data formats.

data register file

The general purpose data register file is used to transfer data between the computational unit and the data bus, and to store intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP-21000 Harvard architecture, allows for unconstrained data flow between the compute unit and internal memory.

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-21061 employs an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers instructions and data (Figure 1, page 1). Thanks to its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from cache) in one cycle.

instruction cache

The ADSP-21061 includes an on-chip instruction cache that supports triple-bus operations to fetch one instruction and two data values. The cache is selective, and only instructions that fetch conflict with PM bus data access are cached. This allows core, looping operations such as digital filter multiply-accumulate and FFT butterfly processing to be performed at full speed.

Data address generator with hardware circular buffer

The ADSP-21061's two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required for digital signal processing, typically used in digital filters and Fourier transforms. The two DAGs of the ADSP-21061 contain enough registers to create up to 32 circular buffers (16 primary register sets, 16 secondary register sets). DAGs automatically handle wrapping address pointers, reducing overhead, improving performance, and simplifying implementation. A circular buffer can start and end at any memory location.

Flexible instruction set

The 48-bit instruction word accommodates various parallel operations for concise programming. For example, the ADSP-21061 can conditionally perform multiplication, addition, subtraction, and branching in one instruction.

Memory and I/O Interface Capabilities

The ADSP-21061 processor adds the following architectural features to the SHARC family of cores.

Dual-port on-chip memory

The ADSP-21061 contains one megabit of on-chip SRAM, each consisting of two blocks of 0.5M bits. Each bank has 8 16-bit columns with 4k 16-bit words per column. Each memory block is dual-ported and independently accessed in a single cycle by the core processor and the I/O processor or DMA controller. Dual-port memory and a separate on-chip bus allow two data transfers from the core and one data transfer from the I/O in one cycle (see Figure 4 for the ADSP-21061 memory map).

On the ADSP-21061, memory can be configured for up to 32k words of 32-bit data, up to 64k words of 16-bit data, up to 16k words of 48-bit instructions (and 40-bit data), or up to 1 Mbit of various word sizes combination. All memory can be accessed as 16-bit, 32-bit or 48-bit.

A 16-bit floating-point storage format is supported, effectively doubling the amount of data that can be stored on-chip. Conversion between 32-bit floating-point and 16-bit floating-point formats is done in one instruction.

Although each memory block can store a combination of code and data, when one block stores data, the DM bus is used for transmission, and when another block stores instructions and data, the PM bus is used for transmission, and the access efficiency is the highest. Using the DM bus and PM bus in this way, each memory block has a dedicated bus, ensures single-cycle execution of two data transfers. In this case, the instruction must be available in the cache. Single-cycle execution is also maintained when one of the data operands is transferred to or from the ADSP-21061's external port.

Off-Chip Memory and Peripheral Interfaces

The external ports of the ADSP-21061 provide the interface between the processor and off-chip memory and peripherals. 4G of off-chip address space is contained in the unified address space of the ADSP-21061. Separate on-chip buses for program memory, data memory, and I/O are multiplexed on external ports to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus. The on-chip Super Harvard architecture provides triple-bus performance, and the off-chip unified address space provides flexibility for designers.

Facilitates addressing of external memory devices by on-chip decoding of high-order address lines to generate memory banks

Select the signal. To simplify addressing of page-mode DRAMs, separate control lines are also generated. The ADSP-21061 provides programmable memory wait states and external memory acknowledgement control, allowing interfacing with DRAM and peripherals with variable access, hold, and disable time requirements.

host processor interface

The host interface of the ADSP-21061 allows easy connection to standard 16-bit and 32-bit microprocessor buses without additional hardware. Asynchronous transfers at the full clock rate of the processor are supported. The host interface is accessed through the external port of the ADSP-21061, and the memory is mapped into the unified address space. The host interface provides two DMA channels; code and data transfers are done with low software overhead.

The host processor requests the external bus of the ADSP-21061

Has host bus request (HBR), host bus grant (HBG) and ready (REDY) signals. The host can directly read and write the internal memory of the ADSP-21061, and can access the DMA channel settings and mailbox registers. Vectored interrupt support is provided for efficient execution of host commands.

DMA controller

The ADSP-21061's on-chip DMA controller allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisible to the processor core, allowing DMA operations to occur while the cores are executing their program instructions concurrently.

DMA transfers can occur between the ADSP-21061's internal memory and external memory, external peripherals, or the host processor. DMA transfers can also occur between the ADSP-21061's internal memory and the serial port.

DMA transfers between external memory and external peripherals are another option. Perform external bus packing of 16-, 32- or 48-bit words during DMA transfers.

The ADSP-21061-4 provides 6 DMA channels through the serial port and 2 DMA channels through the processor's external port (for host processor, other ADSP-21061s, memory, or I/O transfers). Programs can be downloaded to the ADSP-21061 using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels (DMAR1-2, DMAG1-2) using the DMA request/grant lines. Other DMA features include generating interrupts when DMA transfers are complete, and DMA chains for automatically chaining DMA transfers.

serial port

The ADSP-21061 features two synchronous serial ports that provide an inexpensive interface to a variety of digital and mixed-signal peripherals. The serial ports can operate at the full clock rate of the processor, providing a maximum data rate of up to 50mbps per port. Separate transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred between on-chip memories via DMA. Each serial port provides TDM multi-channel mode.

Serial ports can use little-endian or big-endian transfer formats, and word lengths can be selected from 3 to 32 bits. They offer selectable synchronization and transmission modes and selectable μ-law or A-law companding. Serial port clock and frame synchronization can be generated internally or externally. The serial port also includes keyword and key masks to enhance interprocessor communication.

multiprocessing

The ADSP-21061 provides powerful functions tailored for multiprocessor DSP systems. The unified address space (see Figure 4) allows direct access to internal memory between the processors of each ADSP-21061. Up to six ADSP-21061s and a host processor are included on-chip for simple, glue-free connection systems containing distributed bus arbitration logic. The main processor conversion requires only one cycle of overhead. Bus arbitration is selectable with fixed or rotating priority. Bus locking allows an indivisible read-modify-write sequence of semaphores. Provides a vectored interrupt for interprocessor commands. The maximum throughput of data transfer between processors is 500 Mbps through the external port. Allows simultaneous broadcast writes to transmit data to all ADSP-21061s and can be used to implement reflected semaphores.

program start

The internal memory of the ADSP-21061 can be booted from an 8-bit EPROM or the host processor when the system is powered up.

Boot source selection is controlled by the BMS (boot memory select), EBOOT (EPROM boot) and LBOOT (host boot) pins. 32-bit and 16-bit host processors are available for booting.

Call from ADSP-21060 or ADSP-21062

The ADSP-21061 is pin-compatible with the ADSP-21060/ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins that correspond to the link port pins of the ADSP-21060/ADSP-21062 are not connected.

The ADSP-21061 is object code compatible with the ADSP-21060/ADSP-21062 processors, with the exception of the following features:

• ADSP-21061 memory is divided into two blocks, each block has eight columns, each column is 4k deep. The ADSP-21060/ADSP-21062 memory has 16 columns per block.

• The link port function is not available.

• Handshake External port DMA pins DMAR2 and DMAG2 are assigned to external port DMA channel 6, not channel 8.

• The 2-D DMA function for this movement is not available.

• Modify registers in SPORT DMA are not programmable.

On the ADSP-21061, block 0 starts at the beginning of the internal memory, normal word address 0x0002 0000. Block 1 starts at the end of block 0 and has consecutive addresses. The remaining addresses in memory are divided into blocks, which are aliased as block 1. This allows any code or data stored in block 1 of the ADSP-21062 to retain the same addresses on the ADSP-21061. These addresses will alias into the actual block 1 of each processor.

If you are developing applications using the ADSP-21062, but are migrating to the ADSP-21061, use only the first eight columns of each memory bank. In each bank of the ADSP-21062, your application is limited to 8k instructions or 16k data, or no more than any combination of instructions or data for the storage bank.

development tools

Analog Devices supports its processors through a comprehensive suite of software and hardware development tools, including integrated development environments (including CrossCore Embedded Studio and/or VisualDSP++), evaluation products, simulators, and various software plug-ins.

Integrated Development Environment (IDE)

For C/C++ software writing and editing, code generation and debugging support, the emulation device provides two IDEs.

The latest IDE, CrossCore Embedded Studio, is based on the Eclipse framework. It supports most analog device processor families and is the IDE of choice for future processors, including multi-core devices. CrossCore Embedded Studio seamlessly integrates available software plug-ins to support real-time operating systems, file systems, TCP/IP stacks, USB stacks, algorithm software modules and evaluation hardware board support packages. For more information, visit /cces. trademark

The other analog device IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore Embedded Studio. The IDE includes a simulated device VDK real-time operating system and an open-source TCP/IP protocol stack. For more information, visit /visualdsp. Note that VisualDSP++ will not support future analog device processors.

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices offers a wide range of EZ-KIT Lite evaluation boards. Including the processor and key peripherals, the evaluation board also supports evaluation and development features such as on-chip emulation capabilities. Various EZ expanders are also available, which are daughter cards that provide additional specialized functions, including audio and video processing. For more information, visit and search for "ezkit" or "ezextender".

EZ-KIT Lite Evaluation Kit

For a more cost-effective way to learn about analog device processors, Analog Devices offers a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-kit Lite evaluation board, instructions for downloading an available IDE evaluation version, USB cable and power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user's PC, enabling the selected IDE evaluation kit to emulate the on-board processor in the circuit. This allows customers to download, execute and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of on-board flash memory devices to store user-specific boot codes for stand-alone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKit or any custom system using a supported analog device processor.

Software Add-in for CrossCore Embedded Studio

The emulated device offers software add-ins that integrate seamlessly with CrossCore Embedded Studio to extend its functionality and reduce development time. Plug-ins include board support packages for evaluating hardware, various middleware packages, and algorithm modules. Documentation, help, configuration dialogs, and coding examples in these add-ins are available through the CrossCore Embedded Studio IDE after the add-in is installed.

Board Support Package for Evaluation Hardware

Software support for the EZ-KIT Lite Evaluation Board and EZExtender Daughter Cards is provided by software add-ons called Board Support Packages (BSPs). The bsp contains the required drivers, associated release notes, and select sample code for a given evaluation hardware. Download links for specific BSPs are located on the webpages of the relevant EZ-KIT or EZExtender products. The link is in the product download area of the product webpage.

middleware package

The emulated devices respectively provide middleware plugins such as RTOS, file system, USB stack and TCP/IP stack. For more information, see the following web pages:

•/ucos3

•/ucfs

•/ucusbd

•/lwip

Algorithm module

To speed up development, Analog Devices provides plug-ins that execute popular audio and video processing algorithms. These are available with CrossCore Embedded Studio and VisualDSP++. For more information, visit and search for "Blackfin Software Modules" or "SHARC Software Modules".

Design a simulator-compatible DSP board (target)

For the testing and debugging of embedded systems, Simulation Devices provides a series of simulators. On each JTAG DSP, the analog device provides an IEEE 1149.1jtag Test Access Port (TAP). Using this JTAG interface allows for easy in-circuit emulation. The emulator accesses the processor's internal features through the processor's TAP, allowing developers to load code, set breakpoints, and view variables, memory, and registers. The processor must stop to send data and commands, but once the simulator completes an operation, the DSP system is set to run at full speed without affecting system timing. The emulator requires the target board to contain a header that supports connecting the DSP's JTAG port to the emulator.

For detailed information on target board design issues, including mechanical layout, uniprocessor connections, signal buffering, signal termination, and emulator pod logic, see EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website ( ) Use the website search on "EE-68". This documentation is regularly updated to keep up with improvements to emulator support.

Additional Information

This data sheet provides an overview of the architecture and functionality of the ADSP-21061. For more information on the ADSP-21000 series core architecture and instruction set, see the ADSP-2106x SHARC User Manual.

Related Signal Chains

A signal chain is a series of signal conditioning electronics that receive input (either from sampling real-time phenomena or from stored data) and provide the output of one part of the chain to the next. Signal chains are often used in signal processing applications to collect and process data or to apply system control based on real-time phenomenon analysis. For more information on this term and related topics, see the "Signal Chain" entry in the EE Glossary on the Analog Devices website.

Analog devices simplify the development of signal processing systems by providing signal processing components designed to work well together. A tool is available on the website to view the relationship between a specific application and related components.

Circuits from the lab (/signal chains) courtesy: Trademark

• Signal chain graphic circuit block diagrams for various circuit types and applications

• Drill down to selection guides and application information from components in each chain

• Reference designs using best practice design techniques

Pin function description

The ADSP-21061 pin definitions are shown below. All pins are the same on the ADSP-21061 and ADSP-21061L. Inputs identified as synchronous must meet the timing requirements of CLKIN (or TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asynchronously asserted as CLKIN (or TCK for TRST).

Except for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs with internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx, TCLKx, RCLKx, TMS, and TDI), unused inputs should be VDD or GND connected or pulled - these pins can be left floating. These pins have a logic level hold circuit to prevent floating inputs from internally.

EZ-ICE Probe Target Board Connector

The ADSP-2106x EZ-ICE emulator uses the IEEE1149.1JTAG test access port of the ADSP-2106x to monitor the target board processor during the emulation process. The EZ-ICE probe requires the ADSP-2106x's CLKIN, TMS, TCK, TDI, TDO, and GND signals to be accessible on the target system through a 14-pin connector (2 rows of 7-pin strip headers), as shown in Figure 5. The EZ-ICE probe plugs directly into this connector for analog chips on the board. This connector must be added to the target board design if the ADSP-2106x EZ-ICE is to be used. The total trace length between the EZICE connector and the farthest device sharing the EZ-ICE JTAG pins should be limited to a maximum of 15 inches for guaranteed operation. This length limit must include EZ-ICE JTAG signals routed to one or more ADSP-2106x devices, or a combination of ADSP-2106x devices and other JTAG devices on the chain.

The 14-pin, double-row pin strap header is keyed in pin 3 position, pin 3 must be removed from the header. Pins must be 0.025 inches square and at least 0.20 inches long. Pin spacing should be 0.1 x 0.1 inches. Pin leads are available from suppliers such as 3M, McKenzie, and Samtec. BTMS, BTCK, BTRST and BTDI signals are provided so that the test access port can also be used for board level testing.

When the connector is not used for emulation, place jumpers between the Bxxx pins and the xxx pins as shown in Figure 5. If you are not going to use the test access port for board testing, connect BTRST to GND and BTCK to or pull up to VDD. The TRST pin must be asserted (pulsed low) after power up (via BTRST on the connector), or held low for proper operation of the ADSP-2106x. No Bxxx pins (pins 5, 7, 9 and 11) are connected to the EZ-ICE probes.

The JTAG signal is terminated on the EZ-ICE probe as shown in Table 3.

Figure 6 shows the JTAG scan path connections for a system containing multiple ADSP-2106x processors.

Connecting CLKIN to pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when instructed to perform operations such as starting, stopping, and single-stepping multiple ADSP-2106xs in a synchronous manner. If you don't need to synchronize these operations on multiple processors, just connect pin 4 of the EZ-ICE header to ground.

If simultaneous multiprocessor operation is required, the clock skew between multiple ADSP-21061 processors and the CLKIN pins on the EZ-ICE header must be minimal. If the skew is too large, synchronous operations may shut down one or more cycles between processors. For synchronous multiprocessor operation TCK, TMS, CLKIN and EMU should be considered critical signals in terms of skew and should be placed as short as possible on your board. If TCK, TMS, and CLKIN are driving a large number of ADSP-21061s (more than 8) in your system, treat them as a "clock tree" using multiple drivers to minimize skew. (See Figure 7 below and "JTAG Clock Tree" and "Clock Distribution" in the "High Frequency Design Considerations" section of the ADSP-2106x SHARC User Manual.)

If synchronous multiprocessor operation is not required (i.e. CLKIN is not connected), just use the appropriate parallel termination - actions on TCK and TMS. TDI, TDO, EMU and TRST are not critical signals in terms of tilt.

External power consumption (5V)

There are two parts to the total power dissipation, one is due to the internal circuitry and the other is due to the switching of the external output driver. Internal power consumption depends on the instruction execution sequence and the number of data operands involved. The internal power consumption is calculated as follows:

The external component of the total power dissipation is caused by toggling of the output pins. Its size depends on:

- Number of output pins (O) toggled in each cycle

- maximum frequency of switching (f)

- their load capacitance (C)

- Voltage fluctuation (VDD)

The calculation formula is:

The load capacitance should include the package capacitance (CIN) of the processor. The switching frequency consists of driving the load up and down again. Address and data pins can be driven high and low at a maximum rate of 1/(2tCK). The write strobe can toggle every cycle at a frequency of 1/tCK. The select pin switches at 1/(2tCK), but the select can be turned on every cycle. Example: Estimate PEXT using the following assumptions:

• Systems with a set of external data memory RAM (32 bits)

• Uses four 128k x 8 RAM chips, each with a 10 lbf load

• External data memory writes occur every other cycle at a rate of 1/(4tCK), 50% of pins toggle

• The instruction cycle rate is 40 MHz (tCK=25 ns)

For each type of pin that can be driven, the PEXT equation is calculated:

Typical power dissipation under these conditions can now be calculated by adding a typical internal power dissipation:

Note that the conditions that lead to a worst-case PEXT are not the same as the conditions that lead to a worst-case PINT. The maximum pin count cannot occur when 100% of the output pins switch from all 1s to all 0s. Also note that it is not uncommon for applications to switch 100% or even 50% of the output at the same time.

Internal power consumption (3.3V)

These specifications apply to the internal power supply portion of VDD only. Calculations of external supply current and total supply current can be found in the power dissipation section of this data sheet. For a full discussion of the code used to measure the power difference, see the tech note "SHARC Power Consumption Measurement Results."

Specifications are based on operational scenarios:

To estimate power consumption for a specific application, use the following formula, where % is the amount of time your program spends in that state:

External power consumption (3.3V)

There are two parts to the total power dissipation, one is due to the internal circuitry and the other is due to the switching of the external output driver. Internal power consumption depends on the instruction execution sequence and the number of data operands involved. The internal power consumption is calculated as follows:

The external component of the total power dissipation is caused by toggling of the output pins. Its size depends on:

- Number of output pins (O) toggled in each cycle

- maximum frequency of switching (f)

- their load capacitance (C)

- Their voltage swing (VDD) is calculated by:

The load capacitance should include the package capacitance (CIN) of the processor. The switching frequency consists of driving the load up and down again. Address and data pins can be driven high and low at a maximum rate of 1/(2tCK). The write strobe can toggle every cycle at a frequency of 1/tCK. The select pin switches at 1/(2tCK), but the select can be turned on every cycle. Example: Estimate PEXT using the following assumptions:

• Systems with a set of external data memory RAM (32 bits)

• Uses four 128k x 8 RAM chips, each with a 10 lbf load

• External data memory writes occur every other cycle at a rate of 1/(4tCK), 50% of pins toggle

• The instruction cycle rate is 40 MHz (tCK=25 ns)

For each type of pin that can be driven, the PEXT equation is calculated:

Typical power dissipation under these conditions can now be calculated by adding a typical internal power dissipation:

Note that the conditions that lead to a worst-case PEXT are not the same as the conditions that lead to a worst-case PINT. The maximum pin count cannot occur when 100% of the output pins switch from all 1s to all 0s. Also note that it is not uncommon for applications to switch 100% or even 50% of the output at the same time.

Absolute Maximum Ratings

Stresses greater than those listed below may cause permanent damage to the device. These are stress ratings only; functional operation of the device under these or any other conditions

rather than what is shown in the Operational Section of this Specification. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Packaging Identification Information

The information shown in Figure 8 provides details on the package brand of the ADSP-21061 processor. See the Ordering Guide on page 52 for a complete list of product availability.

Timing Specifications

The timing specification shown is based on a CLKIN frequency of 50mhz (tCK=20ns). DT derating allows timing specifications to be calculated over the minimum to maximum range of the tCK specification (see Table 7). DT is the difference between the derated CLKIN period (tCK) and the 25 ns CLKIN period:

Use the given precise timing information. Don't try to get arguments from other addition and subtraction operations. While addition or subtraction will yield meaningful results for a single device, the values given in this data sheet reflect statistical variation and worst-case scenarios. Therefore, parameters cannot be meaningfully added to get longer.

For voltage reference levels, see Figure 29 Voltage Reference Levels under Test Conditions.

Timing requirements apply to signals controlled by circuits external to the processor, such as data inputs for read operations. Timing requirements ensure that the processor works properly with other devices. (O/D) = Open Drain, (A/D) = Active Drive.

Switch characteristics specify how the processor changes its signals. Timing circuits outside of the processor that you cannot control must be designed to be compatible with these signal characteristics. Switch characteristics tell you what the processor will do in a given situation. You can also use the toggle feature to ensure that any timing requirements of devices attached to the processor, such as memory, are met.

Memory read bus master

Use these specifications to asynchronously connect to memory (and memory-mapped peripherals) without reference to CLKIN. When the ADSP-21061 is Table 12. Memory Read Bus Master The bus master asynchronously accesses the external memory space access mode. Note that the ACK, DATA, RD, WR, and DMAGx strobe timing parameters apply only to asynchronous access modes.

memory write bus master

Use these specifications to asynchronously connect to memory (and memory-mapped peripherals) without reference to CLKIN. When the ADSP-21061 is Table 13. Memory Write Bus Master The bus master asynchronously accesses external memory space access mode. Note that the ACK, DATA, RD, WR, and DMAGx strobe timing parameters apply only to asynchronous access modes.

Synchronous read and write bus master

Use these specifications to connect to external memory systems that require CLKIN relative timing, or to access slave ADSP-21061 (in the multiprocessor memory space). These synchronous switching features are also valid during asynchronous memory reads and writes, unless otherwise specified. When accessing the slave ADSP-21061, these switching characteristics must meet the timing requirements of the slave synchronous read/write. The slave ADSP-21061 must also meet (bus master) timing requirements for data and acknowledge setup and hold times.

Synchronous read and write bus slave

Use these specifications for ADSP-21061 bus master access to slave IOP registers or internal memory (in the multiprocessor memory space). The bus master must meet these (bus slave) timing requirements.

Multiprocessor Bus Requests and Host Bus Requests

Use these specifications to pass bus masters between multiprocessing ADSP-21061s (BRx) or host processors (synchronous and asynchronous).

Asynchronous read and write host to ADSP-21061

Use these specifications for asynchronous host processors to assert CS and HBR (low) at the host. After the ADSP-21061 returns to the HBG, the host can drive the RD and WR pins to access the ADSP-21061 memory or IOP registers. Assume that HBR and HBG this time is short.

Tri-state timing bus master, slave, HBR, SBTS

These specifications show how the memory interface can be disabled (stop driving) or enabled (resume driving) with respect to the CLKIN and SBTS pins. This timing applies to the bus master conversion cycle (BTC) and host conversion cycle (HTC) and SBTS pins.

DMA handshake

These specifications describe three DMA handshake modes. In these three modes, DMARx is used to initiate transfers. For handshake mode, DMAGx controls the locking or enabling of external data. For external handshake mode, data transfer is controlled by ADDR31–0, RD, WR, SW, PAGE, MS3–0, Table 20. DMA handshakes ACK and DMAGx signals. For Paced Master mode, data transfer is controlled by ADDR31–0, RD, WR, MS3–0, and ACK (not DMAG). For Paced Master mode, Memory Read-Bus Master, Memory Write Bus Master, and Read/Write Bus Master Timing Specifications for Synchronous ADDR31–0, RD, WR, MS3–0, SW, PAGE, DATA47–0, and ACK are also Be applicable.

serial port

To determine whether two devices can communicate at clock speed n, the following specifications must be confirmed: 1) Frame Sync Delay and Frame Sync Set and Hold, 2) Data Delay and Data Set and Hold, and 3) SCLK Width.

JTAG test access port and emulation

See Table 28 and Figure 26 for JTAG test access ports and emulation.

Test conditions

Output disable time

When output pins stop driving, go into a high impedance state, and begin to decay from the high or low voltage they output, they are considered disabled. The voltage decay time V on the bus depends on the capacitive load CL and the load current IL. This decay time can be approximated by the following equation:

As shown in Figure 27, the output disable time tDIS is the difference between tMEASURED and tDECAY. The time tMeasured refers to the time interval from when the reference signal is switched to when the output voltage decays ΔV from the measured output high voltage or output low voltage. tDECAY is calculated using the test loads CL and IL, and ΔV is equal to 0.5 V.

Output enable time

An output pin is considered enabled when it transitions from a high-impedance state to start driving. The output enable time, tENA, is the time interval from when the reference signal reaches a high or low voltage level until the output reaches the specified high or low trip point, as shown in the output enable/disable graph (Figure 27). If multiple pins are enabled (such as a data bus), the measurement is the measurement of the first pin to start driving.

System Hold Time Calculation Example

To determine the data output hold time in a particular system, first calculate tDECAY using the formula given above. V is chosen to be the difference between the output voltage of the ADSP-21061 and the input threshold of the device requiring hold time. A typical ∏V is 0.4 V. CL is the total bus capacitance (per data line) and IL is the total leakage or tri-state current (per data line). The hold time is tDECAY plus the minimum disable time (ie, tDATRWH for the write cycle).

Output drive characteristics

Figure 30 through Figure 37 show typical characteristics of the ADSP-21061 (5 V) and ADSP-21061L (3 V) output drivers. These curves represent the current drive capability and switching behavior of the output driver as a function of resistive and capacitive load.

capacitive load

Output delay and hold are based on standard capacitive loading: 50 pF on all pins (see Figure 28). For loads other than the 50 pF rating, the given delay and hold specifications should be derated by 1.5 ns/50 pF. Figure 31, Figure 32, Figure 35, and Figure 36 show how the output rise time varies with capacitance. Figure 33 and Figure 37 graphically show how output delay and hold vary with load capacitance. (Note that this graph or derating does not apply to output disable delay; see the previous section for output disable time under test conditions.) The graphs of Figure 31, Figure 32, Figure 35, and Figure 36 may not be outside the ranges shown linear.

environmental conditions

Thermal characteristics

The ADSP-21061 is available in a 240-lead thermally enhanced MQFP package. The top surface of the thermally enhanced MQFP contains a metal warhead from which most of the heat of the die is dissipated. The warhead is flush with the top surface of the package. Note that the metal slug is internally connected to GND through the device substrate.

The ADSP-21061L is available in 240-lead MQFP and 225-ball plastic BGA packages.

All packages are specified for one case temperature (TCASE). To ensure that TCASE is not exceeded, a heat sink and/or airflow source can be used. The heat sink should be attached with thermal adhesive.

TCASE = case temperature (measured on top of package)

ambient temperature

PD = Power Loss (W) (this value depends on the specific application; the method for calculating PD is shown under Power Loss).

θCA=value in the table below.

Dimensions

[1] Applies to three statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6 –1, TFSx, RFSx, TDO, EMU. (Note that in multiprocessor systems, when ID=001 and another ADSP-21061 does not request bus mastering, ACK is internally pulled up by 2 k during reset.)

[2] Fixed pins for three internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1. 7 for CPA pins.

[3] Applies to confirmation pin when pulled up. (Note that in multiprocessor systems, when ID=001 and another ADSP-21061L does not request bus mastering, ACK is internally pulled up by 2 k during reset).

[4] Applied to the acknowledgement pin when the keeper latch is enabled.

[5] Applies to all signal pins.

[6] Guaranteed but not tested.

[7] The test procedure used to measure I represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements using typical applications are less than specified.

[8] IDDINHIGH is based on a composite average of a series of highly active codes. IDDINLOW is based on a composite average of a series of low activity codes.

[9] IDDINLOW is based on a composite average of a series of low activity codes.

[10] Idle represents the ADSP-21061L state during execution of the Idle instruction.

[11] Idle16 indicates the state of the ADSP-2106x when the Idle16 instruction is executed.

[12] The test procedure used to measure I represents worst-case processor operation that is not sustainable under normal application conditions. Actual internal power measurements using typical applications are less than specified.

[13] IDDINHIGH is based on a composite average of a series of highly active codes. IDDINLOW is based on a composite average of a series of low activity codes.

[14] IDDINLOW is based on a composite average of a series of low-activity codes.

[15] Idle represents the ADSP-21061L state during execution of the Idle instruction.

[16] Idle16 represents the ADSP-21061L state during execution of the Idle16 instruction.

[17] Applied after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100µs, and the reset time is lower, assuming V and CLKIN are stable (not including the external clock oscillator start-up time).

[18] Only required if multiple ADSP-21061s must be synchronized from reset to CLKIN with the program counter (PC) equal. There is no need for multiple ADSP-21061s to communicate over a shared bus (via an external port) because the bus arbitration logic is automatically synchronized after reset.

[19] Refer to the falling edge of MSx, SW, BMS.

[20] ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronization specification tSAKC to de-assert ACK (low), all three specifications must meet ACK's assertion (high).

[21] For holdup calculations for a given capacitive and DC load, see Example System Holdup Calculations on page 43.

[22] tDACKAD is true only if the settling time (before CLKIN) of the address and switch inputs is greater than 10+DT/8 and less than 19+3DT/4. If the setup time of the address and input is greater than 19+3DT/4, then ACK is valid 14+DT/4(max) after CLKIN. A slave that sees an address with a matching M field will respond with an ACK, regardless of the state of MMSWS or strobes. Using tACKTR, a slave will return three states per cycle.

[23] CPA assertion must satisfy the setting of CLKIN; deassertion does not need to satisfy the setting of CLKIN.

[24] For the ADSP-21061L (3.3 V), this specification has a maximum value of 8.5–DT/8 ns.

[25] (O/D) = Open Drain, (A/D) = Active Drive.

[26] For the ADSP-21061L (3.3 V), this specification is 12 ns maximum.

[27] For ADSP-21061L (3.3V), this specification is 40+23DT/16ns (min).

[28] tVDATDGH is valid if DMARx is not used to delay read completion. If DMARx is used to stretch the read, then tVDATDGH = tCK – .25tCCLK – 8 + (n × tCK), where n is equal to the number of extra cycles to stretch the access.

[29] For holdup calculations for a given capacitive and DC load, see Example System Holdup Calculations on page 43.

[30] For ADSP-21061L (3.3V), this specification minimum is -1.0ns.

[31] For the ADSP-21061L (3.3V), this specification is 3.5ns minimum.

[32]MCE=1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.