Features

● High bandwidth: 150MHz (g u003d+2)

●+3V to+10V power operation

● Zero power disable (OPA635) [123) [123) ]

● The input range includes ground

● 4.8V output swing+5V power supply

● High output current: 80ma

123]

● Low input voltage noise: 5.6NV/√Hz

● Provide SOT23 packaging

Application

● 123] ● Single power video line drive

● Wireless LAN medium frequency amplifier

● Imaging channel CCD

● Low -power ultrasound

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123] OPA634 and OPA635 are high -speed amplifiers with low power consumption and voltage feedback. The design is designed for+3V or+5V single power supply voltage. It also supports running on ± 5V or+10V power supply. The input range is extended to the ground below the ground and within the 1.2V range of the positive power supply. Using complementary public emission pole output provides a ground with a output swing to 30 millivolo and a positive power supply of 140 millival. High -output -driven current, low difference gain, and phase error make it an ideal choice for single -power composite video cable.

High -gain bandwidth (140MHz) and conversion rate (250V/μs) ensure low distortion work, which makes OPA634 and OPA635 an ideal input buffer level for 3V and 5V CMOS converters. Unlike other low power consumption and single power computing amplifier, the discrete performance has been improved as the signal swing decreases.

Low 5.6NV input voltage noise supports wide dynamic range operation. The use of OPA635 high -speed disable lines can achieve multi -way reuse or system power reduction. By setting the disabled line to high, the power consumption can be reduced to zero.

OPA634 and OPA635 uses industry standard SO-8 packaging. OPA634 also has a super small SOT23-5 package, while OPA635 has SOT23-6. If you need lower power current and speed, consider OPA631 and OPA632.

Typical performance curve: vs u003d+5V

Unless otherwise explained, otherwise TA u003d 25 ° C, G u003d+2, RF u003d 750 , RL u003d 150 to vs/2 (see Figure 1).

Typical performance curve: vs u003d+3V

Unless otherwise explained, otherwise TA u003d 25 ° C, G u003d+2, RF u003d 750 , RL u003d 150 to vs/2 (see Figure 2).

Application information

Broadband voltage feedback operation

OPA634 and OPA6335 are unit gain stable stability , Very high -speed voltage feedback computing amplifier, designed for single power operation (+3V to+10V). The input level supports the input voltage lower than the ground and within the 1.2V range of the positive power supply. The complementary emission pole output level provides a positive power supply with an output swing to 30 millivolta and a 140 millival positive power. They are compensated to provide a wide range of resistance loads. OPA635's internal disable circuit design is used to minimize power currents when disabled.

FIG. 1 shows the AC coupling +2 gain configuration for+5V specifications and typical performance curves. For the purpose of testing, the input impedance setting is 50 and the resistor is grounded. The voltage fluctuation reported in the specification is directly measured at the input and output pin. For the circuit in Figure 1, the total effective load of high -frequency output is 150 | | 1500 Disable the tube foot is driven by low impedance sources, such as the CMOS inverter. 1.50k #8486 at the non -inverted input terminal provides a co -mode bias voltage. Their parallel combination is equal to the DC resistance at the inverter input (RF) to minimize DC offset.

FIG. 2 shows DC coupling +2 gain configuration for+3V specifications and typical performance curves. For the purpose of testing, the input impedance setting is 50 and the resistor is grounded. Although it is not a ""rail -to -orbit"" design in the strict sense, these components are very close while maintaining excellent performance. They will provide ≈2.8VP-P on a single+3V power supply of 70MHz bandwidth. The input level of 374 and 2.26k the resistor will change VIN to VOUT within the allowable output voltage range when Vin u003d 0. For information about driving capacitance loads, see the typical performance curve.

Single power ADC converter interface

The homepage shows a DC coupling, a single power ADC (modulus converter) drive circuit. Many systems now need the+3V power supply capacity of ADC and its drive. OPA635 provides excellent performance in this harsh application. Its large input and output voltage range, low distortion, supports converter, as shown in the AD shown in the figureS900. The design of the input level conversion circuit allows VIN to provide 1V to 2V output voltage for ADS900 between 0V and 0.5V. Both OPA635 and ADS900 have the same extreme power to reduce the tube foot, suitable for systems that require energy -saving.

DC level transformation

FIG. 3 shows a DC non -inverter amplifier, which will move the input level upward to adapt to the required output voltage range. Given the required signal gain (G), and when Vin is in the center of its range, the VOUT amount needs to be shifted ( #8710; vout). The following procedure gives the resistance value of the required performance. First set R4 between 200 and 1.5k .

Among them

ensure that VIN and Vout remain within the specified input and output voltage range.

Home Circuit is a good example of this application. When the+3V power supply is used, it is designed to obtain VIN between 0V and 0.5V and generates VOUT between 1V and 2V. This means g u003d 2.00, and #8710; vout u003d 1.50V 0.25V u003d 1.00V. Insert the above equation (R4 u003d 750 ) to get: ng u003d 2.33, R1 u003d 375 , R2 u003d 2.25K , R3 u003d 563 The resistor is changed to the closest standard value.

Reduced the peak non -inverter bastard

FIG. 4 shows a non -inverse placed large device that can reduce the peak value when low gain. The resistor RC compensates OPA634 or OPA635 to obtain higher noise gain (NG), thereby reducing the peak of AC response without changing the DC gain (usually 5DB at G u003d+1, no RC). VIN must be a low -impedance source, such as operational amplifier. The resistance value is low to reduce noise. The use of RT and RF can help minimize parasitic impedance.

The noise gain can be calculated as follows:

The unit gain buffer can be selected by selecting RT u003d RF u003d 20.0 # 8486; and RC u003d 40.2 (Do not use RG) to design. The noise gain is 2, so its response is similar to the characteristic curve of G u003d+2. Reduce RC to 20.0 increase the noise gain to 3, which usually provides a flat frequency response, but the bandwidth is small.

The circuit in FIG. 1 can be redesigned, and the noise gainIncrease to 3 to reduce peak values. This is achieved by adding RC u003d 2.55k

Design Tool

Demonstration board

There are two PC boards that can be used in three packaging styles to use OPA634 and OPA635 to help preliminary assessment of circuit performance. These are free of charge, as described as an unpopular personal computer board. The summary information of these circuit boards is shown in Table 1.

Operation suggestion

Optimized resistance value

Because OPA634 and OPA635 are voltage feedback computing amplifiers, feedback and gain setting resistors can be used in resistors. A wide range of resistance. The main limitations of these values u200bu200bare set by dynamic range (noise and distortion) and parasitic capacitors. For non -counter -phase unit gain followers, the feedback connection should be 20 resistors, not direct short circuit (see Figure 4, RG u003d ∞). This will beolate reverse input capacitors and output pins, and improve frequency response flat. When the feedback resistance is less than 1.5kΩ, the additional feedback resistance will reduce the network performance of 1.5kΩ. When more than 1.5k typical parasitic capacitors (about 0.2pf) on the feedback resistance may cause the non -due frequency restrictions of the amplifier response.

A good rule of experience is to set the parallel combination of RF and RG (Figure 1) to less than 400 . The combination impedance RF | RG interacts with the inverter input capacitor, and places an additional pole in the feedback network to set zero answers in the front. Assuming a 3PF parasitic on the reversal node, keeping the radio frequency RG LT; 400 it will keep the magnetic pole above 130MHz. As far as it is concerned, this constraint means that the feedback resistance RF can increase to several K under high gain. As long as any parasitic capacitance that appears in the magnetic pole that is formed by RF is not within the frequency range of interest, this is acceptable.

Bandwidth and gain: Non -reversing operation

As the signal gain increases, the closed bandwidth of the voltage feedback Territories gradually decreases. Theoretically, this relationship is described as a width bandwidth (GBP) displayed in the specification. Ideally, GBP except for non -reincarnation signal gain (also known as noise gain, or NG) will predict a closed -loop bandwidth. In fact, it was established when the phase hameness is close to 90 °, just like in a high -gain configuration. At low gain (increase feedback factor), most amplifiers will show a complicated response of lower phase margin. Compensation for OPA634 and OPA635 to generate a minor peak response in the absence of non -reverse phase gain (Figure 1). This has led to a typical +2 bandwidth gain of 150MHz, far exceeding the 140MHz GBP Except the gain of 2 predictions. Increasing gain will make the phase margin close to 90 °, and the bandwidth is closer to the predicted value (GBP/NG). When the gain is +10, the 16MHz bandwidth displayed in the typical specifications is close to using simple formulas and typical GBP forecast bandwidth.

Compared with the+5V power supply, OPA634 and OPA635 showed the smallest bandwidth reduction under the operation of+3V single power operation. This is because when the total power supply voltage between the power pins changes, the internal offset control circuit maintains almost constant static current.

Reverse amplifier operation

Since OPA634 and OPA635 are general broadband voltage feedback amplifiers, all familiar computing amplifiers application circuits are available for designers. Figure 5 shows a typical inverter configuration. The input/output impedance and signal gain in Figure 1 retain the configuration of the inverter circuit. Reversal operation is a more common requirement and provides several performance advantages. The reversal structure shows the improvement rate and distance of improvement. It also allows input to bias to VS/2 without any net empty problem. The output voltage can move independently to the coupling capacitor within the output voltage range, or the bias adjustment resistance.

In the reverse configuration, you must pay attention to three key design considerations. First, the gain resistance (RG) becomes part of the input impedance of the signal channel. If you need to input impedance matching (when the signal is coupled when the signal is coupled by cable, twisted pad, long PC board wire or other transmission wire conductors, this is beneficial), you can set the RG to The required gain. This is the easiest way to get the best bandwidth and noise performance. However, at low reverse gains, the feedback resistance value generated will generate important loads for the output of the amplifier. For the reverse gain of 2, set RG to 50 for input matching, no RM, but 100 feedback resistor. This has an interesting advantage, that is, for the 50Ω source impedance, the noise gain is equal to 2, which is the same as the above non -inverse circuit. However, now the amplifier output will see 100 feedback resistors are connected in parallel with external loads. Generally, the feedback resistance should be limited to the range of 200 to 1.5k In this case, it is best to increase the RF and RG values, as shown in Figure 5, and then use the third resistor (RM) ground to achieve the input matching impedance. The total input impedance becomes a parallel combination of RG and RM.

The second main consideration mentioned in the previous paragraph is that signal source impedance becomes part of the noise gain equation, which affects the bandwidth. For the examples in FIG. 5, the RM value and the external 50 source impedance (under high frequency) parallel combination to generate 50 | | 576 u003d 26.8 This impedance is connected in series with RG, useCalculate noise gain. The result of FIG. 5 is 2.87, and if the RM can be eliminated as mentioned above, only 2.87. Therefore, the bandwidth of the circuit (NG u003d+2.87) with an gain in Figure 5 will be lower than the bandwidth of the +2 circuit in Figure 1 to the +2 circuit.

The third important consideration in the design of the inverter amplifier design is to set the bias current to eliminate the resistor at the non -inverter input terminal (RT u003d 750 parallel combination). If the resistance is set to the total DC resistance from the inverter node, the output DC error caused by the input bias current will be reduced to (input offset current) by RF. When the DC lock capacitor is connected with RG, the DC power supply impedance in the reverse mode shown in Figure 5 is only RF u003d 750 In order to reduce the additional high -frequency noise introduced by resistance and power feeder, RT is bypass by a capacitor. As long as RT LT; 400 its noise contribution is the smallest. As the minimum requirements, OPA634 and OPA635 need a 50 RT value to inhibit the peak of parasitic induced-non-inverse input direct-to-ground short circuit will lead to very high frequency instability in the input level.

Output current and voltage

OPA634 and OPA635 provide excellent output voltage capabilities. Under the empty load conditions of+25 ° C, the fluctuation between the output voltage and the power rail is usually less than 140mV; the guarantee of the guarantee is within the 300mv range of any power rail (vs u003d+5V).

The minimum output voltage and current specifications are set at the coldest temperature limit through the worst case. Only when the cold starts, the output current and voltage will be reduced to the value shown in the guarantee table. When the output transistor provides power, their knot temperature will increase, reducing their VBE (increasing the available output voltage swing) and increasing current gain (increased output current). In the steady -state operation, because the output stage temperature will be higher than the lowest working environment temperature, the output voltage and current can always be greater than the value shown in the ultra -temperature specification.

In order to maintain the maximum output level linearity, it does not provide short -circuit protection. This is usually not a problem, because most applications include a series matching resistor on the output end. If the output end of the resistor is short -circuited, it will limit the internal power consumption. However, in most cases, the output pin is directly connected to the adjacent positive power supply foot (8 pins packaging) will damage the amplifier. If you need additional short -circuit protection, consider a small string of connected resistors in the power cord. This will reduce the available output voltage swing under the overput load.

Drive capacitance load

For the operational amplifier, the most demanding and most common load conditions are the capacitor load. Generally, the capacitance load is the input of ADC, including additional external capacitors, which may be recommended to improve the linearity of ADCEssence High -speed and high -open -rings gains like OPA634 and OPA635, when the capacitance load is directly applied to the output pins, its stability and closed -loop response peak value is very easy to reduce. When the main consideration is frequency response flat, pulse response and/or distortion, the simplest and most effective solution is to insert a series isolation resistance between the output and capacitance load between the amplifier and the capacitance load. Sexual load is separated from feedback ring.

The typical performance curve shows the recommended RS and the frequency response generated by the recommended RS and the capacitance load and the frequency generated under the load. Parasitic capacitance loads greater than 2PF will begin to reduce the performance of OPA634 and OPA635. The long PC board trajectory, unsatisfactory cables, and connection with multiple devices are easy to exceed this value. Always consider this impact carefully, and add a recommended series resistor (see the circuit board layout guide) as close as possible to the output pins.

The standard for setting the RS resistor is the maximum bandwidth and flat frequency response at the load. When the gain is +2, the frequency response at the output pins has slightly reached its peak without a capacitance load, and a relatively high RS value is required to flatten the response under flat load. Increasing noise gain will also reduce peak values u200bu200b(see Figure 4).

distortion performance

OPA634 and OPA635 have good distortion performance under 150 load. Compared with other solutions, it provides excellent performance on lighter load and/or on single+3V power supply. Generally speaking, the second harmonic will dominate the distortion before the base wave signal reaches a very high frequency or power level, and the three harmonic components can be ignored. Then focus on the second harmonic to increase the load impedance directly to improve the distortion. Keep in mind that the total load includes the feedback network; in the non -reverse configuration (Figure 1), this is the sum of RF+RG, and in the reverse configuration, you only need to load the RF with the actual load.

Noise performance

High conversion rate, stable unit gain, voltage feedback computing amplifier usually input noise voltage at a high cost. However, the 5.6NV/√Hz input voltage noise of OPA634 and OPA635 is far lower than that of similar amplifiers. Enter the reference voltage noise, and the two input reference current noise items (2.8Pa/√Hz) can provide low output noise under various working conditions. Figure 6 shows the noise analysis model containing all noise items. In this model, all noise items are considered noise voltage or current density items, and the unit is NV/√Hz or PA/√Hz.

The total output spots noise voltage can be calculated as a square root of all square output noise voltage contributors. Formula 1 shows the general form of the output noise voltage of the term shown in Figure 6:

The table willExcept for noise gain (NG u003d (1+RF/RG)), the reference input point noise voltage at the equivalent input point at the non -inverter input is obtained. 123] Evaluate the two equations of the circuit and component value shown in Figure 1, and will get the total output point noise voltage of the total output point of 12.5NV/√Hz and the total effect input point noise voltage of the total effect input point of 6.3NV/√Hz. This includes noise increased from the resistor. This total input refers to the noise of the noise in terms of the voltage noise of the amplifier, the voltage is not higher than 5.6nv/√Hz. As long as the impedance restrictions appearing at the input end of each operation amplifier are limited to the maximum value of 400 and the input attenuation is very low, this will occur.

DC accuracy and offset control

The balance input stage of broadband voltage feedback amplifier allows good DC output accuracy in various applications. Compared with similar products, the power current of OPA634 and OPA635 provides stricter control. Although high -speed input levels do require relatively high input bias current (usually 25 μA per input terminal), the tight matching between them can be used to reduce the output DC error caused by the current. This is achieved by matching the DC source resistance that appears at two inputs. Use the worst case+25 ° C input offset voltage and current specifications, evaluate the configuration of Figure 1 (its matched DC input resistance), and obtain the output offset voltage in the worst case is equal Non -inverse signal gain)

Generally, you need to fine -tune the output offset or DC working point adjustment. There are many technologies to introduce DC offset control in the computing amplifier circuit. Most of these technologies are based on DC current feedback. When selecting the method of mitigation and fine -tuning, a key consideration is the effect on the frequency response of the expectation signal path. If the signal path is to avoid the interaction with the signal source, the offset control is best as a reverse search and signal application. If the signal path is reversed, you can consider the offset control of the input application of non -turbulent input. The DC bias current is introduced into the inverter input node by the resistance value of much significant channel resistance. This will ensure that the regulatory circuit has the minimum effect on the width gain and frequency response.

Disable operation

OPA635 provides a disabled feature that can be used to reduce system power or realize simple channel reuse operations. To be disabled, the control pin must be assertive. Figure 7 shows the simplified internal circuit of the disable control function.

In normal operation, through 50K the resistor provides the base current to Q1.

A key parameter in the disable operation is the output failure when switching to the disable mode.

The transition of the DIS control lineThe edge rate (DV/DT) will affect the failure. Adding a simple RC filter from a high -speed logic line to the DIS tube foot will reduce the failure. If you use extremely fast conversion logic, 1K series resistors will use only parasitic input capacitors on the DIS pin to provide sufficient bandwidth limit, and at the same time still ensure sufficient logical level swing.

Hot analysis

Maximum expectations will set up the maximum internal power consumption, as described below. In any case, the highest knot temperature must not exceed 175 ° C.

The working knot temperature (TJ) is given by TA+PD θJa, that total internal power consumption (PD) is the additional power consumed by static power (PDQ) and output (PDL) consumption And, to provide load power. Static power is the specified air supply current multiplication by the total power supply voltage of the entire component. PDL will depend on the required output signals and loads, but for the resistance load connected to the intermediate power supply (VS/2), when the output is fixed at a voltage equal to VS/4 or 3VS/4, the PDL will be at the maximum value. Under this condition, PDL u003d vs2/(16 RL), where RL includes feedback network load.

Note that the power consumption of the internal power is the output level, not the load.

As the worst case, the maximum TJ is calculated using the OPA635 (SOT23-6 package) in Figure 1 circuit. Drive 150 load.

Although this is still far lower than the highest prescribed temperature, due to system reliability considerations, lower guarantee temperature cordon may be required. If the load is required to force the current output at a high output voltage, or obtain the current from the output end at a low output voltage, the highest internal loss may occur. This allows high current through a large internal voltage drop in the output transistor.

Circuit plate layout guide

To obtain the best performance and high -frequency amplifier, such as OPA634 and OPA635 need to pay close attention to board layout parasites and external component types. Suggestions for optimization include:

A) Solid the placement of all signal input/output pins of parasitic capacitors. Parasitic capacitors on the output and reverse input terminals will cause instability: at the non -switching input terminal, it will react with the source impedance, resulting in unintentional bandwidth limit. In order to reduce unnecessary capacitors, a window should be opened on all the ground and power plane around the signal I/O pins. Otherwise, the ground and power aircraft should remain complete elsewhere.

B) Short the distance from ( lt; 0.25 "") from power pins to high frequency 0.1 μF decoupling capacitors. At the equipment pinNear signal input/output pin. Avoid narrow power and ground traces to minimize the inductance between the pin and the decoupling capacitor. Each power connection should always be disconnected with one of the capacitors. The optional power supply -coupled capacitors (0.1 μF) (for bipolar operations) between the two power supply will improve the 2ndharmonic distortion performance. The large (2.2 μF to 6.8 μF) decoupling capacitors should be used on the main power. It is valid at a lower frequency. These can be placed in a slightly far away from the device and can be shared between multiple devices in the same area of u200bu200bthe PC board.

C) Careful selection and placing external components will maintain high frequency performance. The resistor should be a very low type of electric resistance. The surface installation resistance work best and allow more compact overall layout. The metal film or carbon component axial leading resistor can also provide good high -frequency performance. Similarly, keep their wires and PC traces as short as possible. Do not use a wire winding resistor in high -frequency applications. Because the output pins and inverter input pins are the most sensitive to the parasitic capacitance, the feedback and series output resistors (if there are) should be as close to the output pin as much as possible. Other network components, such as non -inverse input terminals, should also be placed near the package. If the double -sided component is allowed, the feedback resistor is placed directly below the encapsulation of the other side of the circuit board, which is located between the output and reverse input pins. Even if the low -parasitic capacitor is diverted from the external resistance, the high resistance value will generate significant time constant, thereby reducing performance. A good axial metal membrane or surface installation resistor is about 0.2pf when connecting with the resistor. For the resistance value gt; 1.5k , the parasitic capacitor will add one pole and/or zero to less than 500MHz, which will affect the circuit operation. Keep the resistance value as low as possible to meet the consideration of load driving. 750 feedback is a good starting point for design

and other broadband devices can be used on the connection board of the design. In the next step, the capacitance load is the total load of the set. A relatively wide trace line (50 to 100 mils) should be used, and it is best to open the ground and power aircraft around it. It is estimated that the total capacitance load is estimated, and RS is set according to the typical performance curve ""Recommended RS VS capacitance load"". Low parasitic capacitance load ( lt; 5PF) may not require RS, because OPA634 and OPA635 are named compensation, and can work under the 2PF parasitic load. When the signal gain increases (increasing the load phase margin), if a long trace line is required, and the 6DB signal loss inherent in the double -end transmission line is acceptable, it allows a higher parasitic capacitor load of RS without RS, and uses micro -bands to use micro -bands. The line or strip -like wire technology implements the matching impedance transmission line (see the ECL design manual of the microstructure and the line layout technology). 50 environment does not need to be on the ship. In fact, a higher impedance environment will improve distortion, such as distortion and load charts. Be determinedIn the case of a characteristic circuit board tracking impedance (based on circuit board materials and trace lines), the matching series resistance from OPA634 and OPA635 to tracking, as well as the use of end -connected diversion resistors at the target equipment input end. It is also necessary to remember that terminal impedance will be a parallel combination of parallel resistance and target equipment input impedance; total effective impedance should be set to match the tracking impedance. If the 6DB attenuation of the dual -end transmission line is unacceptable, the long record can only be connected in series at the source end. In this case, the trajectory is regarded as a capacitance load and sets a series resistance value according to the typical performance curve ""recommended RS VS capacitance load"". This will not be able to maintain signal integrity and dual -end lines. If the input impedance of the destination device is low, due to the pressure of the sterilizer formed by the series output to enter the terminal impedance, there will be some signal attenuation.

E) It is not recommended to put high -speed parts. The additional drawing length of the socket and the capacitance between the tube feet will produce very t