The ISL6742 is a high performance double-ended pulse width modulation with advanced synchronous rectifier control and current limiting features. It is suitable for current and voltage mode control methods. The ISL6742 includes Synchronous Rectifier (SR) control. The supplemental output can be relative to the main output using an external control voltage. Its advanced current sensing circuit uses a sample and hold method to provide an accurate average current signal. Common coda current limiting methods that are applicable to average current limiting techniques that virtually eliminate peak currents are also applicable to current sharing circuits and average current mode control. This advanced BiCMOS design features an adjustable oscillator frequency up to 2 MHz, internal thermal protection, precise dead-time control and short propagation delays. Additionally, multi-pulse suppression ensures alternate outputs of pulses that may skip pulses at low duty cycles.

notes:

1. Add "-T" suffix for tapes and reels. See TB347 Reel Specifications for details.

2. These Intersil lead-free plastic packaged products feature a special lead-free material set, molding compound/mold connection material, and 100% matte tinplate plus annealing (e3 finish, i.e. RoHS compliant, with SnPb and lead-free soldering compatible operation). Intersil's lead-free products are classified as lead-free as MSL that meets or exceeds the lead-free peak reflow temperature IPC/JEDEC J STD-020 requirements.

3. For Moisture Sensitivity (MSL), see page of Product Information ISL6742. For more information on MSL, see Technical Brief Type TB363

feature

Synchronous rectifier control output with adjustable delay/advance

Adjustable Average Current Signal

3% Tolerance Cycle Peak Current Limit

Fast current sense output delay

Adjustable oscillator frequency up to 2 MHz

Adjustable dead time control

Voltage or Current Mode Operation

For voltage feedforward or current mode applications

Line, Load and Temperature

175µA starting current

Supply UV

Adjustable soft start

70ns leading edge blanking

multipulse suppression

Internal overheat protection

Lead Free (RoHS Compliant)

application

Half-Bridge, Full-Bridge, Crossover Forward and Push-Pull Converters

Telecom and Datacom Power Supplies

Wireless base station power supply

file server power

Industrial Power Systems

Absolute Maximum Ratings (Note 5) Thermal Information

Supply voltage, VDD. Ground -0.3V to +20.0V

Export. Ground -0.3V to VDD

signal pin. Ground -0.3V to VREF+0.3V

VREF. Ground -0.3V to 6.0V

Peak gate current. 0.1 Amp

operating conditions

temperature range. -40°C to +105°C

Supply voltage range (typical). 9VDC to 16Vdc

Thermal Resistance Connection to Ambient (Typical) θJA (°C/Watt)

16-lead QSOP (Note 4). 100

maximum junction temperature. -55°C to +150°C

Maximum storage temperature range. -65°C to +150°C

Lead free reflow profile. see TB493

NOTE: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to these conditions may adversely affect product reliability, resulting in failures not covered under warranty.

notes:

4. In free air, measure JA with components mounted on a high-efficiency thermal conductivity test board. See Technical Bulletin TB379 for details.

5. All voltages are related to ground.

Operating conditions recommended by electrical codes unless otherwise stated. See Figures 1, 2 and 3. 9V 20V, RTD=10.0kΩ, CT=470pF, TA=-40°C to +105°C, TA=+25°C typical.

Operating conditions recommended by electrical codes unless otherwise stated. See Figures 1, 2 and 3. 9V

notes:

6. Unless otherwise specified, parameters with minimum and/or maximum limits are 100% tested at +25°C. Temperature limits determined by characterization are also not production testing.

7. Limits determined by characterization, no production testing.

8. This is the maximum duty cycle achievable using the specified values of RTD and CT. Additional values for these components can be obtained with larger or smaller maximum duty cycles using the following methods. See equations 1 to 3.

9. Adjust VDD below the UVLO stop threshold before setting to 7V.

10. When OUTx is delayed relative to OUTLxN (VADJ<2.425V), the delay time set by VADJ should not exceed 90% of CT discharge time (dead time) determined by CT and RTD.

Pin Description

VDD—VDD is the power supply connection for the integrated circuit. To optimize noise immunity, bypass VDD to GND with 0.1µF or higher frequency ceramic capacitors as close to the VDD and GND pins as possible. Monitors the VDD supply voltage for under-voltage lockout (UV). The start and stop thresholds track each other resulting in a relatively constant hysteresis. GND—The signal and power ground connections for this device. A low impedance layout is necessary due to high peak currents and high frequency operation. Traces are strongly recommended for ground planes and shorts. VREF - 5V reference voltage output with 3% tolerance over line, load and operating temperature. Bypass to ground with a 0.1 to 2.2µF low ESR capacitor. CT-Oscillator timing capacitor connected at pin and ground. It is charged by an internal 200µA current and discharged with a user-adjustable current source controlled by the RTD. RTD - This is the oscillator timing capacitor discharge current control pin. The current flowing in the connected resistor between this pin and GND determines the CT discharge current. The CT discharge current is nominally 20 times the resistor current. The PWM dead time is determined by the duration of the timing capacitor discharge. The voltage at this RTD is nominally 2V. The recommended minimum RTD value is 2.00kΩ. This is the overcurrent comparator and average current sample and hold circuit. The overcurrent comparator threshold is set to 1V nominal. The CS pin is any one of the PWM outputs shorted to ground. Input resistors may be required depending on the impedance of the current sensing source, due to the internal clock and external power switches. This delay may have caused the CS to discharge equipment that was shutting down before the power switch. OUTA and OUTB - These paired outputs are the alternating sequence of modulated outputs of the pulse width controlled switch fet. OUTAN and OUTBN - These outputs are OUTA and OUTB respectively. These outputs are suitable for the control of synchronous rectifiers. The phase relationship between each output and its complement is set by a control to set the voltage applied to VADJ. VADJ - The 0V to 5V control voltage applied to this input sets OUTA/OUTB and Bund/Bund.

Voltages below 2.425V will cause OUTAN/OUTBN to be advanced relative to OUTA/OUTB. Voltages above 2.575V cause OUTAN/OUTBN to be delayed relative to OUTA/OUTB. When the voltage is 2.50V±75mV, the phase difference is zero. A weak internal 50% divider and VREF result in no phase delay if this input is floating. The phase delay/advance range is 0 or 40ns to 300ns, and the phase difference increases with voltage and the deviation from 2.5V increases. The relationship between control voltage and phase difference is nonlinear. The gain (Δt/ΔV) is low as the control voltage approaches 2.5V and quickly approaches the control range as the voltage approaches. This behavior enables the designer to be more accurate when choosing shorter delay/advance durations. When the PWM output is delayed relative to the SR output (VADJ < 2.425V), the delay time should not exceed the dead time determined by RTD and CT. IOUT - The output of the sample 4x buffer amplifier holds the circuit that captures and averages the CS signal. Ramp - This is the input PWM comparator for the sawtooth wave. Ramp pin at the termination of the PWM signal. A sawtooth voltage waveform is required at this input. For current mode control, this pin is directly connected to CS and the current loop feedback signal is applied to both inputs. For voltage mode controlled oscillators the sawtooth wave can be buffered and used to generate the appropriate signal, or the ramp can be connected to the input voltage forward control through an RC network, or the ramp can be passed through an RC network that produces the desired sawtooth wave. FB-FB is the inverting input of the error amplifier (EA). This amplifier can be used as voltage error amplifier feedback or as an average current limiting amplifier (IEA). If an amplifier is not used, FB should be grounded. The VERR-VERR pin is the output of the error amplifier controlling the inverting input of the PWM comparator. A feedback compensation element is connected between VERR and FB. There is a nominal 1mA pull-up current source connected to Vil. Soft start is used as the VERR signal. when VERR is pulled below 0.6V. OUTAN and OUTBN The complement of OUTA and OUTB respectively reaches 100% of the duty cycle when this occurs. SS - Connect a soft-start timing capacitor across this pin to control the soft-start duration. The value of the capacitor determines the rate of increase of the duty cycle during startup. Although a minimum value of capacitance is not required, a value of at least 100pF is recommended for noise immunity. SS can also be used to suppress the output by grounding it through a small transistor configuration in the collector/drain.

Function description

feature

The ISL6742 PWM is the best choice for low cost bridges where precise duty cycle and dead time control is required. There are many safeguards to control the function, a highly flexible design with minimal external components is possible. Its many features include current or voltage mode control, adjustable soft-start, peak and average overcurrent protection, thermal protection, synchronous rectifier output timing with variable delay/advance and adjustable oscillator frequency. Oscillator ISL6742 oscillator, with programmable frequency range setting to 2 MHz, with only one external resistor and capacitor. The switching period is the sum of the timing capacitor charge and discharge time. Charge time is determined by CT and a fixed 200µA internal current source. The duration of discharge was determined by RTD and CT.

where tC and tD are the charge and discharge times, tSW is the oscillation period, and fSW is the oscillator frequency. Because the Island 6742 is a double-ended controller, two oscillator cycles are required for one output switching cycle. Actual charge and discharge times will be slightly longer due to internal propagation delays of approximately 10ns/transition. This delay directly increases the switching duration, but also causes the timing capacitor peak-to-valley voltage threshold, effectively increasing the peak-to-peak voltage across the timing capacitor. Also, if a very low discharge current is used, the error will increase due to the input impedance of the CT pin. The maximum duty cycle D and the percentage of dead time (DT) can be calculated as:

soft start operation

The ISL6742 has a soft-start function using an external capacitor connected to an internal current source. Soft-start reduces component stress and inrush current during startup. At start-up, the soft-start circuit limits the error voltage input (VERR) to a value equal to the soft-start voltage. This output pulse width increases as the soft-start capacitor voltage increases. This increases the duty cycle to zero to adjust the pulse width during soft-start. When the soft-start voltage exceeds the error voltage, the soft-start is complete. Soft-start occurs during startup and after recovery from a fault state. The soft-start charge cycle may be calculated using Equation 6:

where t is the charge cycle in ms and C is the soft-start capacitor (in μF). The soft-start duration power supply will be less than or equal to this value, depending on when the feedback loop controls. The soft-start voltage is clamped to 4.50V with a 2% tolerance. Suitable for "soft start" if the current is well below the 70µA charge current. Use the SS pin as disable to suppress the output input. Pull SS below 0.27V and all outputs will go low. An open collector/drain configuration can be used to connect a signal that disables the SS pin. The output of the gate drive ISL6742 is capable of sourcing and sinking 10mA (nominal VOH, VOL) for use in combination with integrated FET drivers or discrete bipolar totem pole drivers. The typical on-resistance of the output is 50Ω. Overcurrent Operation Two overcurrent protection mechanisms are available for power supply design. The first method is cycle-by-cycle peak overcurrent protection, which provides fast response. This second method is a slower averaging method that produces constant current or "brick wall" current limiting behavior. The IF voltage mode uses controlled, average overcurrent protection to maintain the flux balance of the transformer by maintaining the load cycle symmetry between half cycles. The current sense signal applied to the CS pin is connected to the peak current comparator and the sample and hold averaging circuit. After a 70ns leading edge blanking (LEB) delay, the current sense signal is actively sampled during turn-on to determine the average current of the cycle, which is amplified by a factor of 4 and output to the output pins. If the RC filter is placed at the CS input, its time constant should not exceed about 50ns or significant errors may be introduced on IOUT

Figure 8 shows the CS signal and under steady state conditions. IOUT is Counter Strike. Figure 9 shows the dynamic behavior of the current averaged circuit wave when CS is externally sinusoidally modulated. Note that IOUT is updated by the sample and hold circuit at the end of the active output pulse.

The average current signal on IOUT remains accurate. The output inductor current is continuous (CCM operation). Once the inductor current becomes discontinuous (DCM operation), IOUT represents 1/2 the peak inductor current greater than the average current. This happens because the hold circuit only activates the loop when the switch is on. When the inductor current reaches zero off time. If average overcurrent limiting is required, IOUT can be combined with the available error amplifier of the ISL6742. Typically, IOUT is broken down and filtered as needed to achieve the desired amplitude. The resulting signal is input to the current error in-amplifier (IEA). The IEA works with most PWM controllers except that it cannot supply current. Instead, VERR has a separate internal 1mA pull-up current source. Use the internal 0.6V reference voltage. The voltage applied at FB is integrated with respect to the 0.6V reference voltage. The resulting signal, VERR, is applied to the sawtooth voltage on the ramp. If FB is less than 0.6V, the IEA will be open loop (no current can be produced), VERR will be at a level determined by the voltage loop, and the duty cycle will be unaffected. As the output load increases, the output will increase and the voltage applied to FB will increase until it reaches 0.6V. At this point, the IEA will lower VERR as needed to keep the output current at the 0.6 volt reference. When the output current falls below the average current limit threshold again, the IEA returns to open loop condition and the duty cycle is again looped by the voltage. The average current control loop behaves like the voltage control loop in a typical power supply, except it regulates current instead of voltage. The EA available on the ISL6742 can also be used as the voltage EA for the voltage feedback control loop instead of the current EA as described earlier. An external op amp can be used as a current or voltage EA supply that does not allow the circuit to feed current into VERR. The external EA must only sink current, which can be achieved by connecting a diode in series with its output. The 4x gain of the sample-and-hold buffer allows 150mV to 1000mV peaks on the CS signal, depending on the resistor divider placed on the interface. The total bandwidth of the average current loop is determined by the integrated current EA compensation and divider on IOUT.