Features and Benefits

▪ N-channel MOSFET full bridge high current gate driver

▪ High side or low side PWM switch

▪ Charge pump operating at low supply voltage

▪ 100% PWM top-up charge pump

▪ Cross-conduction protection with adjustable dead time

▪ 5.5 to 50 V supply voltage range

▪ Integrated 5V regulator

▪ Diagnostic output

▪ Low current sleep mode

illustrate

The A3941 is a full-bridge controller for external N-channel power mosfet and is designed for automotive applications with high power inductive loads such as brushed DC motors.

A unique charge pump regulator provides full (>10V) gate drive with battery voltage as low as 7V and allows the A3941 to operate with reduced gate drive, down to 5.5V.

The bootstrap capacitor is used to provide the above battery supply voltage required by the N-channel mosfet. An internal charge pump driven on the high side allows DC (100% duty cycle) operation.

The full bridge can be driven in fast or slow decay mode using diodes or synchronous rectification. In slow decay mode, current recirculation can pass through the high-side or low-side FETs. Power FETs prevent shoot-through with resistor-tunable dead time.

Integrated diagnostics provide undervoltage, overtemperature and power bridge fault indication and can be configured to protect the power mosfet under most short circuit conditions.

The A3941 is powered from a 28-pin TSSOP power pack with exposed thermal pads (suffix LP). This package is lead free, 100% matte tin plated lead frame.

Functional block diagram

Timing diagram

Function description

The A3941 is a full-bridge MOSFET driver (pre-driver) that requires a single unregulated supply from 7 to 50 volts. It includes an integrated 5V logic power regulator.

Four high-current gate drivers are capable of driving a wide range of N-channel power MOSFETs and are configured as two high-side and two low-side drivers. The A3941 provides all the necessary circuitry to ensure that the gate-source voltage of the high-side and low-side external FETs is above 10 V for supply voltages below 7 V. For extreme battery drop conditions, operation is guaranteed with supply voltages below 5.5 V but with reduced gate drive voltages.

The A3941 can be driven by a single PWM input from a microcontroller and can be configured for fast or slow decay. Fast decay provides four-quadrant motor control, while slow decay is suitable for two-quadrant motor control or simple inductive loads. In slow decay, current recycling can be through the high-side or low-side mosfet. In either case, synchronous rectification can improve bridge efficiency. Cross-conduction (shoot-through) in external bridges can be avoided with adjustable dead time.

A low-power sleep mode allows the A3941, power bridge, and load to remain connected to vehicle battery power without the need for additional power switches.

The A3941 includes many protection functions against undervoltage, overtemperature and power bridge faults. The fault condition enables the device or external controller to respond, depending on the fault condition and logic settings. Two fault flag outputs, FF1 and FF2, are provided for signaling detected faults to an external controller.

power supply

A single power supply needs to be connected to the VBB pin through a reverse voltage protection circuit. The power supply should be separated from the ceramic capacitor connected near the VBB and ground pins.

The A3941 works within the specified parameters, the VBB power supply is from 7V to 50V, and the supply voltage drops to 5.5V, and it works fine. This provides a very robust solution for use in harsh automotive environments.

The 5V low current supply for the external pull-up resistor on the V5 pin is provided by the integrated 5V regulator. This regulator is also used by the internal logic and must be disconnected through a capacitor of at least 100 nF between the V5 pin and GND. When reset is held low, the 5 V regulator is disabled.

door driver

The A3941 is designed to drive external low on-resistance, power N-channel MOSFETs. It provides the large transient current required to rapidly charge and discharge the gate capacitance of the external FET to reduce losses in the external FET during switching. Charge and discharge rates can be controlled by external resistors in series with the FET gates.

Gate Drive Voltage Regulation The gate driver is powered by an internal regulator that limits the supply to the driver, thereby limiting the maximum gate voltage. When the VBB supply is greater than 16v, the regulator is a simple linear regulator. Below 16V, the regulated power supply is maintained by a charge pump boost converter that requires a pump capacitor connected between the CP1 and CP2 pins. This capacitor must have a minimum value of 220 nF, typically 470 nF.

A regulated voltage of nominally 13 V is available on the VREG pin. A large enough storage capacitor must be connected to this pin to provide transient charging current to the low-side driver and bootstrap capacitor.

Top up charge pump An additional top up charge pump is provided for each stage. The charge pump allows the high-side driver to maintain the gate voltage on the external FET indefinitely, ensuring so-called 100% PWM if required. This is a small current trickle charge pump that only works after the high-side FET is turned on by a signal. The floating high-side gate drive requires a small bias current (<20µA) to keep the output high. Without a top-down charge pump, this bias current would be drawn from the bootstrap capacitor through the Cx pin. The charge pump supplies enough current to ensure the bootstrap voltage so that the gate-to-source voltage remains at the necessary level.

Note that the charge required for the initial power-up of the high-side gate is always provided by the bootstrap capacitor. If the bootstrap capacitor is discharged, the charge pump on top will not be able to provide enough current to turn the FET on.

In some applications, a safety resistor is added between the gate and source of each FET in the bridge. When the high-side FET remains on, the current through the associated high-side gate-source resistor (RGSH) is supplied by the high-side driver and thus appears as a static resistive load on the top charge pump. The minimum RGSH value that the top charge pump can supply is shown in the Electrical Characteristics table.

GLA and GLB pins These are the low-side gate drive outputs of the external N-channel mosfet. External resistors between the gate drive output and the gate-to-FET connection (as close to the FET as possible) can be used to control the slew rate seen at the gate, providing di/dt and dv for the SA and SB outputs Some control of /dt. GLx going high turns on the upper half of the driver, providing current to the gate of the low-side FET in the external power bridge, and turning it on. GLx going low turns on the lower half of the driver, injecting current from the external FET gate circuit into the LSS pin, which turns off the FET.

The SA and SB pins are connected directly to the motor and these terminals sense the voltage on the load. These terminals are also connected to the negative side of the bootstrap capacitor, which is the negative supply connection for the floating high-side driver. The discharge current from the high-side FET gate capacitance flows through these connections, which should have low impedance circuit connections to the FET bridge.

GHA and GHB pins These terminals are the high-side gate drive outputs of the external N-channel FET. An external resistor between the gate drive output and the gate-to-FET connection (as close to the FET as possible) can be used to control the slew rate seen at the gate and thus the di/dt and dv/ of the SA and SB outputs dt. The high pass of the GHx energizes the upper half of the driver, providing current to the gate of the high-side FET in the external motor driver bridge to energize it. Going GHx low turns on the lower half of the driver, injecting current from the external FET gate circuit into the corresponding Sx pin, turning off the FET.

CA and CB pins These are the high side connections for the bootstrap capacitor and are the positive supply for the high side gate driver. When the associated output Sx terminal is low, the bootstrap capacitor is charged to approximately VREG. When the Sx output oscillates high, the charge on the bootstrap capacitor causes the voltage on the corresponding Cx terminal to rise with the output to provide the boost gate voltage required by the high-side fet.

LSS pin This is the low-side return path for the discharge of the FET gate capacitance. It should be connected directly to the common source of the low-side external FET through a separate low-impedance connection.

RDEAD Pin This pin controls the internal generation of dead time during FET switching.

• When the resistance connected between RDEAD and AGND is greater than 3 kΩ, the gate drive circuit prevents cross conduction, which introduces a dead time tDEAD between turning off one FET and turning on the complementary FET. The dead time is derived from the resistor value connected between the RDEAD and AGND pins.

• Gate drive circuitry prevents cross-conduction when RDEAD is directly connected to V5. In this case, tDEAD defaults to 6 μs (typ).

Logic control input

Four low-voltage level digital inputs provide control for the gate drivers. These logic inputs have a nominal 500 mV hysteresis for improved noise performance. Together they are used to provide fast decay or slow decay with high or low side recirculation. They also offer braking, coasting and sleep modes as defined in Tables 1 and 2.

PWMH and PWML pins These inputs can be used to control the current in the bridge. PWMH provides high-side chopping and PWML provides low-side chopping. When used together, they control the power bridge in fast decay mode. PWM options are provided in Table 2.

• Set PWMH low to turn off the active high side driver. This provides high-side chopped slow decay PWM.

• Set PWML low to turn off the active low-side driver. This provides low-side chopping slow decay PWM.

• PWMH and PWML can also be connected together and driven by a single PWM signal. This provides fast decaying pulse width modulation.

Phase Pin The state of the Phase pin determines the positive direction of the load current (see Table 1). The phase pin can also be used as a PWM input when full four-quadrant control (fast decay synchronous rectification) is required (see Table 2).

SR pin which will enable or disable sync correction. When SR is high, synchronous rectification is enabled. When a pwmof phase occurs (one or both of the PWMH and PWML pins are low), the MOSFET that is turned on by the synchronous rectification is the complementary one that is turned off. This ensures that current flows through the low resistance MOSFET instead of the diode.

When SR is low, synchronous rectification is disabled. In this case, fewer MOSFET switching cycles occur, reducing losses in the A3941. However, the load current circulates through the high resistance body diode of the power mosfet, causing more power dissipation in the power bridge.

Reset Pin This is an active low input that allows the A3941 to enter sleep mode when active. When reset is held low, the regulator and all internal circuits are disabled and the A3941 enters sleep mode. There is a short delay in the regulator decoupling and storage capacitor discharge before fully entering sleep mode. This typically takes several milliseconds, depending on application conditions and component values.

In sleep mode, the current consumption of the VBB supply is minimized. In addition, locked faults and corresponding fault flags are cleared. When the A3941 comes out of sleep mode, the protection logic ensures that the gate drive outputs are turned off until the charge pump reaches its proper operating state. Under nominal conditions, the priming pump stabilizes in about 3 ms.

Reset can also be used to clear a locked fault flag without going into sleep mode. To do this, hold reset low for less than the reset pulse time tRES. This will clear any latching faults that disable the output, such as short-circuit detection or undervoltage on the bootstrap capacitor.

Note that the A3941 can be configured to start without any external logic inputs. To do this, pull the reset pin to VBB through an external resistor. The resistor value should be between 20 and 33 kΩ.

coasting and braking

To put the power bridge in the coast state, that is when all the power bridges turn off the mosfet, the two PWM inputs (PWMH and PWML) must be kept low while SR must be kept low. This forces all gate driver outputs low.

Braking is achieved by forcing the power bridge to short-circuit the load, allowing the load's back EMF to generate a braking torque.

Several braking states are possible using combinations of inputs on PWMH, PWML, and SR. For example, keeping PWML and SR high and PWMH low turns on the two low-side FETs to shorten the load. The short-circuit path is always present and provides braking in both directions of motor rotation. Another example is keeping SR low so that only one low-side FET is active when PWML is high and PWMH is low, and braking current flows through the body diode of the relatively low-side FET. This only provides braking in one direction, as the diode does not allow braking current to flow if the motor is reversed. Also, by swapping PWMH and PWML, the braking current can circulate around the high side switch.

diagnosis

The A3941 integrates several diagnostic functions to provide fault status indication and take action to prevent permanent damage if required. In addition to system-wide faults such as undervoltage and overtemperature, the A3941 integrates a single drain-source supervisor for each external FET to provide short-circuit detection.

Diagnostic management pins

The VDSTH pin determines faults on external FETs by measuring the drain-source voltage VDS of each active FET and comparing it to the threshold voltage VDSTH applied to the VDSTH input. To avoid false fault detection during switching transients, the comparison is delayed by an internal blanking timer. If the voltage applied to the VDSTH pin is greater than the disable threshold voltage VDSDIS, the FET short detection is disabled.

VDRAIN pin This is a low current sense input from the top of the external FET bridge. This input allows accurate measurement of the voltage at the drain of the high-side FET. It should be directly connected to the common connection point of the drain of the power bridge FET at the positive connection point of the power supply. The input current at the VDRAIN pin is proportional to the voltage at the VDSTH pin and can be approximated as:

where IVDRAIN is the current into the vdstrain pin in μA and VDSTH is the voltage on the VDSTH pin in V.

FF1 and FF2 pins These are open-drain output fault flags that indicate fault conditions through their states, as shown in Table 3.

If two or more faults are detected simultaneously, the state of the fault flag will be determined by the logical OR of the flag states of all detected faults.

fault state

Overtemperature If the connector temperature exceeds the overtemperature threshold (usually 165°C), the A3941 will enter an overtemperature fault state and FF1 will go high. The overtemperature fault condition and FF1 will only be cleared when the temperature falls below the recovery level specified by TJF–TJFhys.

No circuitry will be disabled. External control circuitry must take steps to limit power dissipation in some way to prevent overheating damage to the A3941 chip and unpredictable device operation.

VREG Undervoltage VREG provides the low-side gate driver and bootstrap charge current. It is critical to ensure that the voltage is high enough before enabling any outputs. If the voltage at VREG, VREG is below the falling VREG undervoltage lockout threshold VREGUVoff, the A3941 will enter the VREG undervoltage fault state. In this fault state, both FF1 and FF2 will be high and the output will be disabled. When VREG rises above the VREG undervoltage lockout threshold, VREGUVon, the VREG undervoltage fault status and fault flag will be cleared.

The VREG undervoltage monitoring circuit is active during power-up, and the A3941 remains in the VREG undervoltage fault state until VREG is greater than the rising VREG undervoltage lockout threshold, VREGUVon.

Bootstrap Capacitor Undervoltage The A3941 monitors the voltages of the individual bootstrap capacitors to ensure they have enough charge to provide current pulses for the high side drivers. The voltage on the associated bootstrap capacitor must be higher than the turn-on voltage limit before the high-side driver is turned on. If this is not the case, the A3941 will initiate a boot charge cycle by activating the complementary low-side driver. Under normal conditions, this will charge the bootstrap capacitor above the turn-on voltage within a few microseconds, then the high-side driver will be enabled.

When the high-side driver is active, the bootstrap voltage monitor remains active, and if the voltage falls below the shutdown voltage, a charge cycle is initiated.

In both cases, if there is a fault preventing the boot capacitor from charging, the charge cycle will time out, the fault flag (indicating undervoltage) will be set, and the output will be disabled. The boot undervoltage fault condition remains latched until reset is set low.

V5 Undervoltage V5's logic power regulator voltage output is monitored to ensure proper logic operation. If the voltage at V5, V5 falls below the falling V5 undervoltage lockout threshold V5UVoff, the A3941 will enter the V5 undervoltage fault state. In this fault state, both FF1 and FF2 will be high and the output will be disabled. In addition, all fault states and fault flags are reset and replaced by the fault flag corresponding to the V5 undervoltage fault state, since the state of the other faults reported cannot be guaranteed. For example, a V5 undervoltage will reset the existing short circuit fault condition and replace it with a V5 undervoltage fault. The V5 undervoltage fault status and fault flag will be cleared when V5 rises above the rising V5 undervoltage lockout threshold defined by V5UVoff+5UVhys.

The V5 undervoltage monitoring circuit is activated during power-up, and the A3941 remains in the V5 undervoltage fault state until V5 is greater than the rising VREG undervoltage lockout threshold, V5UVoff5UVhys.

Short fault operation identifies short circuits in the power bridge by monitoring the drain-source voltage VDS of each active FET and comparing it to the fault threshold voltage at the VDSTH pin. Since the power mosfet takes a finite time to reach the rated on-resistance, the measured drain-to-source voltage will show as a phase switch failure. To avoid this false short fault detection, the output of the comparator is ignored in two cases:

▪ When the external FET is off

▪ Until the end of this period, called the fault blank time, after the FET is turned on.

When the FET is on, a short-circuit fault will be detected if the drain-source voltage exceeds the voltage at the VDSTH pin at any time after the fault blank time. This fault will be latched and the FET will be disabled until reset.

In applications that do not require short-time detection, this feature can be disabled by connecting VDSTH to V5 or by applying a voltage greater than the disable threshold voltage, VDSDIS. This will completely disable the VDS monitor circuit, preventing short circuit fault detection and any short circuit fault indication via the fault flag. In this case, the external FET will not be protected by the A3941.

A short circuit from any motor connection to the battery or VBB connection can be detected by monitoring the voltage on each phase low side FET when VDSTH is less than the disable threshold voltage using the appropriate Sx and LSS pins. This drain-source voltage, VDS, is continuously compared with the voltage on the VDSTH pin.

If the FET is not active, the result of this comparison is ignored. The fault is also ignored during a fault blanking interval after the FET is turned on. If the comparator is not ignored and its output indicates that VDS exceeds the voltage at the VDSTH pin, then FF2 will be high.

Short-to-Ground When VDSTH is less than the disable threshold voltage, vdsdi detects short-circuits from any motor connection to ground by monitoring the voltage on each phase high side FET using the appropriate Sx pin and the voltage at VDRAIN. This drain-source voltage, VDS, is continuously compared with the voltage on the VDSTH pin. If the FET is not active, the result of this comparison is ignored. The fault is also ignored during a fault blanking interval after the FET is turned on. If the comparator is not ignored and its output indicates that VDS exceeds the voltage at the VDSTH pin, FF2 will be high.

Short-circuited loads Short-to-ground and short-to-supply monitor circuits also detect motor phase winding shorts. In most cases, a short-circuited winding will be indicated by both high-side and low-side faults detected at the same time. In some cases, the relative impedance may only allow detection of a short circuit.

application information

Bridge Management Based on PWM Control

The A3941 provides two PWM control signals, phase control of current direction, and the ability to enable or disable synchronous rectification. This allows a wide variety of full-bridge control schemes to be implemented. The six basic schemes are shown in Table 2 and described further below.

Slow Decay Slow Decay is the simplest and most common control configuration. Figure 1A shows the path of the bridge and load current with PWML and phase tied high and SR low when a PWM signal is applied to PWMH.

In this case, the high side mosfet is turned off during the current decay time (PWM off time) and the load current is recirculated through the low side mosfet. This is often referred to as high-side chopping or high-side pulse width modulation. The circulating current flows through the body diode of the low-side MOSFET, which is complementary to the high-side MOSFET being turned off. Efficiency can be improved by turning on the complementary mosfet during PWM off to shorten the reverse diode and provide synchronous rectification. As shown in Figure 1B, making SR high is easy to implement.

By applying a PWM signal to the PWML pin instead of the PWMH pin, the low-side MOSFET turns off during the PWM off time, and the load current circulates through the high-side MOSFET, as shown in Figure 1C.

In the three slow decay configurations shown, simply applying a low level to the phase pin reverses the direction of the average current in the load. Referring to the slow decay entry in Table 2, when the phase is high, the average current flows from the A-phase connection (SA) to the B-phase connection (SB). When the phase is low, the direction is from B to A.

Fast Decay While slow decay usually provides adequate control of load current for most simple control systems, the stability of current control can be affected by factors such as load back EMF. In these cases, typically actuator positioning or servo control systems, it may be necessary to use fast decay to provide continuous control of the load current. The A3941 can be configured to provide fast decay using diode recirculation or synchronous rectification.

by application

Simultaneously send a PWM signal to both PWM inputs (PWMH and PWML) while disabling SR (Figure 2A). Because the circulation of the current is through the body diode of the mosfet, the average load current cannot be negative, so for the slow decay scheme, the phase input still needs the reverse load current.

While fast decay diode rectification provides a higher degree of current control than slow decay schemes, it still may not provide adequate control for servo systems that require full four-quadrant control. This is only possible using fast decay and synchronous rectification. By applying a PWM signal to the phase input and keeping PWMH, PWML, and SR high (Figure 2B), the load current can be controlled in both directions with a single PWM signal. Since all four mosfets in the bridge state are changed, power can be applied directly to the load in any direction. The effect is: when the PWM duty cycle is less than 50%, the average current flows from B to A; when it is greater than 50%, the average current flows from A to B; when it is greater than 50%, the average current is zero. This makes the load current immune to any back-EMF voltages, such as those produced by rotating electrical machines, and effectively allows applied torque to work with or against the motor in either direction.

Synchronous Rectification Synchronous rectification is used to reduce the power consumption of the external mosfet. As mentioned above, the A3941 can be instructed to turn on the corresponding low-side and high-side drivers during load current recirculation PWM off cycles. During the decay time, synchronous rectification allows current to flow through the selected MOSFET instead of through the source-drain body diode. The body diode of the circulating power mosfet will only conduct during the dead time period when each PWM transition occurs.

Dead Time

To prevent cross-conduction (penetration) in any phase of the power FET bridge, it is necessary to have a dead-time delay tDEAD between the high-side or low-side turn-off and the next complementary turn-off event. A cross-conduction potential occurs when any complementary high-side and low-side fet pairs are switched simultaneously (for example, when using synchronous rectification or after a bootstrap capacitor charge cycle). In the A3941, the dead time of the two phases is set by a dead time resistor, RDEAD, between the RDEAD and AGND pins.

For values of RDEAD between 3 kΩ and 240 kΩ, the nominal value of tDEAD (in ns) at 25°C can be approximated as:

where RDEAD is kΩ. Maximum accuracy is achieved with RDEAD values between 6 and 60 kΩ, as shown in Figure 3.

IDEAD current can be estimated by:

By connecting the RDEAD pin directly to the V5 pin, a maximum dead time can be set, typically 6µs.

The choice of the power FET and the external series gate resistor determines the choice of the dead zone resistor RDEAD. The dead time should be long enough to ensure that one FET in a phase has stopped conducting before the complementary FET starts conducting. This should also take into account tolerances and variations in the FET gate capacitance, series gate resistance, and on-resistance of the A3941's internal drivers.

Dead time occurs only when the on command of one FET occurs within tDEAD after the off command of its complementary FET. In situations where one side of the phase drive is permanently off, such as when using diode rectification with slow decay, there is no dead time. In this case, the gate driver will turn on within the specified propagation delay after the corresponding phase input goes high. (See Door Drive Timing Diagram.)

fault blank time

To avoid false short-circuit fault detection, the output from the VDS monitor is ignored when any FET is turned off and for a period of time after it is turned on. This time is the fault blank time. Its length is the dead time tDEAD plus an extra period to compensate for the delay in the VDS monitor. This extra delay is typically 300 to 600 nanoseconds.

brake

The A3941 can force all low-side FETs on and high-side FETs off (SR=1, PWMH=0, PWML=1) or conversely by forcing all low-side FETs off and high-side FETs on (SR=1, PWMH=1, PWML=0) to perform dynamic braking. This effectively shorts the motor's back EMF, creating a breakaway torque.

During braking, the load current can be approximated as:

where VBEMF is the voltage produced by the motor and RL is the resistance of the phase windings.

Care must be taken when braking to ensure that the maximum rating of the power FET is not exceeded. Dynamic braking is equivalent to the slow decay of synchronous rectification.

Bootstrap Capacitor Selection

The boot capacitor, CBOOTx, must be selected correctly to ensure proper operation of the A3941. If the capacitance is too high, charging the capacitor will waste time, limiting the maximum duty cycle and PWM frequency. If the capacitance is too low, there will be a large voltage drop due to charge sharing when charge is transferred from CBOOTx to the FET gate.

To keep this voltage drop small, the charge in the bootstrap capacitor QBOOT should be much larger than the charge required by the FET's gate QGATE. A factor of 20 is a reasonable value, and the value of CBOOT can be calculated using the following formula:

therefore:

where VBOOT is the voltage on the bootstrap capacitor.

When the FET is on, the voltage drop ∏V across the bootstrap capacitor can be approximated as:

So, for a factor of 20, ∏V is about 5% of VBOOT.

Under normal operating conditions, the maximum voltage of the bootstrap capacitor is VREG(max). However, in some cases, the voltage can momentarily reach 18 V, the clamping voltage of the Zener diode between the Cx and Sx pins. In most applications, with a good ceramic capacitor, the operating voltage can be limited to 16 volts.

Bootstrap charging

It is best to ensure that the high-side bootstrap capacitor is fully charged before requiring a high-side PWM period.

The time tCHARGE (μs) required to charge the capacitor is approximately:

where CBOOT is the value of the bootstrap capacitor in nF, and ∏V is the voltage required by the bootstrap capacitor.

After power-up, the boot capacitor can be fully discharged when the driver is disabled for an extended period of time. In this case, ∏V can be seen as the full high-side drive voltage, 12 V. Otherwise, ∏V is the amount of voltage drop during charge transfer, which should be less than or equal to 400 mV. The capacitor charges when the Sx pin is pulled low and current flows from VREG to CBOOT through the internal boot diode circuit.

Self-service charge management

The A3941 provides automatic bootstrap capacitor charge management. The bootstrap capacitor voltage for each phase is continuously checked to ensure that it is above the bootstrap undervoltage threshold VBOOTUV. If the bootstrap capacitor voltage falls below this threshold, the A3941 turns on the necessary low-side FET and continues to charge until the bootstrap capacitor exceeds the undervoltage threshold plus hysteresis, VBOOTUV+VBOOTUVhys. The minimum charge time is typically 7µs, but may be longer for very large bootstrap capacitor values (>1000nf). If the bootstrap capacitor voltage does not reach the threshold within approximately 200µs, an undervoltage fault is flagged.

Selection of VREG Capacitors

The internal reference voltage VREG provides current for the low-side gate drive circuit and charging current for the bootstrap capacitor. When a low-side FET is turned on, the gate drive circuit will supply the gate with the high transient current required to turn on the FET quickly. This current, which can reach hundreds of milliamps, cannot be provided directly by the limited output of the VREG regulator, but must be provided by an external capacitor connected to VREG.

The on-current value of the high-side FET is similar to that of the low-side FET, but is mainly provided by the bootstrap capacitor. However, the bootstrap capacitor must be recharged from the VREG regulator output. Unfortunately, bootstrap charging can happen a short time after the low side is turned on. This requires that the capacitor value connected between VREG and AGND be high enough to minimize the transient voltage drop across VREG under the combination of low-side FET turn-on and bootstrap capacitor charging. 20×CBOOT is a reasonable value. The maximum operating voltage never exceeds VREG, so capacitors can be rated as low as 15 V. This capacitor should be placed as close as possible to the VREG pin.

Power decoupling

Because this is a switching circuit, all supplies at the switching point have current spikes. As with all such circuits, the power connections should be separated from the ceramic capacitors (typically 100 nF) between the power pins and ground. These capacitors should be placed as close as possible to the device power pins VBB and V5 and the ground pin GND.

Power consumption

In applications where higher ambient temperatures are expected, on-chip power dissipation can become a critical factor. Care should be taken to ensure that operating conditions allow the A3941 to remain within a safe range of connection temperatures.

A3941, the power consumed by the PD can be estimated by:

Given:

where:

N is the number of FET switches in one PWM cycle, and

N=1 means diode recirculation slow decay, N=2 means synchronous rectification slow decay or diode recirculation fast decay, N=4 means synchronous rectification fast decay.

Layout suggestion

PCB layout must be carefully considered when designing high frequency, fast switching, high current circuits. Here are some suggestions for some of these considerations:

• The A3941 ground, ground and high current loops of the external FET should be returned to the negative terminal of the motor power supply filter capacitor respectively. This will minimize the effect of switching noise on the device logic and analog references.

• The exposed thermal pad should be connected to the ground pin and may form part of the controller power ground (see Figure 4).

• Minimize stray inductance by using short, wide copper traces on the drain and source terminals of all power FETs. This includes the motor lead connections, the input power bus, and the common supply for the low-side power FETs. This will minimize the voltage generated by rapidly switching large load currents.

• Consider using small (100 nF) ceramic decoupling capacitors between the source and drain of the power FET to limit fast transient voltage spikes caused by circuit trace inductance.

• Keep the gate discharge loop connecting Sx and LSS as short as possible. Any inductance on these traces will cause a negative transition on the corresponding A3941 pin, which may exceed the absolute maximum ratings. If possible, consider using clamp diodes to limit negative excursions of these pins from GND.

• Sensitive connections such as RDEAD and VDSTH, which have low ground currents, should be connected to a quiet ground (see Figure 4), which is connected independently, closest to the ground pin. These sensitive parts should not be connected directly to the power common or common ground plane. They must be directly referenced to the GND pin.

• Power supply decoupling for VBB, VREG and V5 should be connected to the controller power supply ground, i.e.

Connect independently near the ground pin. Decoupling capacitors should also be placed as close as possible to the associated power supply pins.

• If layout space is limited, mute and controller power grounds can be combined. In this case, make sure the ground return of the dead-time resistor is close to the ground pin.

• Using a tight ground (tip and barrel) probe, check the transient peak voltage excursion on the LSS pin against the ground pin. If the voltage at LSS exceeds the absolute maximum shown in this datasheet, add one or two additional clamps and capacitors between the LSS pin and the GND pin, as shown in Figure 4.

• The gate charge drive path and gate discharge return path may carry large transient current pulses. Therefore, traces from GHx, GLx, Sx, and LSS should be kept as short as possible to reduce circuit trace inductance.

• Provides independent connection from LSS to the common point of the power bridge. It is not recommended to connect LSS directly to the GND pin, as this may inject noise into sensitive functions such as dead-time timers.

• A low-cost diode can be placed in the VBB connection to provide reverse battery protection. Under reverse battery conditions, the reverse voltage can be clamped to about 4 V using the body diode of the power FET. In this case, the additional diode in the VBB connection will prevent damage to the A3941 and the VDRAIN input will remain under reverse voltage.

Note that the above are only suggestions. Every application is different and may experience different sensitivities. A driver running a few amps will be less sensitive than one running 150 amps and every design should be tested at maximum current to ensure any parasitics are removed.

Package LP 28-pin TSSOP with exposed thermal pad