main feature

350MHz high-performance Blackfin processor core; two 16-bit macs, two 40-bit alus, one 40-bit shifter, four 8-bit video alus and two 40-bit accumulators; RISC-like register and instruction model; programming and compiler friendly support; advanced debug, trace and performance monitoring; 1.0 V–1.6 V core VDD with dynamic power management; 3.3 V input/output; 260-ball PBGA package; memory; 308K bytes of on-chip memory: instruction L1 SRAM 16K bytes of /Cache; 32K bytes of data L1 SRAM/cache; 4K bytes of Notepad L1 SRAM; 256K bytes of full-speed, low-latency L2 SRAM; memory DMA controller; memory-protected memory management unit; none Plastic external memory controller; synchronous SDRAM support; asynchronous, support SRAM, Flash, ROM; peripherals; 32-bit, 33 MHz, 3.3 V, PCI 2.2 compatible bus interface; master-slave support; integrated USB 1.1 compatible device interface; two UARTs, one with IrDA; two SPI-compatible ports; two full-duplex synchronous serial ports (sport); four timers/counters, three with PWM support; 16 bidirectional programmable flag I/ O pin; watchdog timer; real-time clock; on-chip phase-locked loop with 1 to 31 frequency multiplier.

General Instructions

The ADSP-BF535 processor is a member of the Blackfin processor family that integrates the Micro Signal Architecture (MSA) jointly developed by Analog Devices and Intel. The architecture combines the advantages of dual MAC state-of-the-art signal processing engines, a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.

By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support and leading-edge signal processing in an integrated package.

Portable Low Power Architecture

Blackfin processors provide world-class power management and performance. Blackfin processors use a low-power and low-voltage design approach with dynamic power management capabilities that independently vary voltage and operating frequency, significantly reducing overall power consumption. Compared with changing the operating frequency, changing the voltage and frequency can greatly reduce the power consumption. This means longer battery life for portable devices.

system integration

The ADSP-BF535 Blackfin processor is a highly integrated system-on-a-chip solution for next-generation digital communications and portable Internet devices. By combining industry-standard interfaces with high-performance signal processing cores, users can rapidly develop cost-effective solutions without the need for expensive external components. The ADSP-BF535 Blackfin processor system peripherals include UARTs, SPIs, SPORTs, general purpose timers, real-time clocks, programmable flags, watchdog timers, and USB and PCI buses for glueless peripheral expansion.

ADSP-BF535 Peripherals

The ADSP-BF535 Blackfin processor includes a rich set of peripherals connected to the core via multiple high-bandwidth buses, providing flexibility in system configuration and excellent overall system performance. See functional block diagram on page 1. Basic peripherals include general-purpose functions such as uarts, timers with PWM (pulse width modulation) and pulse measurement capabilities, general-purpose flag I/O pins, real-time clock, and watchdog timer. This set of functions addresses a variety of typical system support needs and is enhanced by system scalability through components. In addition to these general purpose peripherals, the ADSP-BF535 Blackfin processor includes high-speed serial ports for interfacing with various audio and modem codec functions. It also contains an event handler for flexible management of interrupts from on-chip peripherals and external sources. It includes power management controls that adjust the performance and power characteristics of processors and systems for many application scenarios.

In many system designs, on-chip peripherals can be easily expanded with little or no glue logic due to the inclusion of multiple interfaces on industry standard buses that provide expansion. These include a 32-bit, 33 MHz, V2.2 compliant PCI bus, SPI serial expansion port, and a device-type USB port. This enables connecting a wide variety of peripherals to tailor the system design to specific applications with minimal design complexity.

With the exception of programmable flags, real-time clocks and timers, all peripherals are supported by a flexible DMA structure, with each DMA channel integrated into the peripheral. There is also a separate memory DMA channel dedicated to data transfers between various memory spaces including external SDRAM and asynchronous memory, internal level 1 and 2 SRAM, and PCI memory spaces. Multiple 32-bit on-chip buses, running at frequencies up to 133MHz, provide enough bandwidth to keep the processor core running with all on-chip and external peripheral activity.

processor core

As shown in Figure 1, the Blackfin processor core contains two multipliers/accumulators (macs), two 40-bit alus, four video alus, and a shifter. The computational unit processes 8-bit, 16-bit or 32-bit data from the register file.

Each MAC performs a 16-bit by 16-bit multiplication per cycle, accumulating a 40-bit result, providing 8-bit extended precision.

The ALU performs a standard set of arithmetic and logical operations. Since the two ALUs are capable of operating on 16-bit or 32-bit data, the flexibility of the computational unit can meet the signal processing requirements of various application needs. Each of the two 32-bit input registers can be viewed as two 16-bit half-registers, so each ALU can perform very flexible single 16-bit arithmetic operations. Dual 16-bit or single 32-bit operations can be done in one cycle by treating registers as 16-bit operand pairs. Four 16-bit operations can simply be accomplished by utilizing the second ALU. This speeds up throughput per cycle.

The powerful 40-bit shifter has extensive functions to perform shifting, rotating, normalizing, extracting and storing data.

The data for the compute unit can be found in a multiport register file with 16 16-bit entries or 8 32-bit entries.

A powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. The sequencer supports conditional jumps and subroutine calls, as well as zero-overhead loops. Circular buffers store instructions locally, eliminating instruction memory accesses to tight loop code.

Two data address generators (DAGs) provide addresses for simultaneously fetching dual operands from memory. DAGs share a register file containing four sets of 32-bit index, modify, length, and base registers. Another eight 32-bit registers provide pointers to variables and regular indices of stack locations.

Blackfin processors support an improved Harvard architecture and a hierarchical memory structure. Level 1 (L1) memory typically runs at full processor speed with little or no latency. Level 2 (L2) memory is other memory, on-chip or off-chip, that can take multiple processor cycles to access. At the L1 level, the instruction memory only holds instructions. Two data memories hold data, while a dedicated Notepad data memory stores stack and local variable information. In a secondary system, there is only one unified memory space where instructions and data can be stored.

In addition, L1 instruction memory and L1 data memory can be configured as static ram (sram) or cache. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be running on the core, and can protect system registers from accidental access.

The architecture provides three modes of operation: user mode, management mode, and emulation mode. User mode provides a protected software environment by restricting access to certain system resources, while admin mode has unrestricted access to system and core resources.

The Blackfin processor instruction set has been optimized so that the 16-bit opcodes represent the most commonly used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes representing full-featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instructions can be issued in parallel with two 16-bit instructions, allowing programmers to use many core resources in one instruction cycle.

Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use with C/C++ compilers, resulting in fast and efficient software implementations.

memory structure

The ADSP-BF535 Blackfin processor uses 32-bit addresses to treat memory as a single unified 4 GB address space. All resources, including internal memory, external memory, PCI address space, and I/O control registers, occupy a separate portion of this common address space. The memory portion of this address space is arranged in a hierarchy to provide a good cost/performance balance, with very fast, low latency memory as cache or SRAM very close to the processor; and larger, lower cost and more A low-performance memory system is far from the processor. See Figure 2.

The L1 memory system is the primary highest performance memory available to the Blackfin processor core. Secondary memory provides additional capacity but slightly lower performance. Finally, through the External Bus Interface Unit (EBIU), SDRAM, Flash and SRAM expansion are provided, with optional access to external physical memory exceeding 768M bytes.

The memory DMA controller provides high bandwidth data movement capabilities. It can perform block transfers of code or data between internal L1/L2 memory and external memory space (including PCI memory space).

Internal (on-chip) memory

The ADSP-BF535 Blackfin processor has four on-chip memories that provide high-bandwidth access to the core.

The first is the L1 instruction memory, consisting of a 16K byte 4-way set associative cache. Also, the memory can be configured as SRAM. This memory is accessed at the maximum speed of the processor.

The second on-chip memory block is the L1 data memory, consisting of two sets of 16K bytes. Each L1 data store can be configured as a way of bidirectional set associative cache or SRAM and accessed by the core at full speed.

The third block of memory is 4Kbytes of Notepad RAM, which runs at the same speed as L1 memory, but is only accessible as data SRAM (cannot be configured as cache, and cannot be accessed via DMA).

The fourth on-chip memory system is the L2 SRAM memory array, which provides 256K bytes of high-speed SRAM at the full bandwidth of the core with slightly longer latency than the L1 memory array. Secondary memory is a unified instruction and data memory that can store any mix of code and data required by the system design.

The Blackfin processor core has a dedicated low-latency 64-bit wide datapath port that connects to L2 SRAM memory.

External (off-chip) memory

External memory is accessed through the External Bus Interface Unit (EBIU). This interface provides a glue-free connection to four sets of synchronous DRAM (SDRAM) and four sets of asynchronous memory devices, including flash, EPROM, ROM, SRAM, and memory-mapped I/O devices.

The PC133 -compatible SDRAM controller can be programmed to interface with up to four SDRAM banks, each containing 16Mbytes to 128Mbytes, and can access up to 512Mbytes of SDRAM. Each bank is independently programmable and adjacent to adjacent banks, regardless of the size of the different banks or their location. This allows flexibility in configuring and upgrading system memory, while allowing the core to treat all SDRAM as one contiguous physical address space.

The asynchronous memory controller can also be programmed to control up to four groups of devices, with very flexible timing parameters for a wide variety of devices. Regardless of the size of the device used, each bank occupies a 64-megabyte segment, so the banks are only contiguous when the 64-megabyte memory is fully populated.

PCI interface

The PCI bus defines three separate address spaces that are accessed by windows in the memory space of the ADSP-BF535 Blackfin processor. These spaces are PCI memory, PCI I/O, and PCI configuration.

In addition, the PCI interface can be used as a bridge from the processor core to the control CPU in the system, or as a host port, where the other CPU in the system is the host, and the ADSP-BF535 is used as a smart I/O on the PCI bus equipment.

When the ADSP-BF535 Blackfin processor is used as the system controller, it can view the PCI address space through the mapping window, can initialize all the devices in the system and maintain the environment topology map.

The PCI memory area is a 4 GB space that appears on the PCI bus and can be used to map memory I/O devices on the bus. The ADSP-BF535 Blackfin processor uses a 128 MB window in the memory space to view a portion of the PCI memory space. A base address register is provided to position the window anywhere in the 4gbyte PCI memory space, while its location relative to the processor address remains fixed.

The PCI I/O area is also 4 GB of space. However, most systems and I/O devices only use a 64 KB subset of this space for I/O mapped addresses. The ADSP-BF535 Blackfin processor implements a 64K byte window in this space and a base address register that can be used to locate it anywhere in the PCI I/O address space, while the window is in the processor's keep the same address in the address space.

The PCI configuration space is a limited address space used for system enumeration and initialization. This address space is a very low-performance mode of communication between the processor and the PCI device. The ADSP-BF535 Blackfin processor provides a single-valued window for accessing a single data value at any address in the PCI configuration space. This window is fixed and receives the address of the value, or the value if the operation is a write. Otherwise, the device returns the value to the same address in the read operation.

I/O memory space

Blackfin processors do not define a separate I/O space. All resources are mapped through a flat 32-bit address space. On-chip I/O devices map their control registers to memory-mapped registers (MMRs) at addresses near the top of the 4 GB address space. They are divided into two smaller blocks, one contains the control mmr for all core functions, and the other contains the registers needed for setup and control of the peripherals on the chip outside the core. The core mmr is only accessible by the core, and only in supervisor mode, and is shown as reserved space by on-chip peripherals and peripherals accessing resources through the PCI bus. In admin mode, the core has access to the system mmr and can be mapped as visible or reserved to other devices, depending on the desired system protection model.

start up

The ADSP-BF535 Blackfin processor contains a small boot core that configures the appropriate peripherals for boot. If the ADSP-BF535 Blackfin processor is configured to boot from the boot ROM memory space, the processor begins execution from the on-chip boot ROM. For more information, see Boot Mode on page 14.

event handling

The event controller on the ADSP-BF535 Blackfin processor handles all asynchronous and synchronous events to the processor. The ADSP-BF535 Blackfin processor provides event processing that supports nesting and prioritization. Nesting allows multiple event service routines to be active at the same time. Prioritization ensures that the service of high-priority events takes precedence over the service of low-priority events. The controller supports five different types of events: • Emulation of an emulation event causes the processor to enter emulation mode, allowing command and control of the processor through the JTAG interface.

• Reset this event resets the processor.

• Non-Maskable Interrupt (NMI) - NMI events can be generated to the processor by a software watchdog timer or an NMI input signal. NMI events are often used as power outage indicators to initiate an orderly shutdown of the system.

• Exception events that occur synchronously with program flow, eg, an exception will be executed before an instruction is allowed to complete. Conditions such as data alignment violations, undefined instructions, etc. cause exceptions.

• Interrupt events that occur asynchronously to program flow. They are caused by timers, peripherals, input pins, explicit software instructions, etc.

Each event has an associated register to hold the return address and an associated event return instruction. When an event is fired, the state of the processor is saved in the manager stack.

The ADSP-BF535 Blackfin processor event controller consists of two stages, the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The core event controller works in conjunction with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from peripherals go into the SIC, which are then routed directly to the CEC's generic interrupts.

Core Event Controller (CEC)

In addition to dedicated interrupts and exception events, CEC supports 9 general purpose interrupts (IVG15–7). Of these general purpose interrupts, it is recommended to reserve two lowest priority interrupts (IVG15-14) for software interrupt handlers, leaving seven priority interrupt inputs to support peripherals of the ADSP-BF535 Blackfin processor. Table 1 describes the inputs to CEC, identifying their names in the event vector table (EVT) and listing their priorities.

System Interrupt Controller (SIC)

The System Interrupt Controller provides event mapping and routing from many peripheral interrupt sources to the CEC's priority general purpose interrupt inputs. Although the ADSP-BF535 Blackfin processor provides a default mapping, the user can change the mapping and priority of interrupt events by writing the appropriate values to the Interrupt Assignment Register (IAR). Table 2 describes the input to SIC and the default mapping to CEC. Table 2. System Interrupt Controller (SIC)

event control

The ADSP-BF535 Blackfin processor provides users with a very flexible mechanism to control the processing of events. In CEC, three registers are used to coordinate and control events. Each register is 16 bits wide, and each bit represents a specific event class:

• CEC Interrupt Latch Register (ILAT) - The ILAT register indicates when an event is latched. The appropriate bits are set when the processor locks the event and cleared when the event is accepted by the system. This register is automatically updated by the controller, but can be read in supervisor mode.

• CEC Interrupt Mask Register (IMASK) - The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, the event is unmasked and handled by CEC when asserted. A clear bit in the IMASK register masks the event, so the processor cannot maintain the event even though it might be latched in the ILAT register. In supervisor mode, this register can be read or written. (Note that general purpose interrupts can be globally enabled and disabled using STI and CLI instructions, respectively.) • CEC Interrupt Pending Register (IPEND)

The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates that the event is currently active or nested at some level. This register is automatically updated by the controller, but can be read in supervisor mode.

The SIC further controls event handling by providing three 32-bit interrupt control and status registers. Each register contains bits corresponding to each peripheral interrupt event shown in Table 2.

• SIC Interrupt Mask Register (SIC_IMASK) - This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in a register, that peripheral event is unmasked and handled by the system when asserted. A clear bit in a register masks a peripheral event, preventing the processor from processing the event. • SIC Interrupt Status Register (SIC_ISTAT) - Since multiple peripherals can be mapped to a single event, this register allows software to determine the source of the peripheral event that triggered the interrupt. A set bit indicates that the peripheral is asserting an interrupt, and a cleared bit indicates that the peripheral is not asserting an event.

• SIC Interrupt Wake-Up Enable Register (SIC_IWR) - Each peripheral can be configured to wake up the processor when the processor is in shutdown mode when the event is generated by enabling the corresponding bit in this register. (See Dynamic Power Management on page 11.)

Since multiple interrupt sources can be mapped to a common interrupt, multiple pulses of interrupt events that have been detected on this interrupt input can be asserted simultaneously before or during interrupt processing. As an interrupt acknowledgement, the SIC monitors the contents of the IPEND register.

When an interrupt rising edge is detected, the appropriate ILAT register bits are set (detection takes two core clock cycles). This bit is cleared when the corresponding IPEND register bit is set. The IPEND bit indicates that the event has entered the processor pipeline. At this point, the CEC will recognize the next rising edge event and queue it on the corresponding event input. The minimum delay from a rising edge transition of a general purpose interrupt to an asserted IPEND output is three core clock cycles; however, the delay may be much higher, depending on the activity and mode inside the processor.

DMA controller

The ADSP-BF535 Blackfin processor has multiple independent DMA controllers that support automatic data transfers to the Blackfin processor core with minimal overhead. DMA transfers can occur between the internal memory of the ADSP-BF535 Blackfin processor and any DMA-capable peripheral. Additionally, DMA transfers can be done between any DMA-capable peripheral and peripherals connected to external memory interfaces, including SDRAM controllers, asynchronous memory controllers, and PCI bus interfaces. Peripherals that support DMA include motion, SPI ports, UART, and USB ports. Every DMA-capable peripheral has at least one dedicated DMA channel. DMA from PCI to PCI is achieved through the memory DMA channel.

To describe each DMA sequence, the DMA controller uses a set of parameters called descriptor blocks. When consecutive DMA sequences are required, these descriptor blocks can be chained together, so the completion of one DMA sequence automatically starts and starts the next. The descriptor block includes the full 32-bit address of the source and destination base pointers, allowing access to the entire ADSP-BF535 Blackfin processor address space.

In addition to the dedicated peripheral DMA channel, there is a separate memory DMA channel for transfers between the various memories of the ADSP-BF535 Blackfin processor system. This enables the transfer of blocks of data between any memory, including chip-level 2 memory, external SDRAM, ROM, SRAM and Flash, and PCI address space with little or no processor intervention.

External memory control

The External Bus Interface Unit (EBIU) on the ADSP-BF535 Blackfin processor provides a high-performance, glue-free interface to a variety of industry-standard storage devices. The controller consists of two parts: the first part is the SDRAM controller, which is used to connect industry standard synchronous DRAM devices and dims (dual inline memory modules), and the second part is the asynchronous memory controller, which is used to connect various memory devices .

PC133 SDRAM Controller

The SDRAM controller provides interfaces to up to four groups of industry standard SDRAM devices or DIMMs at speeds up to fSCLK. Fully compliant with the PC133 SDRAM standard, each bank can be configured to contain from 16Mbytes to 128Mbytes of memory.

The controller maintains all columns as one contiguous address space so that the processor sees it as one address space even if different sized devices are used in different columns. This enables system designs to use similar or different memory upgrade configurations after delivery.

A set of programmable timing parameters can be used to configure the SDRAM bank to support slower memory devices. Memory banks can be configured as 32 bits wide for maximum performance and bandwidth, or 16 bits wide for minimum device count and lower system cost.

All four banks share common SDRAM control signals and have their own bank select lines, providing a completely glueless interface for most system configurations.

The address, data, clock and command pins of the SDRAM controller can drive loads up to 50pf. For larger memory systems, the SDRAM controller external buffer timing should be selected and provided so that the load on the SDRAM controller pins does not exceed 50pf.

Asynchronous controller

The asynchronous memory controller provides a configurable interface for up to four independent sets of memory or I/O devices. Each memory bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices, including SRAM, ROM, and flash-EPROM, as well as I/O devices that interface with standard memory control lines. Each column occupies a 64 MB window in the processor's address space, however, these windows cannot be logically contiguous by the memory controller without being completely filled. Banks can also be configured as 16-bit wide or 32-bit wide buses to facilitate interfacing with a range of memory and I/O devices suitable for either high performance or low cost and low power consumption.

PCI interface

The ADSP-BF535 Blackfin processor offers glueless logic and electrical, 33 MHz, 3.3 V, 32-bit PCI (Peripheral Component Interconnect), version 2.2 compliant interface.

The PCI interface is designed for a 3V signaling environment.

The PCI interface provides bus bridging between the processor core and on-chip peripherals and the external PCI bus. The PCI interface of the ADSP-BF535 Blackfin processor supports two PCI functions:

• Host-to-PCI bridging functionality, where the ADSP-BF535 Blackfin processor resources (processor cores, internal and external memory, and memory DMA controllers) provide the hardware components required to emulate the host PCI interface from the perspective of the PCI target device.

• PCI objective function, where intelligent peripherals based on the ADSP-BF535 Blackfin processor can be designed to easily connect to a PCI bus compliant with version 2.2.

PCI host function

As a PCI host, the ADSP-BF535 Blackfin processor provides the necessary PCI host (platform) functionality to support and control various off-the-shelf PCI I/O devices (such as Ethernet control) in systems hosted by the ADSP-BF535 Blackfin processor devices, bus bridges, etc.).

Note that the Blackfin processor architecture only defines memory space (no I/O or configuration address space). The three address spaces of the PCI space (memory, I/O, and configuration space) are mapped into the 32-bit flat memory space of the ADSP-BF535 Blackfin processor. Since the PCI memory space is as large as the memory address space of the ADSP-BF535 Blackfin processor, a windowing method is adopted, and there are separate windows in the address space of the ADSP-BF535 Blackfin processor for accessing the three PCI address spaces. Base address registers are provided so that these windows can be positioned to view any range in the PCI address space, while these windows maintain fixed locations within the address range of the ADSP-BF535 Blackfin processor.

For devices viewing ADSP-BF535 Blackfin processor resources on the PCI bus, several map registers are provided for viewing resources in the PCI address space. The external memory space, internal L2, and some I/O MMRs of the ADSP-BF535 Blackfin processor can be selectively enabled as memory spaces that devices on the PCI bus can use as targets for PCI memory transactions.

PCI objective function

As a PCI target device, the PCI host processor can configure the ADSP-BF535 Blackfin processor subsystem during PCI bus system enumeration. Once configured, the ADSP-BF535 Blackfin processor subsystem acts as an intelligent I/O device. When configured as a target device, the PCI controller uses the memory DMA controller to perform DMA transfers at the request of the PCI host.

USB device

The ADSP-BF535 Blackfin processor provides a USB1.1-compliant device-type interface that supports direct connection to a host system. The USB core interface provides a flexible programmable environment with up to eight endpoints. Each endpoint can support all USB data types, including control, bulk, interrupt and isochronous. Each endpoint provides a memory-mapped buffer for transferring data to the application. The ADSP-BF535 Blackfin processor USB port has a dedicated DMA controller and interrupt input to minimize processor polling overhead and allow asynchronous requests for CPU attention only when transfer management is required.

USB devices require an external 48 MHz oscillator. The value of SCLK must always exceed 48 MHz for USB to function properly.

Real Time Clock

The ADSP-BF535 Blackfin processor real-time clock (RTC) provides a powerful set of digital watch functions including current time, stopwatch and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF535 Blackfin processor. The RTC peripheral has dedicated power pins so it can stay powered and clocked even when the rest of the processor is in a low power state. The RTC offers a variety of programmable interrupt options, including interrupts per second, minute, or day clock cycle, programmable stopwatch countdown interrupts, or interrupts at programmed alarm times.

The input clock frequency of 32.768khz is divided into 1hz signal by the prescaler. The counter function of the timer consists of four counters: a 6-digit seconds counter, a 6-digit minute counter, a 5-digit hour counter, and an 8-digit day counter.

When enabled, the alarm function generates an interrupt when the timer output matches the programmed value in the alarm control register. There are two alarms: one for a time of day, the second for a time of day and a time of day.

The stopwatch function counts down from the programmed value with a resolution of one minute. An interrupt is generated when the stopwatch is enabled and the counter underflows.

Like other peripherals, the RTC can wake the ADSPBF535 Blackfin processor from a low-power state when any interrupt is generated.

Connect the RTC pins XTALI and XTALO with external components as shown in Figure 3.

watchdog timer

The ADSP-BF535 Blackfin processor includes a 32-bit timer that can be used to implement a software watchdog function. If the timer expires before being reset by software, a software watchdog can improve system availability by generating a hardware reset, non-maskable interrupt (NMI), or general purpose interrupt to force the processor to a known state. The programmer initializes the count value of the timer, enables the appropriate interrupt, and then enables the timer. After this, software must reload the counter before it counts from the programmed value to zero. This prevents the system from being left in an unknown state where the software that normally resets the timer stops functioning due to external noise conditions or software bugs.

After a reset, software can determine if the watchdog is the source of a hardware reset by interrogating the status bit in the timer control register, which is only set when the watchdog generates a reset.

The timer is clocked by the system clock (SCLK) at the maximum frequency fSCLK.

timer

There are four programmable timer units in the ADSP-BF535 Blackfin processor. The three general-purpose timers have an external pin that can be configured as a pulse width modulator (PWM) or timer output, timer clock input, or to measure the pulse width of an external event. Each of the three general purpose timer units can be independently programmed as PWM, internally or externally clocked timers, or pulse width counters.

A general purpose timer unit can be used with the uart to measure the width of pulses in a data stream to provide automatic tone detection for serial channels.

General purpose timers can generate interrupts to the processor core, providing periodic events for synchronization of processor clock or external signal counts.

In addition to the three general-purpose programmable timers, a fourth timer is provided. This additional timer is clocked by the internal processor clock (CCLK), which is typically used as the system clock to generate periodic interrupts to the operating system.

Serial port (sport)

The ADSP-BF535 Blackfin processor contains two complete synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. Motion supports these features:

• Bidirectional operation Each movement has independent send and receive pins.

• Buffered (8-deep) transmit and receive ports Each port has a data register for transferring data words between other processor components and a shift register for shifting data in and out of the data register.

• The clock for each transmit and receive port can use an external serial clock or generate its own clock with frequencies ranging from (fSCLK/131070) Hz to (fSCLK/2) Hz. • Word Length Each motion supports the transfer of serial data words of length 3 to 16 bits in MSb first or LSB first format.

• Framing Each transmit and receive port can operate with or without a frame sync signal per data word. The frame sync signal can be generated internally or externally, active high or low, with two pulse widths and early or late frame sync.

• Companding in hardware Each motion can perform A-law or μ-law companding according to ITU Recommendation G.711. Companding can be selected on moving transmit and/or receive channels without additional delay.

• DMA operations have single-cycle overhead, and each movement can automatically receive and transmit multiple memory data buffers. Blackfin processors can chain or link sequences of DMA transfers between motion and memory. Chained DMA can be dynamically allocated and updated by setting up chained descriptor blocks.

• Interrupts Each transmit and receive port generates an interrupt after completing a data word transfer or transferring an entire data buffer via DMA.

• Multi-channel capability supports 128 channels per motion and is compatible with H.100, H.110, MVIP-90 and HMVIP standards.

Serial Peripheral Interface (SPI) port

The ADSP-BF535 Blackfin processor has two SPI compatible ports that enable the processor to communicate with multiple SPI compatible devices.

The SPI interface uses three pins to transfer data: two data pins (Master Out Slave In, MOSIx and Master In Slave Out, MISOx) and one clock pin (Serial Clock, SCKx). Two SPI chip select input pins (SPISSx) allow other SPI devices to select the processor, and 14 SPI chip select output pins (SPIxSEL7–1) allow the processor to select other SPI devices. The SPI select pins are programmable flag pins for reconfiguration. Using these pins, the SPI port provides a full-duplex, synchronous serial interface that supports master-slave mode and multi-master environments.

The baud rate and clock phase/polarity of each SPI port are programmable (see Figure 4), and each port has an integrated DMA controller that can be configured to support transmit or receive data streams. SPI's DMA controller can only service one-way access at any given time.

During transfers, the SPI port sends and receives data simultaneously by serially shifting data in and out on two serial data lines. The serial clock line synchronizes data shifting and sampling on the two serial data lines.

In master mode, the processor executes the following sequence to set up and start an SPI transfer:

1. Enable and configure the operation of the SPI port (data size and transfer format).

2. Select the target SPI slave with the SPIxSELy output pin (reconfigured programmable flag pin).

3. Define one or more TCBs in the processor memory space (optional only in DMA mode).

4. Enable the SPI DMA engine and specify the transfer direction (optional only in DMA mode).

5. Read or write SPI port receive or transmit data buffer (only in non-DMA mode).

The SCKx line generates the programmed clock pulse for simultaneously shifting data out of MOSIx and shifting data in from MISOx. In DMA mode only, transfers continue until the SPI DMA word count transitions from 1 to 0.

In slave mode, the processor performs the following sequence to set up the SPI port to receive data from the master transmitter:

1. Enable and configure the SPI slave port to match the operating parameters set on the master (data size and transfer format) SPI transmitter.

2. Define and generate the receive TCB in the processor memory space to interrupt at the end of the data transfer (optional in DMA mode only).

3. Enable SPI DMA engine for receive access (optional only in DMA mode).

4. After receiving the SPI chip select on the SPISSx input pin (reconfigured programmable flag pin) from the host, start receiving data on the appropriate SPI SCKx edge.

In DMA mode only, reception continues until the SPI DMA word count transitions from 1 to 0. The processor can continue by queuing the next command TCB.

Slave mode transfer operation is similar, except that the processor designates a data buffer in memory, transfers data from it, generates and relinquishes control of the transmit TCB, and begins filling the SPI port's data buffer. If the SPI controller is not ready to transmit, it can send a "zero" word.

UART port

The ADSP-BF535 Blackfin processor provides two full-duplex Universal Asynchronous Receiver Transmitter (UART) ports (UART0 and UART1) fully compatible with PC standard UARTs. The UART port provides a simplified UART interface for other peripherals or hosts, supports full duplex, supports DMA, and asynchronous serial data transfer. Each UART port supports 5 to 8 data bits; 1 or 2 stop bits; no parity. The UART port supports two modes of operation.

• PIO (Programmed I/O) - The processor sends or receives data by writing to or reading the I/O-mapped UATX or UARX registers, respectively. Data is double-buffered both when sent and received.

• DMA (Direct Memory Access) - DMA Controller

Transmission transmits and receives data. This reduces the number and frequency of interrupts required to transfer data between memories. Each UART has two dedicated DMA channels, one for transmit and one for receive. Since DMA channels are serviced at a relatively low rate, they have lower priority than most DMA channels.

The baud rate (see Figure 5), serial data format, error code generation and status, and interrupts for each UART port are programmable:

• Bit rates ranging from (fSCLK/1048576) to (fSCLK/16) bits/sec

• 7 to 12 bits per frame data format

• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

Automatic audio detection is supported along with the generic timer function.

The functionality of UART0 is further extended by supporting the Infrared Data Association (IrDA Serial Infrared Physical Layer Link Specification (SIR)) protocol.

Programmable Flags (PFX)

The ADSP-BF535 Blackfin processor has 16 bidirectional general purpose I/O programmable flag (PF15–0) pins. Programmable flag pins have special functions for selecting clock multipliers, SROM boot mode, and SPI port operation. For more information, see Serial Peripheral Interface (SPI) Ports on page 10 and Clock Signals on page 13. Each programmable flag can be individually controlled by manipulating the flag control, status and interrupt registers.

• The Flag Direction Control register designates the direction of each individual PFx pin as input or output. • Flag control and status registers, instead of forcing software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF535 Blackfin processor employs "write one to set" and "write one to clear" mechanisms that allow in a single instruction Set or clear any combination of individual flags without affecting the level of any other flags. Two control registers are provided, one register is written to set the flag value and the other register is written to clear the flag value. Reading the flags status register allows software to interrogate the meaning of the flags.

• Flag Interrupt Mask Register Two flag interrupt mask registers allow each individual PFx pin to act as an interrupt to the processor. Similar to the two flag control registers used to set and clear a single flag value, one flag interrupt mask register sets bits to enable interrupt functionality and the other flag interrupt mask register clears bits to disable interrupt functionality. PFx pins defined as inputs can be configured to generate hardware interrupts, while PFx pins defined as outputs can be configured to generate software interrupts. • Flag Interrupt Sensitivity Registers Two Flag Interrupt Sensitivity registers specify whether a single PFx pin is level- or edge-sensitive, and specifies (if edge-sensitive) whether the signal's rising or rising and falling edges are active. One register selects the type of sensitivity, and one register selects which edges are important for edge sensitivity.

Dynamic Power Management

The ADSP-BF535 Blackfin processor offers four operating modes, each with a different performance/power profile. In addition, dynamic power management also provides control functions with appropriate external power regulation capabilities, which can dynamically change the processor core supply voltage to further reduce power consumption. Clock control to each ADSP-BF535 Blackfin processor peripheral also reduces power consumption. See Table 3 for a summary of power settings for each mode.

Fully open operating mode

– Highest performance

In full-on mode, the PLL is enabled and not bypassed, providing the maximum operating frequency. This is the normal execution state where maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.

Active working mode

– Moderate energy saving

In active mode, the PLL is enabled but bypassed. The input clock (CLKIN) is used to generate clocks for the processor core (CCLK) and peripherals (SCLK). When the PLL is bypassed, CCLK runs at half the frequency of CLKIN. Significant power savings can be achieved when the processor runs at half the CLKIN frequency. In this mode, the PLL multiplication ratio can be changed by setting the appropriate value in the SSEL field of the PLL Control Register (PLL-CTL).

When in active mode, supports system DMA access to appropriately configured L1 memory.

sleep mode

– High energy saving

Sleep mode reduces power consumption by disabling the processor core's clock (CCLK). However, the PLL and system clock (SCLK) continue to operate in this mode. Any interrupt, usually through some external event or RTC activity, will wake up the processor. When in sleep mode, the assertion of any interrupt causes the processor to detect the value of the bypass bit (bypass) in the PLL control register (PLL_CTL). If bypass is disabled, the processor will transition to fully on mode. If bypass is enabled, the processor will transition to active mode.

In sleep mode, system DMA access to L1 memory is not supported.

deep sleep mode of operation

– Maximum energy saving

Deep-sleep mode maximizes power savings by disabling clocks to the processor core (CCLK) and all synchronous peripherals (SCLK). Asynchronous peripherals (like RTCs) may still be running, but cannot access internal resources or external memory. This power-down mode can only be exited by asserting a reset interrupt (reset) or by an asynchronous interrupt generated by the RTC. In deep sleep mode, asserting a reset causes the processor to sense the value of the bypass pin. If bypass is disabled, the processor will transition to fully on mode. If bypass is enabled, the processor will transition to active mode. In deep-sleep mode, asserting the RTC asynchronous interrupt causes the processor to transition to full-on mode, regardless of the value of the bypass pin.

The deep sleep output is asserted in this mode.

mode conversion

The available mode transitions shown in Figure 6 can be accomplished through the interrupt events described in the following sections or by programming the PLLCTL register with the appropriate value and then executing the PLL programming sequence.

This sequence of instructions puts the processor into a known idle state and disables interrupts. Note that during mode transitions, all DMA activity should be disabled.

power saving

As shown in Table 4, the ADSP-BF535 Blackfin processor supports five different power domains. The use of multiple power domains maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF535 Blackfin processor into its own power domain, separate from the PLL, RTC, PCI, and other I/Os, the processor can take advantage of dynamic power management without affecting the PLL, RTC, or other I/O /O device.

The power consumed by the processor is largely a function of the processor clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in power consumption, while reducing the voltage by 25% reduces power consumption by more than 40%. Furthermore, these power savings are additive because if both clock frequency and power are reduced, the power savings are significant.

Dynamic power management allows dynamic and independent control of the processor's input voltage (VDDINT) and clock frequency (fCCLK).

As mentioned earlier, power savings can be modeled by the following equation:

Where: fCCLKNOM is the nominal core clock frequency (300 MHz); fCCLKRED is the reduced core clock frequency; VDDINTNOM is the nominal internal supply voltage (1.5 V); VDDINTRED is the reduced internal supply voltage.

For example, how much power savings can be achieved with dynamic power management when both frequency and voltage are reduced, consider an example where the frequency is reduced from its nominal value to 50 MHz and the voltage is reduced from its nominal value to 1.2 V. At this reduced frequency and voltage, the processor consumes about 10% of the power dissipated at the rated frequency and voltage.

Peripheral Power Control

The ADSP-BF535 Blackfin processor provides additional power control capabilities by allowing dynamic scheduling of the clock input to each peripheral. Clocking to each of the peripherals listed below can be enabled or disabled by appropriately setting the peripheral's control bits in the peripheral clock enable register (PLL_IOCK). The peripheral clock enable registers allow individual control of each of these peripherals:

•PCI interface

• EBIT Controller

• Programmable flags

• MemDMA controller

• Motion 0

• Exercise 1

•SPI 0

• SPI No. 1

• UART 0

• Universal Asynchronous Receiver 1

• Timer 0, Timer 1, Timer 2

• USB clock

clock signal

The ADSP-BF535 Blackfin processor can be clocked by a sine wave input or a buffered clock derived from an external clock oscillator.

If a buffered shaped clock is used, this external clock is connected to the processor CLKIN pin. During normal operation, the CLKIN input cannot be stopped, changed, or run below the specified frequency. The clock signal should be a 3.3V LVTTL compatible signal. The processor provides a user-programmable multiplication of the input clock from 1 to 31 to support external-to-internal clock ratios. The MSEL6–0, bypass, and DF pins determine the PLL multiplication factor at reset. At runtime, the multiplication factor can be controlled in software. The combination of pull-up and pull-down resistors in Figure 7 sets a 6:1 core clock ratio that, for example, produces a 150 MHz core clock from a 25 MHz input. See the ADSP-BF535 Blackfin Processor Hardware Reference for other clock multiplication settings.

All on-chip peripherals operate at the rate set by the system clock (SCLK). The system clock frequency is programmable through the SSEL pin. At runtime, the system clock frequency can be controlled in software by writing to the SSEL field in the PLL Control Register (PLL_CTL). The value programmed in the SSEL field defines the division ratio between the core clock (CCLK) and the system clock. Table 5 describes the system clock ratios. The system clock is supplied to the CLKOUT_SCLK0 pin.

The maximum frequency of the system clock is fSCLK. Note that the divisor ratio must be chosen to limit the system clock frequency to the maximum value of fSCLK. The reset value of SSEL1–0 is determined by sampling the SSEL1 and SSEL0 pins during reset. The SSEL value can be changed dynamically by writing the appropriate value to the PLL control register (PLL_CTL), as described in the ADSP-BF535 Blackfin Processor Hardware Reference.

boot mode

The ADSP-BF535 has three mechanisms (see Table 6) for automatically loading the internal secondary memory after reset. The fourth mode is to execute from external memory, bypassing the boot sequence.

The BMODE pin of the reset configuration register sampled during power-on reset and software-initiated reset implements the following modes:

• Execute from 16-bit external memory starting at address 0x2000000, 16-bit packed. The boot ROM is bypassed in this mode. • Booting from 8-bit external flash The 8-bit flash boot routine located in the boot ROM memory space uses the asynchronous memory bank 0 setup. All configuration settings are set for the slowest device possible (3 cycle hold time; 15 cycle R/W access time; 4 cycle settings).

• Boot from SPI serial EEPROM (8-bit addressable) - SPI0 selects a single SPI using the PF10 output pin

EPROM device, submits a read command at address 0x00 and begins clocking data to the beginning of L2 memory. An 8-bit addressable SPI compatible EPROM must be used.

• Boot from SPI serial EEPROM (16-bit addressable) - SPI0 selects a single SPI using the PF10 output pin

EPROM device, submit read command at address

0x0000 and start clocking data to secondary memory. A 16-bit addressable SPI compatible EPROM must be used.

For each of the above boot modes, a four-byte value is first read from the memory device. This value is used to specify the number of subsequent bytes to read into the beginning of the secondary memory space. After each load is complete, the processor jumps to the beginning of the secondary space and begins execution.

Additionally, the reset configuration registers can be set by application code to bypass the normal boot sequence during a software reset. In this case, the processor jumps directly to the beginning of the secondary memory space.

To augment the boot mode, a secondary software loader is provided that adds an additional boot mechanism. This helper loader provides the ability to boot from PCI, 16-bit flash, fast flash, variable baud rates, and more.

Instruction set description

The Blackfin processor family's assembly language instruction set uses an algebraic syntax that is easy to code and read. These instructions are specifically tuned to provide a flexible, densely coded instruction set that compiles to a very small final memory size. The instruction set also provides full-featured multifunction instructions, allowing programmers to use many processor core resources in a single instruction. Combined with many features often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports user (algorithm/application code) and supervisor (O/S cores, device drivers, debuggers, ISRs) operating modes, allowing multiple levels of access to core processor resources.

Assembly language takes advantage of the processor's unique architecture with the following advantages: • Seamlessly integrated DSP/CPU functions optimized for 8-bit and 16-bit operations.

• Super-pipelined multi-problem load/store modified Harvard architecture to support two 16-bit MACs or four 8bit ALUs + two loads/stores + two pointer updates per cycle. • All registers, I/O and memory are mapped into a unified 4 GB memory space, providing a simplified programming model.

• Microcontroller functions such as arbitrary bit and bit field manipulation, insertion and extraction; integer operations on 8-bit, 16-bit and 32-bit data types; and independent user and kernel stack pointers.

• Code density enhancements, including a mix of 16-bit and 32-bit instructions (no mode switching, no code separation). Common instructions are encoded in 16 bits.

development tools

The ADSP-BF535 Blackfin processor supports a full suite of software and hardware development tools, including analog device simulators and the VisualDSP++™ development environment. The emulator hardware that supports the JTAG processor of other emulated devices also fully emulates the ADSP-BF535 Blackfin processor.

The VisualDSP++ project management environment allows programmers to develop and debug applications. The environment includes an easy-to-use assembler (which is based on an algebraic syntax), archiver (librarian/library generator), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler and C/C/ C++ runtime library, which includes DSP and math functions. A key point of these tools is C/C++ code efficiency. Compilers have been developed for efficient translation of C/C++ code into BLIMFAN processor components. BrimFink processors have architectural features that improve the efficiency of compiling C/C++ code.

The VisualDSP++ debugger has many important features. Plotting packages provide great flexibility to enhance data visualization. This graphical representation of user data enables programmers to quickly determine the performance of an algorithm. As the complexity of the algorithm increases, this capability will have greater and greater significance for the designer's development schedule, thereby increasing productivity. Statistical analysis enables programmers to non-invasively poll the processor as it runs the program. This feature unique to VisualDSP++ enables software developers to passively collect important code execution metrics without disrupting the real-time nature of the program. Essentially, developers can quickly and efficiently identify bottlenecks in software. By using the profiler, the programmer can focus on those areas of the program that affect performance and take corrective action.

Using the VisualDSP++ debugger to debug C/C++ and assembler, programmers can: View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory and stack

• Trace instruction execution

• View internal plumbing to further optimize peripherals

• Perform linear or statistical analysis of program execution

• Fill, dump and graphically plot memory contents

VisualDSP++ is a trademark of Analog Devices, Inc.

• Perform source-level debugging

• Create custom debugger windows

VisualDSP++IDDE allows programmers to define and manage software development. Its dialogs and property pages allow programmers to configure and manage all development tools, including color syntax highlighting in the VisualDSP++ editor. These features allow programmers to: • Control how the development tool handles input and generates output

• Maintain one-to-one communication with the tool's command line switches

The VisualDSP++ kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and time constraints of embedded real-time programming. These capabilities enable engineers to develop code more efficiently without having to start from scratch when developing new application code. VDK features include threads, critical and unscheduled areas, semaphores, events, and device flags. The VDK also supports scheduling methods based on priority, preemption, cooperation and time segmentation. Furthermore, the VDK is designed to be extensible. If an application does not use a particular feature, the support code for that feature will be excluded from the target system.

Because the VDK is a library, developers can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When using the VDK, the development environment helps developers with many error-prone tasks, and helps manage system resources, automatically generate various VDK-based objects, and visualize system status when debugging applications that use the VDK.

VCSE is an analog device technology for creating, using, and reusing software components (independent modules with important functions) to assemble software applications quickly and reliably. Download components from the web and put them into the application. Publish component archives from VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Use the expert linker to intuitively manipulate the location of code and data on your embedded system. View memory utilization in color-coded graphs, easily move code and data to different areas of the processor or external memory by dragging the mouse, inspect stack and heap usage at runtime. The Expert Linker is fully compatible with existing Linker Definition Files (LDFs), allowing developers to move between graphical and textual environments.

The analog device emulator adopts the IEEE1149.1 JTAG test access port of the ADSP-BF535 blackfin processor, and monitors the target board processor during the emulation process. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and the processor stack. Non-intrusive in-circuit emulation is ensured by using the processor's JTAG interface. The emulator does not affect target system loading or timing.

In addition to the software and hardware development tools provided by analog devices, third parties also provide a range of tools to support the Blackfin processor family. Third-party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

EZ-KIT Lite™ EZ-KIT Lite provides developers with a cost-effective method for initial evaluation of the ADSP-BF535 Blackfin processor. The EZ-KIT Lite includes a desktop evaluation board and basic debug software for architectural evaluation via a PC-hosted toolset. With EZ-KIT Lite, users can learn more about simulating device hardware and software development tools and prototyping applications. The EZ-KIT toolkit includes an evaluation kit for the VisualDSP++ development environment, including a C/C++ compiler, assembler and linker. The VisualDSP++ software included in the kit is limited in program memory size and is limited to use with the EZ-kit Lite product.

Designed to be compatible with the simulator

Processor board (target)

Analog Devices Family Simulators are the tools every system developer needs to test and debug hardware and software systems. The analog device provides an IEEE1149.1 JTAG Test Access Port (TAP) on the ADSP-BF535 Blackfin processor. This EZ-KIT Lite is a trademark of Analog Devices, Inc.

The emulator uses the TAP to access the internal functions of the processor, allowing developers to load code, set breakpoints, watch variables, watch memory, and inspect registers. The processor must be paused to send data and commands, but once the emulator is done, the processor system is set to run at full speed without affecting system timing.

To use these emulators, the target's design must include a header that connects the processor's JTAG port to the emulator.

For more information on target board design issues, including uniprocessor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see EE-68: JTAG Emulation Techniques for Analog Devices on the Analog Devices website ( ) Reference - Use the site search on "EE-68". This documentation is regularly updated to keep up with improvements in emulator support.

Additional Information

This data sheet provides an overview of the architecture and features of the ADSP-BF535 Blackfin processor. For more information on the core architecture and instruction set of the Blackfin processor family, see the ADSP-BF535 Blackfin Processor Hardware Reference and the Blackfin Processor Instruction Set Reference.

Clock and reset timing

Table 11 and Figure 8 describe the clock and reset operations. Per Absolute Maximum Ratings, page 22, combina-clock multiplier and clock multiplier selection must not exceed 350/300/200 MHz and 133 MHz for core clock and system clock, respectively.

Programmable Flag Period Timing

Table 12 and Figure 9 describe the programmable flag operation.

Timer PWM Output Period Timing

Table 13 and Figure 10 describe the timeout operation. The input signal is asynchronous in "width capture mode" and has an absolute maximum input frequency of fSCLK2.

Asynchronous memory write cycle timing

Table 14 and Figure 11 describe the asynchronous memory write cycle timing.

Asynchronous memory read cycle timing

Table 15 and Figure 12 describe the asynchronous memory read cycle timing.

SDRAM interface timing

For proper operation of the SDRAM controller, the maximum load capacitance for ADDR, DATA, ABE3–0/SDQM3–0, CLKOUT/SCLK1, SCLK0, SCKE, SA10, SRAS, SCAS, SWE, and SMS3-0 is 50 pF.

Universal Asynchronous Receiver Transmitter (UART)

Port receive and transmit timing

Figure 17 depicts the receive and transmit operations of the UART port. The maximum baud rate is SCLK/16. As shown in Figure 17, there is some delay between the generation of the internal UART interrupt and the external data operation. At the data transfer rate of the UART, these delays are negligible.

output drive current

Figure 19 through Figure 21 show the typical current-voltage characteristics of the output driver of the ADSP-BF535 Blackfin processor. These curves represent the current drive capability of the output driver as a function of output voltage. Figure 19 applies to ABE3–0, SDQM3–0, ADDR25–2, AMS3–0, AOE, ARE, AWE, CLKOUT, SCLK1, DATA31–0, DT1–0, EMU, MISO1–0, MOSI1–0, PF15–0, RFS1–0, RSCLK1–0, SA10, SCAS, SCK1–0, SCKE, SCLK0, Deep Sleep, SMS3–0, SRAS, Suspend, SWE, TDO, TFS1–0, TMR2–0, TSCLK1–0 , TX1–0, TXDMNS, TXDPLS, TXEN, and XTAL0 pins. Figure 20 applies to PCI_AD31–0, PCI_CBE3–0, PCI_DEVSEL, PCI_FRAME, PCI_INTA, PCIY-ILDY, PCIYPAR, PCIY-PURR, PCIYRST, PCIIL SerR, PCI Stop, PCI Attempt pins. Figure 21 applies to the PCI-REQ pin.

Power consumption

The total power dissipation consists of two parts: one is caused by the internal circuit (PINT) and the other is caused by the switching of the external output driver (P). Table 26 shows the power consumption of the internal circuit (VDDINT). Internal power consumption depends on the instruction execution sequence and the number of data operands involved. Table 27 shows the power consumption of the phase-locked loop (PLL) circuit (VDDPLL). An external component of the additional total power dissipation is caused by toggling of the output pins. Its size depends on:

• The maximum frequency (f0) at which all output pins can be toggled per cycle

• Load capacitance of all switch pins (C0)

• Voltage fluctuation (VDDEXT)

Calculate the external components using the following formula:

The frequency f consists of driving the load up and down again. For example: In SDRAM burst mode, DATA31–0 pins can be driven at high and low speeds at a maximum rate of 1/(2tsck).

Typical power dissipation under these conditions can now be calculated by adding the typical internal power dissipation:

Note that the conditions that lead to the worst-case PEXT are not the same as the conditions that lead to the worst-case P. The maximum P does not occur when 100% of the output pins switch from all 1s (1s) to all 0s (0s). Also, note that it is uncommon for an application to toggle 100% or even 50% of the output at the same time.

Test conditions

All timing parameters presented in this data sheet are measured under the conditions described in this section.

Output enable time

An output pin is considered enabled when it transitions from a high-impedance state to start driving. The output enable time, tENA, is the interval from when the reference signal reaches a high or low voltage level to when the output begins to drive, as shown in the output enable/disable diagram (Figure 22). The measured time, tENA_, is the interval between when the reference signal switches to when the output voltage reaches 2.0 V (output high) or 1.0 V (output low). Time tTRIP is the interval from when the output starts driving until the output reaches the 1.0v or 2.0v trip voltage. The time tENA is calculated as follows:

If multiple pins are enabled (such as a data bus), the measurement is the measurement of the first pin to start driving.

Output disable time

When output pins stop driving, go into a high impedance state, and begin to decay from the high or low voltage they output, they are considered disabled. The time for the voltage on the bus to decay ∏V depends on the capacitive load CL and the load current IL. This decay time can be approximated by the following equation:

The output disable time, tDIS, is the difference between tDIS_measured and tDECAY, as shown in Figure 22. The measured time tDIS is the time interval from when the reference signal switches until the output voltage decays ∏V from the measured output high voltage or output low voltage. The time tDECAY is calculated with the test loads CL and IL, and ∏V is equal to 0.5v.

System Hold Time Calculation Example

To determine the data output hold time in a particular system, first calculate tDECAY using the formula given above. ∏V was chosen as the difference between the output voltage of the ADSP-BF535 Blackfin processor and the input threshold of the device requiring hold time. A typical ∏V is 0.4 V. CL is the total bus capacitance (per data line) and IL is the total leakage or tri-state current (per data line). The hold time is tDECAY plus the minimum disable time (eg, tDSDAT for an SDRAM write cycle).

environmental conditions

The ADSP-BF535 is packaged in a 260-ball PBGA.

To determine the junction temperature on the application printed circuit board, use:

Where: TJ=junction temperature (C); TCASE=case temperature (C) measured by the customer at the top of the package center.

ΨJT = from Table 28; PD = power consumption (for how to calculate PD)

θJA values are used for package comparison and printed circuit board design considerations. θJA can be used for a first-order approximation of TJ with the following formula:

In the formula: TA = ambient temperature (C)

The theta value is used for package comparison and printed circuit board design considerations when an external heat sink is required.

Theta values are used for package comparison and printed circuit board design considerations. J Type B

In Table 28, airflow measurements conform to JEDEC standards JESD51-2 and JESD51-6, and connection board measurements conform to JESD51-8. Connector-to-housing measurements are in accordance with MIL-STD-883 (Method 1012.1). All measurements were performed using the 2S2P JEDEC test board.

Dimensions