feature

illustrate

Input Voltage Range: 4.75 V to 5.25 V TPS51100 Product Specifications, Documentation and Sourcing Information

terminal conditioner. The device is designed for low cost and low external components. The 3-A sink/source termination conditioner includes a counting system at the expense of space.

Sag compensation only requires 20μF ceramic output capacitor TPS51100 to maintain fast transient response, only 20μF (2 × 10μF) ceramic output is required to support Hi-Z in S3 and soft-off capacitor in S5. The TPS51100 supports remote sensing 1.2-V input (VLDOIN) to help reduce the total power required to power DDR and all functions

dissipate

and DDR2 VTT bus termination, compliant with JEDEC specifications. The part also supports DDR3 integrated divider track 0.5 VDDQSNS for VTT VTT termination with VDDQ of 1.5 V (typ). In and VTTREF In addition, the TPS51100 includes integrated sleep-telemetry (VTTSNS) state control to place VTT in Hi-Z in S3 (suspend to ±20 mV precision RAM for VTT and VTTREF) and soft shutdown for VTT and VTTREF in S5

10mA buffered voltage reference (VTTREF) (suspend to disk). The TPS51100 can be packaged with built-in soft-start, UVLO, and OCL in a thermally efficient 10-pin MSOP power board, specified from -40°C to 85°C.

Thermal shutdown supports JEDEC specification

applications

SSTL-2, SSTL-18 and HSTL terminations

Functional block diagram

Feature description

VTT receiver/power conditioner

The TPS51100 is a 3-a sink/source tracking termination regulator designed for low cost, low external component systems such as notebook computer applications. The TPS51100 integrates a high-performance, low-loss linear regulator capable of sourcing and sinking up to 3 A. This VTT linear regulator employs a final fast response feedback loop such that a small ceramic capacitor is sufficient to track VTTREF within ±40 mV under all conditions, including fast load transients. To achieve tight regulation of the minimum tracking resistance effect, the remote sensing terminal VTTSNS should be connected to the positive node of the VTT output capacitor as a separate tracking for the VTT high current line.

VTTREF regulator

The VTTREF block consists of an on-chip 1/2 divider, low pass filter (LPF) and buffer. This regulator can generate up to 10mA of current. Bypass VTTREF to GND with a 0.1µF ceramic capacitor to ensure stable operation.

Characterization (continued)

soft start

The soft-start function of the VTT is achieved by a current clamp, which allows the output capacitor to be charged with a low and constant current, thereby causing the output voltage to rise linearly. The current limit threshold is changed in two stages using the internal powergood signal. When VTT exceeds the powergood threshold, the current limit is 2.2 A. The current limit switches to 3.8 A when VTT is above (VTTREF–5%) or below (VTTREF+5%). Thresholds are typically ±5% of VTTREF (adjusted from external to internal) and ±10% (when it falls outside). The soft-start function is completely symmetrical, it operates not only from GND to VTTREF voltage, but also from VDDQ to VTTREF voltage. Note that during the S3 state, the VTT output is in a high impedance state (S3=low, S5=high) and its voltage can be as high as the VDDQ voltage, depending on external conditions. Note that VTT cannot start under full load conditions.

VTT current protection

The LDO has a constant overcurrent limit (OCL) at 3.8a. This trigger point drops to 2.2a before the output voltage is within ±5% of the target voltage or exceeds ±10% of the target voltage.

Vehicle Identification Number UV Protection

For VIN under-voltage lockout (UVLO) protection, the TPS51100 monitors the VIN voltage. When the VIN voltage is below the UVLO threshold voltage, the VTT regulator is turned off. This is non-latching protection.

thermal shutdown

The TPS51100 monitors its temperature. If the temperature exceeds a threshold (typically 160°C), the VTT and VTTREF regulators are turned off. This is also a non-latching protection.

Device functional mode

1 S5 control and soft close

The S3 and S5 terminals should be connected to the SLP_S3 and SLP_S5 signals respectively. Both VTTREF and VTT are turned on in the S0 state (S3=high, S5=high). VTTREF remains active when VTT is off and remains high impedance in the S3 state (S3=low, S5=high). In the S4/S5 state, both the VTT and VTTREF outputs are turned off and discharged to ground through the internal mosfet (both S3 and S5 are low).

Application Information

The TPS51100 is typically used as a sink/source tracking termination regulator, switching the converter voltage from VTT.

typical application

TPS51100 5-V Input/1.8-V Output Reference Design

output capacitor

For stable operation, the total capacitance at the VTT output can be equal to or greater than 20µF. Connect two 10µF ceramic capacitors in parallel to minimize the effects of ESR and ESL. If the ESR is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input for loop stability. The time constant of the RC filter should be almost equal to or slightly lower than the time constant of the output capacitor and its ESR.

The soft-start duration, tSS, is also a function of the output capacitance. In the formula, ITTOCL=2.2 A (typical value), tSS can be calculated as,

input capacitor

According to the tracking impedance of the VLDOIN bulk power supply to the part, the instantaneous increase in source current is mainly provided by the charge of the VLDOIN input capacitor. Use a 10µF (or more) ceramic capacitor to provide this transient charge. More input capacitance is provided when the VTT uses more output capacitance. In general, use 1/2 COUT as the input.

VIN capacitor

Add a ceramic capacitor with a value between 1µF and 4.7µF placed close to the VIN pin to stabilize 5v from any parasitic impedance from the power supply.

Apply Curve

Power Recommendations

The TPS51100 is designed for sink/source double data rate (DDR) termination regulators with VTTREF buffered reference outputs. The power input voltage (VIN) supports voltages from 4.75 volts to 5.25 volts; VLDOIN supports input voltages from 1.2 volts to 3.6 volts.

Layout Guidelines

Before you start laying out your TPS51100 design, consider the following points.

Input bypass capacitors for VLDOIN should be placed as close to the pins as possible with short, wide connections.

The output capacitor of the VTT should be placed near the pins with short and wide connections to avoid additional ESR and/or ESL tracking.

VTTSN should be connected to the positive node of the VTT output capacitor as a separate channel from the high current supply line, it is strongly recommended to avoid additional ESR and/or ESL. If the voltage at the point of load needs to be sensed, it is recommended to connect an output capacitor at that point. Also, it is recommended to minimize any additional ESR and/or ESL of the ground trace between the ground pin and the output capacitor.

If the ESR of the VTT output capacitor is greater than 2 mΩ, consider adding an LPF at VTTSN.

VDDQSNS can be connected separately from VLDOIN. Remember, this induced potential is the reference voltage for VTTREF. Avoid any noise generating lines.

The negative nodes of the VTT output capacitor and the VTTREF capacitor should be connected together to avoid common impedance with the high current paths of the VTT source/sink current.

The GND (signal GND) pin node represents the reference potential for VTTREF and the VTT output. Connect GND to the negative node of the VTT capacitor, VTTREF capacitor, and VDDQ capacitor, taking care to avoid additional ESR and/or ESL. GND and PGND (Power GND) should be isolated with a single point connection between them.

To effectively remove heat from the package, prepare thermal pads and solder to the package thermal pads. Extensive traces of component-side copper connected to this hot soil aid in heat dissipation. A number of 0.33 mm diameter vias should be used to connect from the heat sink to the internal/solder side ground plane to aid heat dissipation.

layout example

Note: 1. The positive terminal of each output capacitor should be connected directly to the VTT of the IC; do not use vias.

2. The negative terminal of each output capacitor should be connected directly to the GND of the IC; do not use vias.

3. Via

Pass between the first and second layers

Go through layers 1 and 2 and the other layers under the 4th layer. Rs and Cs with dashed outlines are optional.

TPS51100 Printed Circuit Board Layout Guidelines

Thermal factor

Since the TPS51100 is a linear regulator, VTT current flow in both the source and sink directions produces power dissipation from the device. In the source phase, the potential difference between VVLDOIN and VVTT multiplied by the VTT current becomes the power dissipation WDSRC.

WDSRC=(VVLDOIN-VVTT)'IVTT(2)

In this case, the power loss can be reduced if VLDOIN is connected to a backup power supply that is lower than the VDDQ voltage.

For the sink phase, the VTT voltage is applied to the internal LDO regulator, and the power dissipation and WDSNK are calculated by:

WDSNK=VVTT-VTT'I(3)

Since the device does not sink and supply current at the same time, and the IVTT varies rapidly over time, the actual power dissipation that must be considered in thermal design is the average of the duration of thermal relaxation across the system. Another power consumption is the current from the Vehicle Identification Number (VIN) and Vehicle Identification Number (VLDOIN) power supplies for the internal control circuits. Under normal operating conditions, this can be estimated at 20 megawatts or less. This force must be effectively dissipated from the package. The maximum power dissipation allowed by the package is calculated as,

Thermal Factors (continued)

TA(max) is the maximum ambient temperature in the system θJA is the thermal resistance of the silicon junction to ambient

This thermal resistance is highly dependent on the layout of the board. The TPS51100 is assembled in a thermally enhanced PowerPAD package with an exposed die pad under the body. To improve thermal performance, this die pad must be connected to the ground trace via thermal solder rings on the PCB. This ground trace acts as a heat sink/heat sink. Typical thermal resistance is 57.7°C/W based on a 3 mm x 2 mm thermal pad with two vias and no airflow. It can be improved by using larger heatsinks and/or increasing the number of vias. For example, assuming a 3 mm x 3 mm thermal pad with four vias and no airflow, the temperature is 45.4°C/W. For more information on the PowerPAD package and its recommended board layout, see the PowerPAD Thermally Enhanced Packaging Application Report (SLMA002).

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Electrostatic discharge precautions

These devices have limited built-in ESD protection. During storage or handling, the wires should be shorted together, or the device should be placed in conductive foam to prevent electrostatic damage to the MOS gate.

Glossary