The ISL6545 enables the realization of a complete DC/DC buck control protection scheme for converter topologies driving N-channel mosfets in synchronous bucks. Because it can work with 5V or 12V supplies, one IC can be used in the system. The ISL6545 integrates control, gate driver, output regulation, monitoring and protection functions into an 8Ld SOIC or 10 Ld DFN package. The ISL6545 provides single feedback loop, voltage mode control with fast transient response. The output voltage can be precisely regulated to 0.6V with a maximum temperature and line voltage tolerance of ±1.0% variation. Selectable fixed frequency oscillators (ISL6545 for 300kHz; ISL6545A for 600kHz) reduce design complexity while balancing typical application cost and efficiency. The error amplifier has a gain bandwidth product of 20MHz and a slew rate of 9V/µs, enabling high converter bandwidth for fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. Overcurrent protection consists of monitoring the rDS(ON) of the lower MOSFET to suppress proper PWM operation. This approach simplifies by eliminating the need for a current sense resistor.

feature

Operates from +5V or +12V supply voltage (for biasing) -1.0V to 12V VIN input range (at limits; see Input Voltage Notes) -0.6V to VIN output range - Integrated gate driver Using VCC (5V to 12V) -0.6V internal reference; 1.0% tolerance

Simple single-loop control design - voltage-based PWM control - driving N-channel mosfet

Fast Transient Response - High Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle

Lossless, Programmable Overcurrent Protection - Uses Lower MOSFET's rDS(On)

Small converter in 8 Ld SOIC or 10 Ld DFN - 300kHz or 600kHz fixed frequency oscillator - fixed internal soft start, able to enter pre-bias loading

Integrated Boot Diode - Enable/Disable Function on COMP/SD Pin - Output Current Source and Notch

Lead-free plus annealed (RoHS compliant) available

application

Power supplies for microprocessors or peripherals - personal computers, embedded controllers, memories - power supplies for digital signal processors and core communication processors

Subsystem Power - PCI, AGP; Graphics Card; Digital TV - SSTL-2 and DDR/DDR2/ DDR3 SDRAM Bus Termination Supply

Cable Modems, Set-Top Boxes, and DSL Modems

Industrial Power; Universal Power

5V or 12V input DC/DC regulator

Low Voltage Distributed Power

Absolute Maximum Ratings Thermal Information

Supply voltage, VCC. Ground -0.3V to 15V

Start-up voltage, VBOOT. Ground -0.3V to 36V

Wear voltage VUGATE. Phase V -0.3V to VBOOT+0.3V

LGATE/OCSET voltage, VLGATE/OCSET ground -0.3V to VCC+0.3V

Phase voltage, V phase. Ground -0.3V to VBOOT+0.3V

Upper driver supply voltage, VBOOT-V phase. 15 volts

Clamping Voltage, VBOOT-VCC. 24 volts

FB, COMP/SD voltage. Ground -0.3V to 6V

Electrostatic discharge classification, HBM. 1.5kV

Electrostatic Discharge Classification, MM. 150 volts

ESD classification, CDM. 1.0 kV

operating conditions

Supply voltage, VCC. +5V±10%, +12V±20%, or 6.5V to 14.4V

Ambient temperature range

ISL6545C, ISL6545AC. 0°C to +70°C

ISL6545I, ISL6545AI. -40°C to +85°C

junction temperature range. -40°C to +125°C

Thermal resistance θJA (°C/W) θJC (°C/W)

SOIC package (Note 1). 95 knives

DFN package (Note 3). 44 5.5

Maximum junction temperature

(Plastic Packaging). +150 degrees Celsius

Maximum storage temperature range. -65°C to +150°C

Maximum lead temperature

(10 seconds of soldering). +300 degrees Celsius

(SOIC - lead only)

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation of the device under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

1. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air. See Technical Bulletin TB379 for details.

2. θJA is measured with components with "direct attach" characteristics mounted on a high efficiency thermal conductivity test board in free air. See Technical Bulletin TB379 for details.

3. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

4. Guaranteed by design; not production tested

Electrical Specifications Test Conditions: VCC=12V, TJ=0~85°C, unless otherwise specified

Electrical Specifications Test Conditions: VCC=12V, TJ=0~85°C, unless otherwise specified. (continued)

Function pin description (SOIC, DFN)

VCC (SOIC pin 5, DFN pin 6) This pin provides the bias supply for the ISL6545, as well as the lower MOSFET gate and upper MOSFET gate. The internal 5V regulator will provide if VCC rises above 6.5V (but LGATE/OCSET and start-up will still be provided by VCC). Connect a well decoupled 5V or 12V power supply to this pin. FB (SOIC pin 6, DFN pin 8) This pin is the inverting input of the internal error amplifier. Use FB, in conjunction with the COMP/SD pin, to compensate for the converter's voltage control feedback loop. A resistor divider from the output to ground is used to set the regulation voltage. Ground (SOIC pin 3, DFN pin 4) This pin represents the IC's signal and power ground. Put this pin through the lowest impedance connection available. For DFN packages, Pin4 must be connected to electrical ground; under the metal pad package should also be connected to the GND thermal conductivity plane. Phase (SOIC pin 8, DFN pin 10) connect this pin to the power supply of the upper MOSFET, and the drain of the lower MOSFET. It is used as a Ugart driver and monitors the voltage drop through low MOSFET overcurrent protection. This pin is also monitored by the adaptive shoot-through protection circuit to determine when the upper MOSFET is turned off. Wear (SOIC pin 2, DFN pin 2) connects this pin to the gate of the upper MOSFET; it provides gate drive controlled by PWM. It is also used to determine when the upper MOSFET is turned off. Sheath (SOIC pin 1, DFN pin 1) This pin provides the ground referenced bias MOSFET driver to the top. The bootstrap circuit is used to generate a voltage suitable for driving the N-channel MOSFET (equal to the VCC negative drop on the boot diode on the chip), with respect to phase.

COMP/SD (SOIC pin 7, DFN pin 9) This is a multiplexed pin. During soft-start and normal inverter operation, this pin represents the output of the error amplifier. Use COMP/SD in conjunction with the FB pin to compensate the converter's voltage control feedback loop. Pulling compressor/SD low (Vdisable = 0.4V nominal) will shut down (disable) the controller, causing the oscillator to stop, the LGATE and UGATE outputs to remain low, and the soft-start circuit to re-arm. The external pull-down device initially needs to overcome up to 5mA of COMP/SD output current. However, once the IC is disabled, the COMP output will also be disabled, so only the 20µA current source will continue to draw current. When the pull-down is released, the COMP/SD pin will begin to rise at a rate determined by the 20µA charge that increases the capacitance of the COMP/SD pin. When the COMP/SD pin is above the disabled trigger point the ISL6545 will start a new cycle of initialization and soft-start. LGATE/OCSET (SOIC pin 4, DFN pin 5) connects this pin to the gate of the lower MOSFET; it provides gate drive (from VCC) controlled by PWM. This pin is also monitored by the adaptive shoot-through protection circuit to determine when the lower MOSFET is turned off. This pin is also used to determine the converter's overcurrent threshold during a short period of time after power-on reset (POR) or shutdown release. Connect a resistor (ROCSET) from this pin to GND. See Flow Protection Section Equation. An overcurrent trip is cycled after two soft-start functions with virtual soft-start timeout. Some describing LGATE functions may omit the OCSET part of the name when it is not relevant to the discussion.

N/C (DFN only; pin 3, pin 7)

These two pins in the DFN package are not connected. Function Description Initialization (POR and OCP sampling). Figure 1 shows a simplified timing diagram. The power-on reset (POR) function continuously monitors the VCC pin. Once the rising POR threshold (VPOR ~4V nominal) is exceeded, the POR function initiates overcurrent protection (OCP) sample-and-hold operation (when COMP/SD is ~1V). When the sampling is complete, you start the soft-start ramp. If the COMP/SD pin is held low during power-up, initialization is delayed until it is released and the COMP/SD voltage is above the disabled trigger point.

Figure 2 shows a typical power-up sequence in more detail. Initialization starts at T0 when either VCC rises to VPOR, or the COMP/SD pin is released (after POR). This COMP/SD will be sourced high by an internal 20µA current, but timed until COMP/SD exceeds the VDISABLE trip point (T1). The capacitance of the external disable device, as well as the compensation capacitor, will determine that the 20µA current source will charge the COMP/SD pin. with typical values, with soft-start time. Compressor/SD will continue to rise to ~1V. From T1, there is a nominal 6.8ms delay, which allows the VCC pin to exceed 6.5V (if rising to 12V) so that the internal bias regulator can fully turn on. At the same time by disabling the LGATE driver, initialize the LGATE/OCSET pin to draw IOCSET (nominal 21.5µA) via ROCSET. This setting represents the voltage at the OCSET trip point. At T2, the OCP's sample and hold operates with a variable period of time (0 to 3.4ms nominal; at higher overcurrent settings). Sample and Hold uses a digital counter and DAC to save the voltage, so the stored value does not degrade as long as VCC is above VPOR. See Current Protection, Equations and Variables on page 7. After the sample is completed and held at T3, the soft-start operation starts and the output voltage rises between T4 and T5.

Soft-Start and Pre-Biased Output Functionally, the soft-start will internally reference the ramp to the non-inverting terminal of the error amplifier, from 0 to 0.6V nominally for 6.8ms The output voltage will follow the ramp, from zero to the final value, at The same 6.8ms (the actual ramp time seen on the slip will be less than the nominal time some initialization time, between T3 and T4) for the following reasons. The ramps are created digitally, so there will be 64 small discrete steps. There is no easy way to change this ramp speed externally, for ICs (300kHz or 600kHz). After the initialization period (T3 to T4), the error amplifier (COMP/SD pin) is enabled and starts regulating the output voltage of the inverter during soft start. The oscillator's triangle wave compares the voltage with the ramp error amplifier. This produces a phase pulse of increased width to charge the output capacitor. When the internally generated soft-start voltage exceeds the reference voltage (0.6V), the soft-start is completed and the output should be at the expected voltage. This method provides a fast and controllable output voltage rise; no large inrush currents charge the output capacitors. Ball's entire start-up routine typically takes 17ms; delay and OCP take 10.2ms samples, and the soft-start ramp is 6.8ms.

Figure 3 shows the normal curve in blue; initialization starts at T0 and the output ramps between T1 and T2. If the output pre-bias is less than expected, as shown by the magenta curve, the ISL6545 will detect the condition. Neither MOSFET turns on until the ramp voltage exceeds the output until soft-start; VOUT seamless start-up starts there. If the output pre-bias is higher than expected, as in the red curve, the MOSFET will remain on until the end of the soft-start, at which time it will pull the output voltage down to its final value. Any resistive load connected to the output will contribute to the voltage (output capacitance at the RC rate of the load R and C).

If the VIN of the upper MOSFET drain comes from a different supply after VCC, the soft-start cycles through it, but there is no output voltage ramp. When the VIN is on, the output will follow the VIN ramp (at near 100% duty cycle, COMP/SD pin > 4V) from zeroing to the final desired voltage. If VIN is too fast, then there may be excessive inrush current charging the output capacitor (only at the beginning of the ramp, going from zero to you is important here). If this is not acceptable then consider changing the order of the power supplies, or sharing the same supply, or adding sequencing logic to the COMP/SD pin to delay soft start until VIN power is ready (see Input Voltage Considerations ). If the IC is disabled after soft-start (by pulling the COMP/SD pin low), then enabled (by releasing the COMP/SD pin), then full initialization (including the OCP example) takes place. However, retry on overcurrent. If the output is shorted to ground during soft-start, the OCP will handle it as described in the next section. Over Current Protection (OCP) The over current function protects the converter from short circuits using the lower MOSFET on-resistance rDS(on) output, monitoring the current. Resistor (ROCSET) to overcurrent trip level (see Typical Application Diagram). This method improves the efficiency of the converter and reduces the cost by eliminating the current sense resistance. If overcurrent is detected, the output shuts down immediately, cycling the soft-start function in hiccup mode (2 virtual soft-start timeouts, providing fault protection. If the short-circuit condition is not removed, this cycle will continue indefinitely

After POR (and 6.8ms delay), the ISL6545 starts the overcurrent protection sample-and-hold operation. This source disables the LGATE driver to allow the internal 21.5µA current to generate a voltage on ROCSET. Island 6545 samples this voltage (referenced to the GND pin) on the LGATE/OCSET pin and saves it in the counter and DAC combination. The sampled voltage is held internally as long as power is applied, over the current setpoint, or until a new sample is taken from the off state. The actual monitoring of the low MOSFET on-resistance begins with a logic signal (creating a rising external LGATE signal) 200ns (nominal) after the end of the internal pulse width modulation. This is done to allow gate transition noise and ringing to be resolved before monitoring the phase pins. Monitor ends low when the internal PWM edge (and therefore LGATE) moves. OCP windows can be detected anywhere above. If the regulator is operating at a high wear duty cycle (75% at about 600kHz and 87% at 300kHz, then the LGATE pulse width may not be wide enough for the OCP to properly sample the rDS(on). 3 consecutive pulses are too narrow (or not at all), then the third pulse will be stretched and/or inserted with a minimum width of 425ns. This allows the OCP to monitor each third pulse in this case .This can introduce a pulse width error in the output voltage to be corrected on the next pulse; the output ripple voltage will have an unusual 3 clock pattern, which may look like jitter. This is not necessarily a problem, more of a The compromise keeps the OCP at a higher duty cycle. If the OCP is disabled (by choosing a ROCSET value that is too high, or no resistor), then the pulse stretching feature is also disabled. Figure 4 shows the LGATE pulse width stretching, with the width becomes smaller.

The overcurrent function will trip on inductor current peaks (IPEAK) by

where IOCSET is the internal OCSET current source (21.5µA typical). The scale factor of 2 is the voltage drop across the MOSFET compared to the setting on the ROCSET resistor. The OC trigger point varies mainly in the system due to the rDS(ON) variation of the MOSFET (overprocessing, current and temperature). To avoid overcurrent tripping over the normal operating load range, find the ROCSET resistor from the equation above:

1. Maximum junction maximum rDS(on) temperature.

2. Minimum IOCSET in spec sheet.

3. Determine IPEAK, where ΔI is the output inductor ripple current. The equation for ripple current, See Output Inductor Selection. The detected allowable voltage range (2*IOCSET*ROCSET) is 0 to 475mV; but the actual range is a ballpark (500 to 3000Ω) where mosfets are typically 20 to 120mV. If the voltage drop on ROCSET is set too low, this can result in almost continuous OCP trips and retries. It is also very sensitive to system noise and inrush current spikes and should be avoided. The maximum usable setting is around 0.2V of ROCSET (around 0.4V of ROCSET MOSFET); higher than this value may disable protection. A voltage drop across ROCSET greater than 0.3V (0.6V MOSFET trip point) will disable the OCP. The preferred way to disable OCP is to simply remove the resistor; will be detected as having no OCP.

The detected allowable voltage range (2*IOCSET*ROCSET) is 0 to 475mV; but the actual range is a ballpark (500 to 3000Ω) where mosfets are typically 20 to 120mV. If the voltage drop on ROCSET is set too low, this can result in almost continuous OCP trips and retries. It is also very sensitive to system noise and inrush current spikes and should be avoided. The maximum usable setting is around 0.2V of ROCSET (around 0.4V of ROCSET MOSFET); higher than this value may disable protection. A voltage drop across ROCSET greater than 0.3V (0.6V MOSFET trip point) will disable the OCP. The preferred way to disable OCP is to simply remove the resistor; will be detected as having no OCP. Note that conditions during power up or retries may appear different from normal operation. In a 12V system, the IC starts working above 4V; if the supply ramp is slow, the soft-start ramp may go well before 12V. So when energized when the gate drive voltage is low, the rDS(ON) of the mosfet will be higher, effectively reducing catenary tripping. Also, the ripple current may be different at lower input voltages. Another factor is the digital nature of the soft-start ramp. Turning on each discrete voltage step actually has a small load transient, as well as a current spike capacitor charging the output. The height of the current spike is not controlled; it is affected by the step size of the output, the output capacitance, and the IC error amplifier compensation. Therefore, it is possible to trip over current with magnetizing inrush current in addition to normal load and ripple considerations.

Figure 5 shows the output shorted to ground during retry. At time TO, the output has shut down due to the sensed overcurrent condition. Are there two internal soft-start delay periods (T1 and T2) to allow the mosfet to cool down in order to keep the average power dissipated when retrying at an acceptable level. At time T2 the output starts a normal soft-start cycle and the output tries to ramp. If the short circuit remains and the current reaches any time during the OCSET soft-start ramp, the trip point output will turn off and return to time T0 to delay the cycle again. So the retry period is two dummy soft-start periods plus a variable 1 (which depends on tripping the sensor each time). Figure 5 shows an example output that is about halfway down before shutting down; therefore, the retry (or hiccup) time will be around 17ms. Minimum should be nominally 13.6ms maximum 20.4ms. If the short state eventually clears, on the next T2 cycle, the output should rise normally. Booting into a shorted load looks like retrying into the same shorted load. In both cases, the OCP is always enabled on soft start; once it trips, it will enter a retry state (hiccup) mode. The retry period will always have two dummy timeouts, plus whatever portion of the actual soft-start time passes before detection and shutdown; at which point the logic immediately starts a new two dummy period timeouts.

OUTPUT VOLTAGE SELECTION The output voltage can be programmed to an internal reference voltage of 0.6 volts up to the VIN supply. The ISL6545 can operate at nearly 100% duty cycle at zero load, but the rDS(ON) of the upper MOSFET will effectively be limited to something smaller as the load current increases. Additionally OCP (if enabled) will also limit the maximum payload cycle. An external resistor divider is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. See Typical Application Schematic on page 2 for more details; RS is the upper resistor; ROFFSET (abbreviated RO below) is the lower one. The suggested value for RS is 1-5kΩ (±1% for accuracy), then according to the equation below. Because RS is part of the compensation circuit (see the Feedback Compensation section), it is usually easier to change ROFFSET to change the output voltage; this way the compensation calculation does not need to be repeated. If VOUT=0.6V, ROFFSET can remain open. Output voltages below 0.6V are not available.

Input Voltage Considerations

The typical application diagram on page 2 shows VCC as 5V (±10%) or 12V (±20%); in each case, the gate driver uses the voltages of VCCLGATE and BOOT/UGATE. Also, VCC is the maximum allowed to operate anywhere from 6.5V to 14.4V. A VCC range between 5.5V and 6.5V is not a reason for long term reliability, but transitions through it to voltages above 6.5V are acceptable. There is an internal 5V bias regulator; it is at 5.5 and 6.5V; some delay after the POR allows the typical supply voltage to rise above 6.5V before the soft-start ramp begins. This prevents disturbing the output, due to the internal regulator being turned on or off. If the transition is slow (not a step change), the disturbance should be minimal. So while the recommendation is not to enable output during transitions through this area, it's probably acceptable. Users should monitor their applications for problems. The VIN of the upper MOSFET can share the same power supply as VCC, but can also be supplied separately or from other sources such as the output of other regulators. If the VCC power supply goes up first, until the initialization is complete, the soft start will not be able to ramp the output, and the output will later follow the VIN ramp at the time of application. If not, then change the order of the supplies, or use the COMP/SD pin to disable VOUT until both supplies are ready. Figure 6 shows a simple sequencer in this case. If VCC is powered on first, Q1 is off, R3 pulls VCC to turn Q2 on, making the ISL6545 off. Resistor dividers R1 and R2 determine when Q1 turns on when VIN turns on, which turns off Q2, and releases it off. If the VIN is powered up first, Q1 will be on and Q2 will be off; so the ISL6545VCC will start as soon as it appears. An impractical travel point is 0.4V nominal, so various NFETs or NPNs or even some logic ICs can be used as Q1 or Q2; but Q2 must be low leakage when closed (drain or sump open) to avoid Interfere with the COMP output. Question 2 should also be placed near the COMP/SD pins.

The VIN range can be as low as ~1V (as low as 0.6V reference for VIN). up to 20 volts below the VIN). There are some limited voltages for high VIN operation. The first thing to consider for a high VIN is the maximum cranking time voltage of 36V. VIN (as indicated by phase) plus VCC (starting voltage - minus diode drop), plus any ringing (or other transients on the start pin must be less than 36V. If the VIN is 20V, this Limits the VCC plus ring to 16V. The second consideration for high VIN is the (boot - VCC) voltage; must be less than 24 volts BOOT = VIN + VCC + ring, reducing to (VIN + ring) must be less than 24 volts. So according to Typical circuits, 20V max VIN is a good starting assumption; users should verify that ringing in their particular application. Another consideration for high VINs is the duty cycle. Very low duty cycles (eg. 20V input to 1.0V output with 5% duty cycle) requires component selection compatible with that selection (e.g. low rDS(ON) low MOSFET and good LC output filter). At the other extreme (e.g. 20V input to 12V output), the upper MOSFET needs a low rDS (on). Also, if the duty cycle is too high, it will affect the overcurrent sampling time. In all cases, the input and output capacitors and both mosfets must operate according to the current voltage Nominal. Switching Frequency Switching frequency is fixed 300 or 600 kHz, depending on part number selected (300 kHz for ISL6545; 600 kHz for ISL6545A; generic name "ISL6545" may apply in the rest of this document unless frequency is selected) .However, all other mentioned times (POR delay, OCP sampling, soft-start, etc.) are independent of clock frequency (unless otherwise stated). Boot Refresh If the molar is left on for an extended period of time, the charge on the boot capacitor will start to drop , raises the rDS(ON) of the upper MOSFET. Island 6545 detects long wear (100µs nominal) circuits and forces LGATE to rise for one clock cycle, which gives the boot capacitor time to charge.

Also, the OCP circuit has an LGATE pulse stretcher (to ensure the sampling time is long enough), which can also help with refresh initiation. But if OCP is disabled (no current sense resistor), the regular boot refresh circuit will still be active.

current sink

The ISL6545 integrates a MOSFET punch through a protection method that allows the converter to sink current as well as source current. When designing a converter with the ISL6545 known, the converter may sink current. When the converter sinks current, it behaves as a boost converter regulating the input voltage. This means that the converter is injecting current into the VCC rail that provides the bias voltage for the ISL6545. If there is nowhere to go, like loads on other VCC rails, protecting the capacitors on the VCC bus by voltage limiting will sink current. This condition will allow the voltage level to increase over the VCC rail. If the voltage level of the rail is raised to a level that exceeds the maximum rated voltage in the ISL6545, the IC will experience an irreversible failure and the converter will no longer work. Making sure the current has a path for the capacitors on the rails will prevent this failure mode.

Application Guide

Layout Considerations

In any high frequency switching converter, layout is very important. Switching current from one power supply to another can be done in interconnecting wires and circuit traces. These interconnect impedances should be achieved by using wide, shorted printed circuit traces. Critical components should be constructed as close to the ground plane as possible or grounded at a single point.

Figure 7 shows the key power components of the converter. To minimize voltage overshoot, interconnecting wires represented by thick lines should be ground or part of the power plane on the printed circuit board. The parts shown should be as close together as possible. Note that capacitors CIN and CO can each represent many physical capacitors. For best results, position the ISL6545 at the mosfet, Q1 and Q2. The circuit traces of the MOSFETs must be sized to the gate and source connections of the ISL6545 to handle peak currents up to 1A.

Figure 8 shows that additional layout considerations are required. The structure of the circuit shown using a single point and a ground plane. To minimize leakage current paths on the COMP/SD pin and locate the resistor, ROSCET is close to the COMP/SD pin as the internal current source is only 20µA. Provide local VCC decoupling between the VCC and GND pins. Position the capacitors, CBOOT, as close to the start and phase pins as possible. All components used for feedback compensation (not shown) should be as close to the IC as possible.

feedback compensation

This section focuses on design considerations for voltage-mode controllers that require external compensation. To address a wide range of applications, a Type 3 feedback network is recommended, as shown at the top of Figure 9. Figure 9 also highlights the synchronous rectification buck converter for the ISL6545 circuit. The output voltage (VOUT) is regulated to the reference voltage, VREF. The error amplifier output (COMP pin compares the voltage) to the oscillator (OSC) modified sawtooth wave to provide the VIN amplitude at the PWM wave phase node. The PWM wave is smoothed by the output filters (L and C). The series resistance E is used for the equivalent series resistance of the output filter capacitor bank.