Features

High driver mode:

- Gigabawa (g u003d 100): 120 MM

- Conversion rate: 115 v/μs

-4-V step 16-bit stability: 280 NS

-This low-pressure noise: 10 kHz is 2.5 nv/√Hz

-Low output impedance: 1 MHz The time is 1Ω

-The offset voltage: ± 100 μV (maximum)

-The offset voltage drift: ± 3 μV/OC (maximum value)

- Low static current: 2 MA (typical value)

Low -power consumption mode:

- Gigabawa: 1 megaphris

- Low static current: 270 μA (typical value)

Power supply scalability function:

-Super -fast conversion mode from low power to high -driving: 170 ns

DC accuracy:

-Low distortion: at 100 kHz, HD2 is -122 DBC, HD3 is -140 dbc

-The input covarrantation range includes negative

-orbit Inter-output

-Wide temperature range: completely specified from -40 ° C to+125 ° C

123] Precision reference voltage buffer

programmable logic controller

test and measurement equipment

Electricity sensitive data acquisition system

Instructions

OPAX625 series operational amplifier is excellent 16 -bit and 18 -bit SAR ADC drive, which has high precision, low THD and noise. Program. The characteristics of this series of equipment and the specified 16 -bit stability time are 280 nan seconds, making it possible for the real 16 -bit valid digit (ENOB). In addition to the high DC accuracy of only 100μV bias voltage, the width of 120MHz, and the low broadband noise of 2.5NV/√Hz, this series is also optimized to drive high throughput and high -resolution SAR ADC, such as SAR ADC ADS88XX series.

OPAX625 has two working modes: high driver and low power consumption. Under the innovative low -power mode, OPAX625 tracks the input signal, allowing OPAX625 to be 170 nThe Sobes transition from a 16 -bit ENOB from a low power mode to a high -driving mode.

The OPAX625 series has 6 stitches SOT and 10-needle VSSOP packaging, and is specified at the temperature of -40 ° C to+125 ° C.

SAR ADC driver

(1), please refer to the end of the data table at the end of the data table. Order appendix.

(2), OPA2625 is a product preview version.

Switch feature

When TA u003d 25 ° C, (v+) u003d 5V, (v-) u003d 0V, mode pins connect to V to V Pin, g u003d 1, vCom u003d vo u003d 2.5V, CLOAD u003d 20pf, road u003d 1kΩ, connect to 2.5V (unless otherwise explained).

Typical features

in TA u003d 25 ° C, v+u003d 5 v, v-u003d 0 v, mode u003d v-, vo u003d vo u003d 2.5 V, G u003d 2, RF u003d 1 KΩ, CF u003d 2.7 PF, CLOAD u003d 20 PF, RLOAD u003d 2 KΩ, connected to 2.5 V (unless there is another instructions).

] Parameter measurement information DC parameter measurement The circuit shown in FIG Measure the DC input offset related parameters of OPAX625. This circuit can measure the input disorder voltage, power suppression ratio, co -mode suppression ratio, and open ring gain. The basic test program requires that the input (power supply voltage VS and co -mode voltage VCM) is set to the required value. Drive the loop by adjusting the measuring value of the VO. After all inputs are configured, the input input offset at the VX measuring point. Remove the measurement results at 101 and calculate the input offset voltage. Changing the voltage at different inputs will change the input offset voltage. The input parameters can be measured according to the relationship between type 1 to 5. Instant parameter measurement

FIG. 64 The circuit shown in FIG. 64 The circuit shown in FIG. Configure V+, V -, RISO, RLOAD and CLOAD. Monitor the input and output voltage on the oscilloscope or other signal analyzers. Use this circuit to measure large signals and small signals transient response, conversion rate, and overrunQuantity and capacity load stability.

AC parameter measurement

FIG. 65 The circuit shown in FIG. 65 The circuit used to measure the AC parameters of OPA625. Configure V+, V-and CLOAD as needed. THS4271 is used to buffer the input and output of OPA625 to prevent loading in the phase analyzer. Monitor the input and output voltage on the analyzer of the gain phase. Use this circuit to measure the width accumulation of the gain band, and the effect of the opening gain on the frequency of the frequency on the capacitance load.

Noise parameter measurement

The circuit shown in FIG. 66 is used to measure the voltage noise of OPA625. Configure V+, V-and CLOAD as needed.

FIG. 67 The circuit shown in FIG. 67 is used to measure the current noise of OPAX625. Configure V+, V-and CLOAD as needed.

The circuit shown in FIG. 68 is used to measure OPAX625 0.1-Hz to 10 Hz voltage noise. Configure V+, V-and CLOAD as needed.

Detailed instructions

Overview

OPA625 is a kind of fast and stable, high conversion rate, high bandwidth, voltage feedback computing amplifier. The low offset and low offset drift combine the superior dynamic performance and extremely low output impedance, which produces a amplifier suitable for driving 16 -bit SAR ADC and buffering accurate reference voltage in industrial applications. OPAX625 is composed of low noise input level, rotation boost level, and rail circulation output level. Mode deviation The selection function allows OPA625 to configure in high drive mode and low power mode. During the ADC signal collection, use a high drive mode when driving SAR ADC. OPAX625 can also be configured in low power consumption mode, and SAR ADC is converting the collected signal, which saves the power of the entire system. In order to promote the rapid conversion from low power consumption mode to high -driving mode, OPAX625 will not be completely closed in low power consumption mode; on the contrary, the device is still a source of low bandwidth (1 MHz) and loose DC specifications. A amplifier.

Figure Figure

Feature description

SAR ADC drive Rate driving accuracy (16 -bit and 18 -bit) SAR ADC. The combination of low output impedance, low THD, low noise and fast stability time makes OPAX625 an ideal choice to drive SAR ADC input and ADC reference input. The internal conversion voltage circuit increases the conversion rate of the function of the input semaphore.As a result, input from 4V in 280ns u200bu200bstabilizes to 16 -bit level. Low output impedance (1 megs at 1 ω) to ensure the stability of the capacitance load while achieving the minimum overwhelming.

Electrical Overwhelming

Designers often ask the capacity of the transportation amplifier to withstand the power of electrical stress (EOS). These problems are often concentrated on the device input, but may involve the power supply voltage pins and even output pins. Each different pins function has the electrical stability limit determined by the voltage breakdown characteristics of a specific semiconductor manufacturing process and a specific circuit connected to the pin. In addition, internal electrostatic discharge (ESD) is protected in these circuits to prevent an ESD incident that occurs before and in the process of product assembly. It has a good understanding of this basic ESD circuit and its correlation with excessive stress events. For the icons of the ESD circuit contained in OPA625, see Figure 69. The ESD protection circuit includes several current control diode. These diode connect from the input and output pins and return to the internal power cord. The diode is converged at the absorption device or the power supply ESD unit, which is located inside the operation amplifier. The protective circuit aims to maintain a non -activity state during normal circuit operation.

Equipment function mode

OPAX625 has two functional modes: high driver and low power consumption. In low power consumption mode, the static current of OPAX625 is reduced to 270 μA (typical value), which significantly reduces the bandwidth, higher noise and lower output current drivers. OPAX625 transitions from a low power mode to a high -driving mode within 170 NS.

High -drive mode

Put OPAX625 at the high -drive mode by applying low logic levels to the mode pins. The mode pin can be driven by the general input/output (GPIO) of the system controller, or it can be driven by discrete logic doors, or directly connected to the V pins. Don't let the pattern pins float. When a microcontroller GPIO drive mode pins, make sure that GPIO is not in a high impedance state. Putting GPIO in a high impedance state will cause the pattern pins to float basically. It is not recommended to do this. The voltage of the driving mode pin should not be lower than the voltage of the V pins; the allowable voltage of the driving mode pins, see the absolute maximum rated value. Use mode pins to force OPA625 to enter high -drive mode or low -power mode. OPAX625 has a 120MHz gain bandwidth, 2.5-nV/√Hz input reference noise, and only consumes 2mA static current in high drive mode. In addition, OPA625 also has a offset voltage drift of 100 μV (maximum) offset voltage and 1 μV/° C (typical value). This combination of high -precision, high speed and low noise makes the device suitable for SAR ADC (such as SAR ADC's ADS88XX seriesThe input drive of the column), as shown in Figure 72.

Under the high -driving mode, OPAX625 is completely specified as a broadband, low noise, and low distortion precision amplifier. During the signal collection before the conversion cycle starts, when the input of SAR ADC is driven, the high drive mode is the main working mode of OPAX625. Before the end of the collection cycle and before the conversion cycle starts, the OPA625 is placed in the HighDrive mode, which can make OPA625 set to the final value before the conversion. When the ADC is converting the input signal and the signal is no longer collected, the OPA625 is placed in a low -power mode to reduce the system power. The use of low power consumption mode allows OPAX625 power consumption to directly zoom in the sampling rate.

The uniqueness of OPAX625 is that the switch between patterns occurs at 170 nan seconds (typical value). This fast switching is implemented by the architecture of OPAX625 in a low power consumption mode; more information, please refer to the low power consumption mode part.

Low -power mode

Set OPAX625 low -power mode by applying high logic levels on the pattern pin. The mode tube foot can be driven by the GPIO of the system controller, it can also be driven from the discrete logic door, or it can be directly connected to the V+pipe foot. Don't let the pattern pins float. When a microcontroller GPIO drive mode pins, make sure that GPIO is not in a high impedance state. Putting GPIO in a high impedance state will cause the pattern pins to float basically. It is not recommended to do this. Do not allow the mode pins voltage to exceed the voltage of the V+pin; see the absolute maximum rated value of the allowable voltage of the driving mode pin.

Under low power consumption mode, OPAX625 is completely specified as a general operational amplifier. You can control the mode signal so that the OPAX625 is placed in a high -drive mode before the ADC enters the collection stage. This configuration ensures that the voltage on the anti -hybrid filter capacitor is stable to the required accuracy before the collection cycle is completed. When running in this way, the power consumed by OPAX625 is proportional to the throughput of the system. This function is very useful in the power key application and variable throughput data collection system.

The uniqueness of OPAX625 is that the switch between patterns occurs at 170 nan seconds (typical value). This fast switching is implemented by the structure of OPAX625 in a low power consumption mode. Most amplifiers consume very small power in power off or shutdown mode, but they are not working linearly. For example, the output of a typical amplifier can be placed in a high impedance state when it is disabled, which cannot drive any load. Switching from the shutdown state to the linear state needs to charging the internal capacitance and partial pressure point to the level of the linear work range. Generally, this switch may require a few microseconds or longer. This problem is solved with OPAX625. OPAX625 works as a linear operational amplifier in a low power consumption mode, outputTrack the input signal, but the bandwidth is low, the offset and noise are slightly higher. Switch from low power mode to high -drive mode and stabilize to 16 -bit levels in 170 nan seconds (typical values), because this is to keep operations in a linear manner in the duration of each mode. This configuration allows dynamic power extensions while maintaining high throughput.

Application and implementation

Note: The information in the following application chapters is not part of the TI component specification, TI does not guarantee its accuracy or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

OPAX625 is a high -precision, high -speed, voltage feedback computing amplifier. Quickly stable to 16 -bit level, low THD and low noise make OPA625 suitable for driving SAR ADC input and buffering precision voltage reference. OPA625's power supply voltage range from 2.7 to 5.5 volts, and the operating temperature is from -40 degrees Celsius to +125 degrees Celsius. It is suitable for various high-speed industrial applications. The following sections show the application information of OPAX625. For simplicity, the power supply container is not displayed in these figures.

Typical application

Single power supply, 16-bit, 1-MSPS SAR ADC driver

Design requirements

sar ADC, such as ADS8860, uses sampling capacitors at the data converter input terminal. During the signal collection phase, these sample capacitors are connected to the ADC simulation input terminal AINP and AINN through a set of switches. After the collection cycle is over, the internal sampling capacitor is disconnected from the input terminal and connected to the input terminal of the ADC via the second set and switch. During this period, the ADC is undergoing the modulus conversion. Figure 73 illustrates this architecture.

SAR ADC input and sampling capacitors must be driven by OPA625 to 16 -bit level within the ADC collection time. In the example shown in FIG. 72, OPA625 is used to drive ADS8860 with a sampling rate of 1 MSPS.

Detailed design program

The circuit shown in FIG. 72 consists of the SAR ADC driver, low -pass filter, and SAR ADC. The SAR ADC drive circuit is composed of OPA625, and its reversal gain is 1. The filter consists of RFLT and CFLT, connected to the output end of OPA625 and the input terminal of ADS8860. Each selection of each passive element is essential for the best performance from the ADC. CFLT CFLT is used as a charge library to provide the necessary charge to the ADC sampling capacitor. The dynamic load provided by ADC in the filter capacitorThere is a failure on the CFLT. To minimize the size of this fault, select a sufficiently large value for CFLT to maintain the fault amplitude less than 100 mv. Maintaining such a low failure at the amplifier output end can ensure that the amplifier maintains the linear working area and leads to the minimum stable time. Use Formula 6, select 10 NF capacitors for CFLT.

directly connecting the 10NF capacitor directly to the output of OPA625 will reduce the phase of the OPA625 and lead to the problem of stability and stability. In order to correctly drive the 10NF capacitor, the CFLT CFLT CFLT CFLT is used to isolate OPA625. The size of RFLT must be based on multiple constraints. In order to determine the appropriate RFLT value, the effect of the existing effect of the switch resistance (RSW) reaction of the RFLT and the ADC input circuit is considered, and the effect of the output impedance on the stability of the amplifier. In this example, a 4.7Ω resistor was selected. In this design example, FIG. 16 can be used to estimate the appropriate value of RISO. Riso said the total resistance to the CFLT series is equivalent to 2 × RFLT in this example.

Application curve

FIG. 74 illustrates the performance of the circuit shown in FIG. 72.

Single power supply, 16-bit, 1-MSPS, multi-road reuse, SAR ADC driver

In order The bit ADC, the full margin voltage level jump must be stable in the 16 -bit accuracy of the ADC input at the specified minimum collection time (TACQ). This setting puts forward very strict requirements for the driver amplifier in terms of large signal bandwidth, conversion rate and stability time. FIG. 75 illustrates a typical multi -way ADC driver application using OPA625.

Design requirements

In order to optimize the performance of the circuit, this design does not allow any large signal input to input to the input terminal of the drive circuit until A small quiet time period (TQT) at the end of the last conversion. The input step voltage may occur from the beginning of the conversion (convSt rising edge) to the half cycle (0.5 × tCyc). In the worst case, the time limit on the input step allows the minimum stability time (TQT+TACQ) in the required accuracy range. This provides more time for the output of the amplifier so as to change and stabilize within the required accuracy range before the next conversion. Figure 76 illustrates this sequence.

Detailed design program

ADC input driving circuit is mainly composed of two parts: driver amplifier and flywheel RC filter. Amplifier forInput voltage signal adjustment, its low output impedance provides buffer between the signal source and ADC input. The RC filter helps to attenit the sampling charge injection of the switch capacitor input stage of the ADC, which can also be used as an anti -hybrid filter to restrict the broadband noise generated by the front -end circuit. The design of the ADC input drive involves optimizing the circuit bandwidth, which is mainly driven by the following requirements:

RFLTCFLT filter bandwidth should be low to limit the noise ratio of the input ADC input, thereby increasing the signal -to -noise ratio of the system ( SNR).

The entire system bandwidth should be large enough to adapt to the best settings of the input signal input at the ADC input at the beginning of the conversion.

Select CFLT according to Formula 7. CFLT selection as 1NF.

Directly connecting the 1-NF capacitor to the output of OPA625 will reduce the phase of the OPA625 and lead to stability and stability. In order to correctly drive the 1-NF capacitor, the CFLT CFLT CFLT CFLT is used with a series resistor RFLT. The size of RFLT must be based on multiple constraints. In order to determine the appropriate RFLT value, system designers must consider the effects of the effects of the existing effects generated by the switch resistance of the RFLT and ADC input circuits on THD, and the impact of the output impedance on the stability of the amplifier. In this example, select a 12.4Ω resistor. In this design example, Figure 15 can be used to estimate the appropriate value of RISO. Riso said the total resistance to the CFLT series is equivalent to 2 × RFLT in this example.

Application curve

FIG. 77 illustrates the performance of the circuit shown in Figure 75.

Power suggestion

OPAX625's working voltage is 2.7 v to 5.5 v (± 1.35 v to ± 2.75 V)); many specifications are suitable for -40 ° to -40 ° C to+125 ° C. The typical features are given significant parameters related to work voltage or temperature. Place the bypass container near the power pin to reduce the coupling error of noise or high impedance power supply. For more information on the side electric container, see the layout part.

Pay attention to safety

Power voltage greater than 6V will cause permanent damage to the equipment. See the absolute maximum rated part.

Layout

layout guide

In order to obtain the best operating performance of the equipment, please use good PCB layout practice, including:

Use bypass capacitors to reduce the noise of power coupling. Connect low ESR, ceramics, and bypass containers between power pins (V+and V-) and ground layers. As shown in Figure 79Show that the bypass container is placed at the position of the device as close to the device as much as possible, and the 100 NF capacitor is closest to the device. For single -power applications, there is no need to bypass electric container on the V pins.

Circuit simulation and the individual grounding of the digital part are one of the simplest and most effective noise suppression methods. A layer or multi -layer on the multi -layer printing circuit board is usually used for ground layers. The floor helps to distribute heat and reduce the noise of electromagnetic interference. Ensure that the number of numbers and simulation of the ground is separated, and the flowing current flows. For more details, see Sloa089, circuit board layout technology.

In order to reduce parasitic coupling, the input trajectory should be as far away from the power supply or output trajectory as much as possible. If it is impossible to separate them, it is best to be perpendicular to sensitive records instead of parallel with noise recorded channels.

minimize parasitic coupling between+in and out to obtain the best communication performance.

The external components are as close to the device as possible. As shown in Figure 79, keeping RF, CF, and RG near inverter input will minimize parasitic capacitors.

The length of the input record should be as short as possible. Always remember that the input trajectory is the most sensitive part of the circuit.

It is recommended to clean the PCB after assembly to obtain the best performance.

Any precision set circuit may change performance changes due to water entering plastic packaging. After any water -based PCB cleaning process, baking PCB components to remove the water packaging water during the cleaning process. In most cases, it is enough to bake at low temperature and clean at 85 ° C.

layout example