The Intersil ISL54050 device's low on-resistance bidirectional dual SPDT voltage analog switches are designed to operate from a single +1.65V to +4.5V supply. Target applications include battery powered from low rON (0.29Ω) and fast switching speed (tON=40ns, tOFF=20ns). Digital Logic Inputs are compatible with 1.8V logic when using a single +3V supply. For example, mobile phones often face ASIC functionality limitations. The number of analog inputs or GPIO pins can be limited and the digital geometry is not well suited for analog switch performance. This section can be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL54050 is packaged in a small footprint, alleviating board space constraints. The ISL54050 is a committed double single pole double throw (SPDT) consisting of two normally open (NO) and two normally closed (NC) switches. This configuration can be used as a dual 2-to-1 multiplexer. The ISL54050 is pin compatible with the NLAS5223 and NLAS5223L.

feature

Types NLAS5223 and NLAS5223L

On-resistance (rON) -V++=+4.3 volts. 0.29Ω-V+=+3.0V. 0.33Ω-V+=+1.8V. 0.55Ω

rON matching between channels. 0.06Ω

rON flatness over the signal range. 0.03Ω

Single power supply operation. +1.65V to +4.5V

Low Power (PD). <0.45 microwatts

Fast switching action (V+=+4.3V) - t. 40 nanoseconds - time of flight. 20 ns

ESD HBM rating. >8kV

break before make

1.8V logic compatible (+3V power supply)

Low ICC current when VinH is not on the V+ rail

Provide 10 Ld 1.8mmx1.4mmx0.5mmμTQFN

Lead Free (RoHS Compliant)

application

Battery Powered, Handheld and Portable Devices - Cellular/Mobile Phones - Pagers - Notebooks, Notebooks, Palmtops

Portable Test and Measurement

medical equipment

Audio and video switching

Related Literature

Technical Brief TB363 "Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"

Application Note AN557 "Recommended Test Procedures for Analog Switches"

Note: Logic "0"≤0.5V. Logic "1" ≥ 1.4V, 3V power supply.

Absolute Maximum Ratings Thermal Information

V+ is grounded. -0.5V to 5.5V

Input voltage

No, NC, Enter (Note 2). -0.5V to ((V+)+0.5V) output voltage

COMx (Note 2). -0.5V to ((V+)+0.5V)

Continuous current NO, NC or COM. ±300mA

Peak current NO, NC or COM

(pulse 1 ms, 10% duty cycle, max). ±500mA

Electrostatic discharge rating

mannequin. >8kV

machine type. >500V

Charger model. >1.4kV

Thermal Resistance (Typical) θJA (°C/Watt)

10 LdμTQFN package (Note 3). 143

Maximum Junction Temperature (Plastic Packaging). +150 degrees Celsius

Maximum storage temperature range. -65°C to +150°C

Lead-free reflow profile.

operating conditions

temperature range. -40°C to +85°C

NOTE: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to these conditions may compromise product reliability and cause failures not covered by warranty.

notes:

2. Signals on NC, NO, IN or COM that exceed V+ or GND are clamped by internal diodes. Limit forward diode current to maximum rated current.

3. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air. See Technical Bulletin TB379 for details.

Electrical Specifications -4.3V Power Supply Test Conditions: V+=+3.9V to +4.5V, GND=0V, VINH=1.6V, VINL=0.5V (Note 4), unless otherwise specified.

Electrical Specifications - 3V Power Supply Test Conditions: V+=+2.7V to +3.3V, GND=0V, VINH=1.4V, VINL=0.5V (Note 4) unless otherwise specified. (continued)

notes:

4. VIN = Input voltage to perform correct function.

5. The algebraic convention is used in this data sheet, where the most negative value is the minimum value and the most positive value is the maximum value.

6. Flatness refers to the difference between the maximum value and the minimum value of the on-resistance within the specified analog signal range.

7. The rON match between channels is a numerical value calculated by subtracting the channel with the highest maximum rON value from the channel with the lowest maximum rON value, between NC1 and NC2 or between NO1 and NO2.

8. Unless otherwise specified, parameters with minimum and/or maximum limits are 100% tested at +25°C. Temperature limits determined by characterization are also not production testing.

9. Limits determined by characterization, not production tested

Detailed description

The ISL54050 is a bidirectional, dual unipolar/dual analog switch that provides precision switching from 1.65V to 4.5V from a single supply with low voltage supply capability with on-resistance (0.29Ω) and high speed operation (t=40ns, tOFF=20ns). This device is particularly well suited for portable battery powered equipment operating at supply voltage (1.65V), low power consumption (4.5µW max), low leakage current (195nA max) and in a μTQFN package. Ultra-low on-resistance and rON flatness provide very low insertion loss and distortion for applications requiring signal reproduction. External V+ series resistors To improve ESD and latch-up immunity, Intersil recommends V+ on the power supply pins of the ISL54050 IC (see Figure 8). During overvoltage transient events, such as system-level IEC 61000 ESD testing, substrate currents can create structures to open in integrated circuits capable of triggering parasitic thyristors, creating a low-impedance path from V+ to ground. This will cause a large amount of current in the IC that can potentially cause a latched state or permanently damage the IC. The external V+ resistor limits the current stress during this period and has been found to prevent lock-up or many of the destructive damage events of overvoltage transients. The IC has no impact on the switch operation or performance at 100Ω series resistance during normal operation.

Power Supply Sequencing and Overvoltage Protection As with any CMOS device, proper power supply sequencing is to protect the device from excessive input current that can permanently damage the integrated circuit. All I/O pins contain ESD protection diodes from the pin to V+ and ground (see Figure 9). To prevent these diodes from being forward biased, V+ must be applied before any input signal, and the input signal voltage must be kept between V+ and GND. If these conditions cannot be guaranteed, precautions must be taken to prohibit logic pins and signal pins from exceeding the maximum switch ratings. The following two methods can be used to provide additional protection to limit signal pins or logic pins from voltages below ground or above the V+ rail. The logic input can be connected in series with the logic input (see Figure 9). Input currents below the resistance limit cause permanent damage, and sub-microamp input currents produce insignificant voltage drop operations under normal conditions. This method does not work for signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting the Schottky As shown in Figure 9, a diode connected to the signal pin will shunt the fault current to power or ground, thus protecting the switching. These Schottky diodes must be sized to handle the expected fault current.

Power Considerations

The ISL54050 structure is typical of most single-supply CMOS analog switches with two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike the switch when the maximum supply voltage is 4V, the ISL54050 has a 5.5V maximum supply voltage with a 10% tolerance of the 4.3V supply, as well as overshoot and noise peaking. The recommended minimum supply voltage is 1.65V. It is important to note the range of the input signal, switching time, and on-resistance decrease at lower supply voltages. Refer to the "Electrical Specifications" table starting on page 3 and the "Typical Performance Curves" on page 9. V+ and GND also power the internal logic and level shifters. The level shifter converts the input logic level to the switch level to drive the V+ and GND signal terminals of the analog switch gate. This series of switches cannot be used with bipolar switches to operate the power supply because the input switch point becomes negative for this configuration. Logic Level Thresholds This switch family is compatible with 1.8V CMOS (0.5V and 1.4V) over a supply range of 2.7V to 4.5V (see Figure 19). At 2.7V, the VIL level is about 0.53V, still higher than the 1.8V CMOS guaranteed low output maximum level of 0.5V, but with reduced noise margins. The digital input stage is where the digital input voltage is not on one of the supply rails. Power consumption is minimized by driving the fast transition time of digital input signals from GND to V+. The ISL54050 is designed to minimize supply when the digital input voltage is not driven to the supply rail (0V to V+). For example, using 2.85V logic (0V to 2.85V), running on a 4.2V supply, the device draws only 12µA (see Figure 17 VIN=2.85V).

Frequency performance

In a 50Ω system, the -3dB bandwidth of the ISL54050 is 25MHz (see Figure 22). The frequency response is very consistent over a wide V+ range for a variety of analog signal levels. The turn-off switch acts like a capacitor, creating a feedthrough of the signal from the input to the output of the switch by passing higher frequencies with less attenuation. Turning off isolation is the resistance to that feedthrough, while crosstalk means switching from one to the other. Figure 23 details the high-off isolation and crosstalk suppression provided in this section. At 100kHz, in a 50Ω system, the off-isolation is about 62dB, decreasing with frequency by about 20dB per decade. Higher load impedance reduces crosstalk rejection due to isolation and voltage divider action off impedance and load impedance.

Spill Precautions

Reverse ESD protection diodes are internally connected between each analog signal pin and V+ and GND. One of what if any analog signal exceeds V+ or ground. Almost all analog leakage current comes from the ESD diode to V+ or ground. Although the pins on a given signal are the same and thus fairly balanced, they have different reverse biases. Everyone is biased against V+ or GND and analog signals. This means that their leakage varies with the signal. The difference between the two diodes The leakage of the V+ and GND pins constitutes the analog signal path leakage current. Full analog leakage current between each pin and one power supply terminal, not to the other switch terminal. This is why the sides of a given switch can show the same or opposite polarity. There is no connection between the analog signal path and V+ or GND.

Typical performance curve TA=+25°C unless otherwise specified