feature

80 MSPS guaranteed sample rate; 100 dB dual-tone SFDR, 69.3 MHz and 70.3 MHz; 73.1 dB SNR, 70 MHz input; 97 dBc SFDR, 70 MHz input; good linearity; DNL=±0.4 LSB typical; INL =±0.6 LSB typical; 1.2W power consumption; 3.3 V and 5 V supply operation; 2.0V pp differential full-scale input; LVDS output (ANSI-644 compliant); data format selection; output clock available.

application

Multi-carrier multi-mode cellular receiver; antenna array positioning; power amplifier linearization; broadband wireless; radar, infrared imaging; communication instrumentation.

General Instructions

The AD9444 is a 14-bit monolithic sampling analog-to-digital converter (ADC) with on-chip, track-and-hold circuitry optimized for power, small size, and ease of use. The product operates at slew rates up to 80 MSPS and is optimized for multi-carrier, multi-mode receivers such as those found in cellular infrastructure equipment.

The ADC requires 3.3v and 5.0v power supplies and a low voltage differential input clock for full performance operation. Many applications do not require external references or driver components. The data output is LVDS compatible (ANSI644) or CMOS compatible and includes means to reduce the total current required for short tracking distances.

Optional functions allow users to implement various optional operating conditions, including data format selection and output data mode.

The AD9444 is available in a 100-lead surface mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (-40°C to +85°C).

Product Highlights

1. High performance: Excellent SFDR performance for multi-carrier, multi-mode 3G and 4G cellular base station receivers.

2. Ease of use: On-chip reference and track hold. The output clock simplifies data capture.

3. Packaged in lead-free 100 lead TQFP/EP.

4. The clock DCS maintains the overall performance of the ADC over a wide range of clock pulse widths.

5. The OR (Out of Range) output indicates when the signal is outside the selected input range.

Switch Specifications

AVDD1=3.3V, AVDD2=5.0V, DRVDD=3.3V unless otherwise noted.

1. Enable the duty cycle stabilizer (DCS).

2. Measure the output propagation delay from 50% transition of clock to 50% transition of data under 5 pF load.

3. LVDS RTERM=100 Euro. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

Absolute Maximum Ratings

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Thermal resistance

The heat sink of the AD9444 package must be soldered to ground.

Typical θ=19.8°C/W for a multilayer board in still air (heat sink soldering).

Typical θ=8.3°C/W for multilayer boards in still air (heat sink soldering).

A typical θ=2°C/W (connected to an exposed heat sink) represents the thermal resistance of the path through the heat sink.

The airflow increases heat dissipation and effectively reduces θ. Additionally, more metal is in direct contact with package leads, from metal traces, through vias, ground and power planes, reducing θ. Requires that the exposed heat sink be soldered to the ground plane.

canonical definition

Analog bandwidth (full power bandwidth)

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3db.

Aperture Delay (tA)

Delay between the 50% point of the rising edge of the clock and the instant the analog input is sampled.

Aperture uncertainty (jitter, tJ)

Sample-to-sample variation of aperture delay.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that a clock pulse remains in a logic 1 state to achieve rated performance. Pulse width low is the minimum time a clock pulse should remain low. These specifications define acceptable clock duty cycles for a given clock rate.

Differential Nonlinearity (DNL, no missing code)

An ideal ADC shows code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes at 14-bit resolution means that all 16384 codes must be present in all working ranges.

Effective Number of Bits (ENOB)

At a given input frequency, the effective number of bits for a sine wave input can be calculated directly from its measured SINAD using the following formula

gain error

The first code transition should occur at 1/2 LSB of the analog value above negative full scale. The last conversion should occur at the analog value 1.5 LSB below positive full scale. Gain error is the deviation between the actual difference between the first and last transcoding and the ideal difference between the first and last transcoding.

Integral Nonlinearity (INL)

The deviation of each individual code between the lines drawn from negative full scale to positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as 1.5 LSBs past the last code transition. Measure the deviation from the middle of each specific code to a true straight line.

Maximum conversion rate

The clock frequency at which the parametric test is performed.

Minimum conversion rate

The signal-to-noise ratio of the lowest analog signal frequency is below the guaranteed limit by no more than 3 dB of the clock rate.

offset error

When the analog value is less than VIN+=VIN-, a large carry conversion should occur. Offset error is defined as the deviation of the actual transition point from this point.

Out of range recovery time

The time required for the ADC to regain the analog input after a transition from 10% above positive full scale to 10% above negative full scale or from 10% below negative full scale to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the rising edge of the clock and the time when all bits are within valid logic levels.

power supply rejection ratio

A full-scale change from the value where the supply is at the minimum limit to the value where the supply is at the maximum limit.

Signal to Noise and Distortion (SINAD)

rms The ratio of the input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics, but excluding DC.

signal to noise ratio

The sum of the rms input signal amplitude and all other spectral components below the Nyquist frequency, excluding the first six harmonics and DC.

Spurious Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral components. Peak spurious components may or may not be harmonics. Can be reported in dBc (that is, decreases as signal level decreases) or dBFS (always relative to converter full scale).

temperature drift

The temperature drift of the offset error and gain error specifies the maximum change from the initial (25°C) value to the TMIN or TMAX value.

Total Harmonic Distortion (THD)

rms The ratio of the input signal amplitude to the rms value of the sum of the first six harmonic components.

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be IMD products.

Equivalent Circuit

Typical performance characteristics

AVDD1=3.3 V, AVDD2=5.0 V, DRVDD=3.3 V, sample rate=80 MSPS, LVDS mode, DCS enabled, T=25°C, 2 V pp differential input, AIN=-0.5 dBFS, internal trim reference (standard called VREF=1.0 V) unless otherwise noted.

theory of operation

The AD9444 architecture is optimized for high speed and ease of use. The analog input drives an integrated, high-bandwidth track-and-hold circuit that samples the signal prior to quantization by the 14-bit pipelined ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS or LVPECL levels. The digital output logic levels are user selectable as standard 3V CMOS or LVDS (ANSI-644 compatible) via the output mode pins.

Overview of Analog Inputs and References

The AD9444 has a built-in stable and accurate 0.5V voltage reference. The input range can be adjusted by changing the reference voltage applied to the AD9444 using the internal reference voltage or an externally applied reference voltage. The input range of the ADC tracks linear changes in the reference voltage. The following sections describe the various reference modes.

Internal reference connection

The comparator in the AD9444 senses the potential at the sense pin and configures the reference to four possible states, as shown in Table 9. If the sensor is grounded, the reference amplifier switch is connected to an internal resistor divider (see Figure 40), setting VREF to ~1V. Connecting the sensor pin to VREF switches the reference amplifier output to the sensor pin, completing the loop and providing a ~0.5V reference output. As shown in Figure 41, if a resistive divider is connected, the switch is again set to the sense pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input range. The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

Internal reference fine-tuning

The internal reference voltage is adjusted during production test to adjust the gain (analog input voltage range) of the AD9444. Therefore, users who provide an external voltage reference to the AD9444 have little advantage. Gain trimming is performed with the AD9444's input range set to 2V pp nominal (sensor connected to AGND). Because of this trimming, and since the 2v pp analog input range provides maximum ac performance, there is little benefit to using an analog input range less than 2vp-p. The user should note that the differential nonlinearity of the ADC varies with the reference voltage. Using <2v pp configurations may suffer from missing codes, thus degrading noise and distortion performance.

Xref Operations

Adjust the internal reference of the AD9444 to improve the gain accuracy of the ADC. The external reference temperature may be more stable, but the gain of the ADC is unlikely to improve. Figure 36 shows the typical drift characteristics of the internal reference in 1V and 0.5V modes.

When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 7kΩ load. Internal buffers still generate positive and negative full-scale references (REFT and REFB) for the ADC core. The input range is always twice the value of the reference voltage; therefore, the maximum value of the external reference voltage must be limited to 1V.

analog input

Like most new high-speed, high-dynamic-range ADCs, the analog inputs to the AD9444 are differential. Differential inputs improve on-chip performance as the signal is processed through attenuation and gain stages. Most of the improvements are due to the differential analog stage's high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of spurious signals such as ground noise and power noise. Second, they are good at rejecting common-mode signals such as LO feedthrough. The specified noise and distortion of the AD9444 cannot be achieved with a single-ended analog input, so such a configuration is discouraged. Please contact ADI for advice on other 14-bit ADCs that support single-ended analog input configurations.

Using a 1V reference voltage (nominal, see Internal Reference Trim section), the differential input range of the AD9444 analog inputs is nominally 2V pp or 1V pp (VIN+ or VIN-) per input.

The AD9444 analog input voltage range is offset 3.5 V from ground. Each analog input is connected to the input of the 3.5 V bias voltage and differential buffer through 1 kΩ resistors. An internal biasing network at the input biases the buffer appropriately for maximum linearity and range (see the Equivalent Circuits section). Therefore, the analog source driving the AD9444 should be AC coupled to the input pins. The recommended way to drive the analog inputs of the AD9444 is to use an RF transformer to convert a single-ended signal to a differential signal (see Figure 44). A series resistor between the transformer output and the AD9444 analog input helps isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. In matching the impedance to the transformer input, the series resistor as well as the 1 kΩ resistor connected to the internal 3.5 V bias must be considered. For example, if R is set to 51Ω, R is set to 33Ω, and a 1:1 impedance ratio transformer, the input will match a 50Ω source and a 10.0 dBm full-scale driver. As shown in the evaluation board schematics (see Figures 47 and 59), a 50Ω impedance match can also be incorporated into the secondary side of the transformer.

Clock Input Considerations

Any high speed ADC is very sensitive to the quality of the sample clock provided by the user. The track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Therefore, great care is taken when designing the clock input to the AD9444, and the user is advised to carefully consider the clock source.

Typical high speed ADCs use two clock edges to generate various internal timing signals and, as a result, may be sensitive to the clock duty cycle. Typically, a 5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics. The AD9444 includes a clock duty cycle stabilizer (DC) that retimes non-sampling edges to provide an internal clock signal with a nominal 50% duty cycle. As shown in Figure 32, with DCS enabled, the noise and distortion performance is nearly flat at 30% to 70% duty cycle. The DCS circuit latches on to the rising edge of CLK+ and optimizes the timing internally. This allows a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still the most important issue and is not reduced by the internal stabilization circuit. The duty cycle control loop is generally not suitable for clock frequencies less than 30 MHz. This loop has a time constant associated with it that needs to be taken into account in applications where the clock rate can vary dynamically, which requires 1.5 microseconds after the dynamic clock frequency increase (or decrease) before the DCS loop relocks to the input signal to 5 microseconds wait time. During this time period, the loop is not locked, the DCS loop is bypassed, and the internal device timing depends on the duty cycle of the input clock signal. In this application, the duty cycle stabilizer can be appropriately disabled. In all other applications, it is recommended to enable the DCS circuit to maximize AC performance.

The DCS circuit is controlled by the DCS mode pin; a CMOS logic low (AGND) on DCS mode enables the duty cycle stabilizer, and a logic high (AVDD1=3.3v) disables the controller.

The AD9444 input sampling clock signal must be a high quality, very low phase noise source to prevent performance degradation. Maintaining 14-bit accuracy is an advantage of encoding clock phase noise. When using a high jitter clock source, the SNR performance can easily degrade by 3db to 4db when using a 70mhz analog input signal. (See AN-501, Aperture Uncertainty and ADC System Performance, for complete details.) For optimum performance, the AD9444 must be clocked differentially. The sample clock input is internally biased to ~2.2V, and the input signal is typically AC coupled to the CLK+ and CLK- pins through a transformer or capacitor. Figure 44 shows a preferred method of timing the AD9444. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. Back-to-back Schottky diodes on the secondary side of the transformer limit the clock skew of the AD9444 to approximately 0.8V pp differential. This helps prevent large voltage fluctuations of the clock from passing through other parts of the AD9444 and limits the noise presented to the sampling clock input.

Another option, if a low-jitter clock is available, is to AC-couple the differential ECL/PECL signal to the encode input pins, as shown in Figure 46.

Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given input frequency (f) and rms amplitude, the SNR attenuation due to aperture jitter (t) alone can be calculated using the following equation.

In the equation, rms aperture jitter represents the rms of all jitter sources, including clock inputs, analog input signals, and ADC aperture jitter specifications. If the undersampling application is particularly sensitive to jitter, see Figure 46.

The clock input should be treated as an analog signal when aperture jitter may affect the dynamic range of the AD9444. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

Power Factor

Care should be taken when choosing a power source. A linear DC power supply is strongly recommended. Switching power supplies tend to have radiating components that can be received by the AD9444. Each power supply pin should be separated from the package as much as possible using 0.1µF chip capacitors.

The AD9444 has separate digital and analog power supply pins. The analog supplies are denoted as AVDD1 (3.3v) and AVDD2 (5v), and the digital supply pins are denoted as DRVDD. Although the AVDD1 and DRVDD supplies can be tied together, best performance is obtained when the supplies are separated. This is because fast digital output fluctuations can couple switch currents back into the analog supply. Note that AVDD1 and AVDD2 must remain within 5% of the specified voltage.

The DRVDD supply of the AD9444 is a dedicated supply for the digital outputs in LVD or CMOS output mode. When in LVDS mode, DRVDD should be set to 3.3v. In CMOS mode, the DRVDD supply can be connected from 2.5v to 3.6v for compatibility with receive logic.

digital output

LVDS mode

The on-chip off-chip driver can be configured to provide LVDS-compatible output levels via pin 5 (output mode). The LVDS output is available when the output mode is CMOS logic high (or AVDD1 for convenience) and the 3.74 kΩR resistor is placed at pin 7 (LVDSBIAS) to ground. Dynamic performance, including SFDR and SNR, is maximized when the AD9444 is used in LVDS mode, and designers are encouraged to take advantage of this mode. AD9444 outputs include complementary LVDS outputs per data bit (DX+/DX-), overrange outputs (or +/or -), and output data clock outputs (DCO+/DCO-). The R resistor current is rated on the chip, setting the output current to 3.5 mA (11 x IR) per output. A 100Ω differential termination resistor placed at the input of the LVDS receiver results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that are LVDS capable and have excellent switching performance in noisy environments. It is recommended to use a point-to-point network topology with 100Ω termination resistors as close as possible to the receiver. It is recommended to keep track lengths between 1" and 2" and keep differential output track lengths as equal as possible.

CMOS mode

In applications that can tolerate a slight degradation in dynamic performance, the AD9444 output driver can be configured to interface with a 2.5v or 3.3v logic family by matching DRVDD to the digital supply of the interface logic. The CMOS output is available when the output mode is CMOS logic low (or AGND for convenience). In this mode, the output data bits are single-ended CMOS, DX, and so are the overrange outputs. The output clock is provided as differential CMOS signals DCO+/DCO-. A lower supply voltage is recommended to avoid coupling switching transients back to the sensitive analog parts of the ADC. Capacitive loading on the CMOS outputs should be minimized, and each output should be connected to a single gate through a series resistor (220Ω) to minimize switching transients caused by capacitive loading.

opportunity

The AD9444 provides a latched data output with a pipeline delay of 12 clock cycles. Data output is available one propagation delay (t) after the rising edge of CLK+. See Figure 2 and Figure 3 for detailed timing diagrams.

Operation mode selection

Data format selection

The Data Format Select (DFS) pin of the AD9444 determines the encoding format of the output data. This pin is 3.3V CMOS compatible, logic high (or AVDD1, 3.3V) selects two's complement, while DFS logic low (AGND) selects offset binary format. Table 10 summarizes the output encodings.

output mode selection

Output mode pins control logic compatibility, as well as pins for digital outputs. This pin is a CMOS compatible input. With output mode = 0 (AGND), the AD9444 outputs are CMOS compatible and the pin assignments for the device are defined in Table 8. When output mode = 1 (AVDD1, 3.3v), the AD9444 output is LVDS compatible, and the pin assignments of the device are shown in Table 7.

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS mode pin; a CMOS logic low (AGND) on DCS mode enables the DCS, while a logic high (AVDD1, 3.3v) disables the controller.

Evaluation Committee

An evaluation board is available to configure the AD9444 in CMOS or LVDS mode. Each represents a recommended configuration for using the device over a wide range of sample rates and analog input frequencies. These evaluation boards provide all the support circuitry required to operate the ADC in various modes and configurations. The complete schematic and layout diagrams follow and demonstrate proper wiring and grounding techniques that should be applied at the system level.

A signal source with very low phase noise is important to use (<1ps rms jitter) to achieve the final performance of the converter. Appropriate filtering of the input signal to remove harmonics and reduce the overall noise at the input is also a necessary condition to achieve the specified noise performance.

The EV kit comes with an AC to 6V DC power supply. The evaluation board includes low dropout voltage regulators to generate the various DC power supplies required by the AD9444 and its supporting circuitry. Provide a separate power supply to isolate the device under test from supporting circuits. Each input configuration can be selected by the proper connection of various jumpers (see Figures 47 to 50 and 59 to 61).

Both the LVDS and CMOS versions of the evaluation board are compatible with the High Speed ADC FIFO Evaluation Kit (part number HSC-ADC-EVALA-SC). The kit includes a high-speed data acquisition board that provides a hardware solution for acquiring up to 32k high-speed ADC output data (user upgradeable to 256K samples) in a FIFO memory chip. The provided software allows the user to download the captured data to a PC via the USB port. The software also includes behavioral models for the AD9444 and many other high-speed ADCs.

Behavioral modeling of the AD9444 is also available on /ADIsimADC. Adisimado™ software supports virtual ADC evaluation using ADI's proprietary behavioral modeling technology. This allows a quick comparison of the AD9444 with other high speed ADCs with or without a hardware evaluation board.

The AD9444 LVDS Evaluation Board includes an on-board converter from LVDS to CMOS, but the user can choose to remove the converter and termination for direct access to the LVDS output.

The CMOS evaluation board includes buffers for the AD9444's output data and DCO output clock.

Dimensions