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DESCRIPTION ISO1540 and ISO1541 devices are low-power, 1-isolated bidirectional, I2C compatible, bidirectional isolators compatible with the I2C communication interface. These devices have their logic inputs and output buffers that support up to 1 MHz of operation, separated by TI's capacitive isolation technology for the 3-V to 5.5-V power supply range using a silicon dioxide (silicon dioxide) barrier. 3.5 mA Open-Drain Outputs on Sides 1 and 35 - When used with isolated power supplies, these mA devices block high voltage, isolated ground and 2-side sink current capability prevents noise currents from entering local ground –40°C to +125 °C operating temperature, interfere with or damage sensitive circuits. ±50 kV/µs transient immunity (typ) This isolation technology provides functional, 4 kV HBM ESD protection on all pins; performance, size and power consumption compared to optocoupler, 8 kV bus pin advantage. This safety and regulatory approval ISO154 and ISO1541 device enables an isolated I2C interface to be implemented within –4242-VPK isolation according to DIN V VDE V 0884-10 small form factor (VDE V 0884-10): December 2006 – 2500-V According to UL 1577, ISO154 has two isolated bidirectional channels RMS isolated for 1 minute for clock and data lines, while ISO1541 has –CSA Parts Acceptance Notice 5A, IEC bidirectional data and unidirectional clock channels. 60950-1 and IEC 61010-1 terminal equipment ISO1541 is suitable for standard single main, while ISO1540 is ideal for multi--CQC basic insulation in accordance with GB4943.1-2011 main application. Isolated bidirectional communication is achieved by offsetting the I-side 1 low-level output voltage value greater than the 2C bus. Therefore, the SMBus and PMBus interfaces prevent internal logic latching that would otherwise open the drain network using standard digital isolators.

Motor Control System Equipment Information (1)

Battery Management Part Number Package Body Dimensions (nominal) I2C Horizontal Displacement

Electrical Characteristics

exceed recommended operating conditions unless otherwise specified

(1) This parameter does not apply to the ISO1541 SCL1 line because it is unidirectional.

(2) ΔVOIT1 = Volume 1 – Volume 1. This represents the threshold at which the minimum difference between the low-level output voltage and the high-level input voltage is used to prevent a permanent latched state that may exist in bidirectional communication.

(3) A VCC voltage on either side below the minimum value will ensure the device is locked. Both VCC voltages are greater than the maximum value to prevent the device from locking up.

The I2C bus is widely used due to its simplicity of use. The bus consists of two wires forming a communication bus that supports bidirectional data transfer between master and slave. The master or processor controls the bus, especially the serial clock (SCL) line. data on the master and slave via the serial data (SDA) line. This data can be transmitted at four speeds: Standard Mode (0 to 100kbps), Fast Mode (0 to 400 kbps), Fast Mode Enhanced (0 to 1 Mbps), and High Speed Mode (0 to 3.4 Mbps). The most common speeds are standard and express modes. The I2C bus operates in bidirectional half-duplex mode, whereas standard digital isolators are unidirectional devices. In order to efficiently utilize one technology in favor of another, external circuitry is required to split the bidirectional bus into two unidirectional signal paths without introducing effective propagation delays. The logic input and output buffers of these devices are separated by TI's capacitive isolation technology using a silicon dioxide (silicon dioxide) barrier. When used with isolated power supplies, these devices block high voltages, isolate the ground, and prevent noise currents from entering the local ground, interfering with or damaging sensitive circuits.

ISO equipment makes a complete isolation I? The C interface enables the following features in a small form factor:

1) All pins on each side of the barrier are connected together to form a 2-terminal device.

(2) Measured from input pin to ground.

Safety limits are designed to prevent potential damage to the isolation barrier if an input or output circuit fails. Failure of an I/O can cause low resistance to ground or power and, in the absence of current limiting, can dissipate enough power to overheat the die and damage the isolation barrier, potentially causing secondary system failure.

The safety limit constraint is the absolute maximum junction temperature rating specified in Absolute Maximum. The power dissipation of the device installed in the application and the thermal impedance of the junction to air hardware determine the junction temperature. It is assumed that the junction-to-air thermal resistance information is that of a lead surface mount packaged device mounted on a high-K test board. Power is the recommended maximum input voltage multiplied by the current. Junction temperature is the ambient temperature plus power times the thermal resistance of the junction to air.

The Inter-Integrated Circuit (I2C) bus is a single-ended, multi-master, 2-wire bus for an efficient inter-IC half-duplex communication mode. I2C uses open-drain technology and requires two lines to connect serial data (SDA) and serial clock (SCL) to VDD through resistors (see Figure 25). Treating the line ground as a logical zero floating point operation is a logical operation when grounding the line. This is used as the channel access method. Transitions when SCL is low and SCL high represent start and stop conditions. Typical supply voltages are 3.3 V and 5 V, although higher or lower voltage systems are permitted.

I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112 nodes can communicate on the same bus. In practice, however, the number of nodes is specified, and the total bus capacitance is 400 pF, limiting the communication distance to a few meters. The specified signaling rates for ISO1540 and ISO1541 are 100kbps (standard mode), 400kbps (fast mode), 1 Mbps (fast mode enhanced). The bus has two roles for nodes: master and slave. The master node issues clocks, slave node addresses, and starts and ends data transactions. The slave node receives the clock and address and responds to requests there. Figure 26 shows a typical data transfer between a master and a slave.

The master initiates a transaction by creating a start condition, followed by the 7-bit address of the slave it wishes to communicate with. It is followed by a read/write bit indicating whether the master wishes to write (0) or read from (1) the slave. The master then releases the SDA line to allow the slave to acknowledge receipt of the data. The slave responds to the clock pulse on SCL by pulling SDA low for the entire high time on the 9th with an acknowledge bit (ACK), after which the master continues to be in transmit or receive mode (sent according to the R/W bit) while the slave continues to be in Complementary mode (receive or transmit, respectively). The address and the most significant bit (MSB) of the 8-bit data byte are sent first. A high-to-low transition of SDA when the start bit is high from SCL. A stop condition is created by a low-to-high transition of SDA while SCL is high. If the master writes to the slave, it repeatedly sends a byte, and the slave sends an ACK bit. In this case the master device is in master transmit mode and the slave device is in slave receive mode. If the master reads data from the slave, it repeatedly receives a byte from the slave, acknowledging (ACK) receipt of every byte except the last (see Figure 27). In this case, the master is in master receive mode and the slave is in slave transmit mode. The master ends the transfer with a stop bit, or can send another start bit to keep bus control for further transfers.

When writing to a slave, the master mainly works in transmit mode and only receives acknowledgments from the slave server. When the slave reads data, the master starts in the transmit mode, and then changes to the receive mode to read the slave request (R/W bit = 1). The slave continues to be in complementary mode until a transaction. Note that the host ends the read sequence by not acknowledging (NACK) the last byte received. This process resets the slave state machine and allows the master to send a stop command.

To isolate the bidirectional signal path (SDA or SCL), the ISO1540 internally splits the bidirectional line into two unidirectional signal lines, each isolated by a single-channel digital isolator. Each channel output uses an open drain to comply with I2C's open drain technology. Side 1 of the ISO154 connects to low capacitance I2C nodes, while Side 2 is designed to connect to fully loaded I2C bus capacitances up to 400 pF.

At first glance, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up. However, by implementing an output buffer (B) whose output low is raised by a diode, breaking the loop down to approximately 0.75 V, the input buffer (C) is driven by a comparator with a specified hysteresis device composition. The upper and lower input thresholds of this comparator then distinguish the appropriate low of 0.4V for the maximum value directly driven by SDA1 and the buffered output low of B. Figure 29 shows a heavy-duty bus with the I2C isolator ISO1540 at SDA1 and SDA2.

When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. It yields low VOL1=0.75v buffered output, low enough for Schmitt trigger input with minimum input low voltage VIL=0.9V, 3V supply level. Once SDA2 is released, its voltage potential increases in the direction of VCC2 with the time constant formed by RPU2 and CBU. After the receive delay, SDA1 is released and rises towards VCC1 with a time constant of RPU1 × CNOOC. Due to the significantly reduced time constant, SDA1 may reach the VCC1VCC2 potential before SDA2 arrives.

When the main driver SDA1 is low, SDA2 follows after a certain delay in the transfer direction. When SDA2 turns low it also causes the output of buffer B to go low, but at a higher 0.75 V level. It cannot be observed that this level is immediately covered by the lower level of the host. However, when the master releases SDA1, its voltage potential rises, and it must first release the threshold of SDA2 through the upper input comparator VIHT1. Then SDA1 is further increased until it reaches the output level of buffer VOL1 = 0.75 V, held by the receive path. After comparator C is turned high, release SDA2 after the transmission direction delay. It takes another receive delay until B's output goes high and fully releases SDA1 to move towards the VCC1 potential.

10.2 Typical applications

In Figure 30, the ultra-low-power microcontroller MSP430G2132 controls the configured I2C data flow to simulate the input and output data and conversion results. Low-power data converters build analog interfaces with sensors and actuators. ISO1541 provides the necessary isolation between different grounds for the system controller, remote sensor and actuator circuits to prevent ground loop currents that might otherwise falsify the acquired data. The entire circuit is powered by a 3.3 volt supply. The low power push-pull converter SN6501 drives a center-tapped transformer whose output is rectified and linearly regulated to provide a stable 5-volt power converter for data

The recommended supply voltages (VCC1 and VCC2) must be between 3 V and 5.5 V. It is recommended that decoupling requires 0.1-µF capacitors between VCC1 to GND1 and VCC2 to GND2 to protect against supply voltage transients and ensure reliable operation at all data rates. The 0.1-µF supply capacitor must be as close as possible to the supply pins.

The recommended capacitor location must be a maximum of 2mm away from the input and output power pins (VCC1 and VCC2). The maximum allowable load on the input SDA1 and SCL1 lines is ≤40pf, and the maximum allowable load on the output SDA2 and SCL2 lines is ≤400 lbf. The minimum pull-up resistors on the input SDA1 and SCL1 lines of VCC1 must be chosen such that the input current consumption is less than or equal to 3.5 mA. The minimum pull-up resistor must be selected on the input SDA2 and SCL2 lines of VCC2. The output current is less than or equal to 35ma. The maximum pull-up resistors on the input lines (SDA1 and SCL1) to VCC1 and the output lines (SDA1 and SCL1) to VCC2 will depend on the load and rise time requirements on their respective lines.

To ensure reliable operation at all data rates and supply voltages, TI recommends using the input and output power pins (VCC1 and VCC2). Capacitors should be placed as close as possible to the power supply pins. If only one primary supply is available in the application, it can be generated for the secondary with the help of a transformer driver such as TI's SN6501. For this application, see the SN6501 data sheet (SLLSEA0) for detailed power supply design and transformer selection recommendations.

A minimum of four layers are required to complete a low EMI PCB design (see Figure 34). The stackup should be in the following order (top to bottom): high-speed signal layer, ground plane, power plane, and low frequency

signal layer. Routing high-speed traces on the top layer avoids the use of vias (and the introduction of vias inductance) and allows for clean interconnection between the isolator and the transmitter and receiver circuits of the data link. Placing a solid ground plane next to the high-speed signal layers provides an excellent low-inductance path for the return line to interconnect the transmission lines. Placing the power plane next to the ground plane creates an additional high frequency bypass capacitance of approximately 100 pF/in2. • Routing slower speed control signals on the bottom layer to make these signal chains more flexible and usually have enough margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is required, add a second power or ground plane system to the stack to keep it symmetrical. This keeps the stack mechanically stable and prevents it from warping. There are also power and ground planes for each power system that can be put together, thereby increasing the high frequency bypass capacitance significantly.

For digital boards operating below 150 Mbps (or rise and fall times greater than 1 ns), trace lengths up to 10 inches use standard FR-4 epoxy glass as the PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, due to its low dielectric loss at high frequency, low hygroscopicity, high strength and stiffness, and self-extinguishing combustion characteristics