feature

10-bit and 12-bit ADCs with fast conversion times: 2 μs typical; 8 single-ended analog input channels; specified VDD from 2.7 V to 5.5 V; low power consumption; fast throughput: up to 188 kSPS; sequencer operation; Auto Loop Mode; I2C® Compatible Serial Interface Supports Standard, Fast and High Speed Modes; Out of Range Indicator/Alarm Function; Pin-Selectable Addressing via AS; Shutdown Mode: 1µA Max; Temperature Range: -40° C to +85°C; 20-lead TSSOP package; see thd or 2- and 4-channel equivalents, respectively.

General Instructions

The AD7997 /AD7998 are 8-channel, 10- and 12-bit, low power, successive approximation ADCs with an IC-compatible interface. These parts operate from a single 2.7V to 5.5V supply with a 2 microsecond transition time. These parts include an 8-channel multiplexer and track-and-hold amplifier that can handle input frequencies up to 11MHz.

The AD7997/AD7998 provide a 2-wire serial interface compatible with the IC interface. There are two versions of each part, AD7997-0/AD7998-0 and AD7997-1/AD7998-1, each allowing at least two different IC addresses. The IC interface on the AD7997-0/AD7998-0 supports standard and fast IC interface modes. The IC interface on the AD7997-1/AD7998-1 supports standard, fast, and high-speed IC interface modes.

The AD7997/AD7998 are normally kept off when not converting and powered up only when converting. This conversion process can be controlled using the CONVST pin, either by command mode (converting between IC write operations) or by software-controlled selection of automatic conversion interval mode.

The AD7997/AD7998 require an external reference, which is applied to the reference pin and can range from 1.2 V to V. This allows the maximum dynamic input range of the ADC.

The on-chip limit registers can be programmed to the high and low limits of the conversion result. When the conversion result violates the programmed high or low limits, an open circuit, out of range indication output (alert) becomes active. This output can be used as an interrupt.

Product Highlights

1, 2 microsecond conversion time, low power consumption.

2. A serial interface compatible with integrated circuits with pin-selectable addresses. Two AD7997/AD7998 versions allow five AD7997/AD7998 devices to be connected to the same serial bus.

3. These components feature automatic shutdown rather than conversion for maximum electrical efficiency. In shutdown mode at 3V, the current consumption is a maximum of 1µA.

4. The reference can be driven to the power supply.

5. The software's out-of-range indicator can be disabled or enabled.

6. One-time and automatic conversion rates.

7. The registers store the minimum and maximum conversion results.

Absolute Maximum Ratings

T=25°C unless otherwise noted.

May cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions listed in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

the term

Signal-to-noise ratio and distortion ratio The signal-to-noise ratio and distortion ratio measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the sum of all non-fundamental signals up to half the sampling frequency (f/2), excluding DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio and distortion ratio of an ideal N-bit sine wave converter are given:

So SINAD is 61.96 dB for a 10-bit converter and 74 dB for a 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the harmonics to the fundamental. For the AD7997/AD7998, it is defined as:

where V is the rms amplitude of the fundamental and V1, V2, V3... and V5 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

The ratio of the rms value of the next largest component in the ADC output spectrum (excluding DC) to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonic is buried in the noise floor, it is the noise peak.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3, etc. Intermodulation distortion terms are those where m and n are not equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), while third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7997/AD7998 are tested using the CCIF standard using two input frequencies near the top of the input bandwidth. In this case, the second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated, as in the THD specification, as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the rationale, expressed in dB.

Isolation between channels

A method of measuring the level of crosstalk between channels by applying a full-scale sine wave signal to unselected input channels and determining how much the 108 Hz signal is attenuated in the selected channel. Then, the sine wave signal applied to the unselected channel was varied from 1khz to 2mhz, each time determining the degree of attenuation of the 108hz signal in the selected channel. This number represents the worst-case scenario for all channels.

Aperture delay

The measurement interval between the leading edge of the sampling clock and the ADC sampling point.

Aperture jitter

This is the sample-to-sample variation at the effective time point for sampling.

full power bandwidth

For full-scale input, the reconstructed fundamental amplitude is reduced by 0.1db or 3db of the input frequency.

power supply rejection ratio

At full-scale frequency f, the ratio of the power output by the ADC to the power of a 200mv pp sine wave applied to the ADC VDD supply at frequency fS:

where Pf is the power at frequency f in the ADC output; Pf is the power at frequency f coupled to the ADC V supply.

Integral nonlinearity

Maximum deviation of a straight line through the endpoints of the ADC transfer function. The endpoints are zero scale, the point 1lsb below the first code transition, and full scale, the point 1lsb above the last code transition.

Differential nonlinearity

The difference between the measured value and the ideal 1 LSB between any two adjacent codes in the ADC changes.

offset error

The first code transitions (00…000) to (00…001) the deviation from the ideal (i.e. AGND+1lsb).

offset error matching

The difference in offset error between any two channels.

gain error

The deviation of the last code transition (111…110) to (111…111) from the ideal (ie REF-1 LSB) after the offset error has been adjusted.

Gain Error Matching

The difference in gain error between any two channels.

Typical performance characteristics

circuit information

The AD7997/AD7998 are low power, 10- and 12-bit, single-supply, 8-channel A/D converters. These parts can operate from 2.7 volts to 5.5 volts.

The AD7997/AD7998 feature an 8-channel multiplexer, an on-chip track and hold, an A/D converter, an on-chip oscillator, internal data registers, and an IC-compatible serial interface, all packaged in a single 20-lead TSSOP. This package has considerable space saving advantages over other solutions. The AD7997/AD7998 require a range of 1.2 volts to 5 volts.

The AD7997/AD7998 typically remain powered down when not converting. When power is used for the first time, the components are powered off. Power up is initiated before the conversion, and the device returns to the off state after the conversion is complete. Conversions can be performed on the AD7997/AD7998 by pulsing the CONVST signal in the AD7997/AD7998 by pulsing the CONVST signal using the automatic cycle interval mode or the command mode (see the Operational Modes section) which wakes up and converts during the write address function. After the conversion is complete, the AD7997/AD7998 enter shutdown mode again. This automatic shutdown feature allows power saving between transitions. This means that any read and write operations on the IC interface can happen when the device is powered off.

Inverter operation

The AD7997/AD7998 are successive approximation analog-to-digital converters based on capacitive DACs. Figure 18 and Figure 19 show simplified schematics of the ADC during the acquisition and conversion phases, respectively. Figure 18 shows the acquisition phase. SW2 is closed, SW1 is in position A, the comparator remains in balance, and the sampling capacitor takes the signal on VIN.

At the start of the conversion, SW2 opens and SW1 moves to position B, causing the comparator to become unbalanced, as shown in Figure 19. Once the conversion starts, the input is disconnected. Control logic and capacitive DACs are used to add and subtract a fixed amount of charge from the sampling capacitor to bring the comparator back into equilibrium. The conversion is complete when the comparator is rebalanced. The control logic generates the ADC output codes. Figure 20 shows the ADC transfer characteristics.

ADC transfer function

The output encoding of the AD7997/AD7998 is straight binary. The designed transcoding occurs at consecutive integer LSB values (1lsb, 2lsb, etc.). The LSB size of the AD7997 is REF/1024 and the LSB size of the AD7998 is REF/4096. Figure 20 shows the ideal transfer characteristics of the AD7997/AD7998.

Typical Wiring Diagram

A typical connection diagram for the AD7997/AD7998 is shown in Figure 22. In this figure, the address select pin (AS) is tied to V; however, AS can also be tied to AGND or left floating, allowing the user to select up to five AD7997/AD7998 devices on the same serial bus. External references must be applied to the AD7997/AD7998. This reference voltage can be in the range of 1.2 V to V. A precision voltage reference like the REF 19x family, AD780, ADR03, or ADR381 can be used to provide a reference voltage to the ADC.

SDA and SCL form a 2-wire IC-/SMBus compatible interface. Both the SDA and SCL lines require external pull-up resistors.

The AD7998-0/AD7997-0 support standard and fast IC interface modes. The AD7998-1/AD7997-1 support standard, fast, and high-speed IC interface modes. Therefore, if operating in standard or fast mode, up to five AD7997/AD7998 devices can be connected to the bus, as described earlier:

3×AD7997-0/AD7998-0 and 2×AD7997-1/AD7998-1 or 3×AD7997-1/AD7998-1 and 2×AD7997-0/AD7998-0

In high-speed mode, up to three AD7997-1/AD7998-1 devices can be connected to the bus.

The time to wake up from shutdown and acquisition before conversion is about 1 microsecond, and the conversion time is about 2 microseconds. After each conversion, the AD7997/AD7998 enter shutdown mode again, which is useful in applications involving power consumption.

analog input

Figure 21 shows the equivalent circuit of the AD7997/AD7998 analog input structure. Two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed 300 mV of the supply rails. This causes the diode to be forward biased and start conducting current to the substrate. These diodes can conduct a maximum current of 10 mA without irreversible damage to parts.

Capacitor C1 in Figure 21 is typically around 4pf, mainly due to pin capacitance. Resistor R1 is a lumped element consisting of the on-resistance (R) of the track and hold switch, and also includes the R input to the multiplexer. The total resistance is typically about 400Ω. C2 is the ADC sampling capacitor with a typical capacitance of 30 pF.

For AC applications, it is recommended to remove high frequency components from the analog input signal by using an RC bandpass filter on the associated analog input pin. In applications where harmonic distortion and signal-to-noise ratio are important, the analog input should be driven by a low impedance source. A large source impedance has a significant effect on the AC performance of the ADC. This may require the use of an input buffer amplifier. The choice of op amp is a function of the specific application.

When no amplifier is driving the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. THD increases as source impedance increases, and performance decreases. Figure 23 shows THD versus analog input signal frequency when using supply voltages of 3 V ± 10% and 5 V ± 10%. Figure 24 shows THD versus analog input signal frequency for different source impedances.

Internal register structure

The AD7997/AD7998 contain 17 internal registers that store conversion results, high and low conversion limits, and information to configure and control the device (see Figure 25). Sixteen are data registers and one is an address pointer register.

Each data register has an address that the address pointer register points to when communicating with it. The conversion result register is the only read-only data register.

address pointer register

Because it is the register that automatically writes the first data byte of each write operation, the address pointer register has no address and does not need an address. The address pointer register is an 8-bit register with the 4 LSBs used as pointer bits to store the address to one of the AD7997/AD7998 data registers. When operating in Mode 2, the 4 msbs are used as command bits (see the Operating Modes section). The first byte after each write address is the address pointer register, which contains the address of a data register. The 4 LSBs select the data register to which subsequent data bytes are written. Only the 4 LSBs of this register are used to select the data register. At power-up, the address pointer register contains all 0s and points to the conversion result register.

configuration register

The configuration register is a 16-bit read/write register that sets the operating mode of the AD7997/AD7998. The 4 msb of the register are unused. The bit functions of all 12 LSBs of the configuration register are shown in Table 9. A 2-byte write is required when writing to the configuration registers.

Conversion result register

The conversion result register is a 16-bit read-only register that stores the conversion result from the ADC in straight binary format. Reading data from this register requires a 2-byte read. Table 13 shows the content of the first byte to be read from the AD7997/AD7998, and Table 14 shows the content of the second byte to be read.

The AD7997/AD7998 conversion result consists of an alarm flag bit, three channel identifier bits, and 10- and 12-bit data results (MSB first). For the AD7997, the two lsbs (D1 and D0) of the second read contain two 0s. The three channel identification bits can be used to identify which of the eight analog input channels the conversion result corresponds to.

The Alert_Flag bit indicates whether the conversion result or any other channel result being read violates the limit register associated with it. If an alarm occurs, the host can read the alarm status register to get more information about where the alarm occurred.

limit register

The AD7997/AD7998 have four pairs of limit registers. Each pair stores the high and low transition limits for the first four analog input channels CH1 to CH4. Each pair of limit registers has an associated hysteresis register. All 12 registers are 16 bits wide; only the LSBs of the 12 registers are used for the AD7997 and AD7998. For the AD7997, the 2 LSBs of these registers, D1 and D0, should contain 0s. At power-up, the contents of each channel's data registers are full-scale, while the contents of the data registers default to zero-scale. If the conversion result exceeds the upper or lower limit set by the limit register, the AD7997/AD7998 will signal an alarm (hardware, software, or both depending on configuration). There are no limit or hysteresis registers associated with CH5 to CH8.

Data High Register CH1/CH2/CH3/CH4

The data registers for CH1 to CH4 are 16-bit read/write registers; only the 12 lsb of each register are used. This register stores the upper limit of the alert output and/or alert flag bits in the active conversion result register. If the value in the conversion result register is greater than the value in the data register, the channel will be alerted. When the conversion result returns to a value that is at least N lsb below the data register value, the alert output pin and the alert flag bit are reset. The value of N is taken from the hysteresis register associated with that channel. The alert pin can also be reset by writing to bits D2 and D1 in the configuration register. For the AD7997, D1 and D0 of the data register should contain 0s.

Data low register CH1/CH2/CH3/CH4

The data registers for each channel are 16-bit read/write registers; only the 12 LSBs of each register are used. The register stores the active alarm output and/or the lower limit of the alarm flag bit in the conversion result register. If the value in the conversion result register is less than the value in the data register, the channel will be alerted. When the conversion result returns to a value at least N lsb higher than the data register value, the alarm output pin and the alarm flag bit are reset. The value of N is taken from the hysteresis register associated with that channel. The alarm output pins can also be reset by writing to bits D2 and D1 in the configuration register. For the AD7997, D1 to D0 of the data register should contain 0s.

Hysteresis Register (CH1/CH2/CH3/CH4)

Each hysteresis register is a 16-bit read/write register of which only 12 LSBs are used. When using limit registers, the hysteresis register stores the hysteresis value N. Each pair of limit registers has a dedicated hysteresis register. The hysteresis value will determine the reset point for the ALERT pin/ALERT flag if a limit violation occurs. For example, if a hysteresis value of 8 lsb is required for the upper and lower limits of channel 1, the 12-bit word 0000 0000 1000 should be written to the hysteresis register of CH1 at the address shown in Table 8. At power-up, the hysteresis register contains the value of 2 for the AD7997 and the value of 8 for the AD7998. If a different hysteresis value is required, the value must be written to the hysteresis register of the relevant channel. For the AD7997, D1 and D0 of the hysteresis register should contain 0s.

Use limit register to store min/max conversion result of CH1 to CH4

If the full scale (i.e. all 1s) is written to the hysteresis register for a particular channel, the data and data registers for that channel no longer act as limit registers as previously described, but instead act as storage registers for The maximum and minimum conversion results returned by conversions on the channel during the specified time period. This function is useful in applications that require the maximum range of actual conversion results, rather than using alerts to signal the need for intervention. This feature can be used to monitor extreme temperatures during transport of refrigerated goods. It must be noted that at power-up, the contents of the data registers for each channel are full scale, whereas by default the contents of the data registers are zero scale. Therefore, the min and max conversion values stored in this way will be lost in the event of a power outage or cycle.

Alarm Status Registers (CH1 to CH4)

The Alarm Status Register is an 8-bit read/write register that provides information on alarm events. As described in the Limit Registers section, the Alert Status Register can be read for more information if a conversion result activates the Alert pin or Alert Flag bit in the Conversion Result register. The Alarm Status Register contains two status bits per channel, one corresponding to the data limit and the other corresponding to the data limit. A bit with status 1 shows where the violation occurred, i.e. on which channel, and whether the violation occurred on the upper or lower limit. If a second alarm event occurs on another channel between the receipt of the first alarm and the query of the alarm status register, the corresponding bit for that alarm event is also set.

The alarm status registers only contain information for CH1 to CH4, as these channels are the only ones with associated limit registers.

As shown in Table 12, the entire contents of the alarm status register can be cleared by writing 1,1 to bits D2 and D1 in the configuration register. This can also be achieved by writing all 1s to the alarm status register itself. Therefore, if the alert status register is addressed for a write operation of all 1s, the contents of the alert status register will be cleared or reset to all 0s.

Loop Timer Register

The cycle timer register is an 8-bit read/write register that stores the conversion interval value for the AD7997/AD7998 automatic cycle interval mode (see the Operating Modes section). D5 to D3 of the loop timer register are unused and should always contain 0. At power-up, the cycle timer register contains all 0s, thus disabling the automatic cycle operation of the AD7997/AD7998. To enable automatic cycle mode, the user must write to the cycle timer register to select the desired conversion interval by programming bits D2 to D0. Table 23 shows the structure of the Periodic Timer register, while Table 24 shows how the bits in this register are decoded to provide various automatic sampling intervals.

Sample Delay and Bit Trial Delay

It is recommended that no IC bus activity occurs while the conversion is taking place. However, if this is not possible, such as when operating in Mode 2 or Mode 3, in order to preserve the performance of the ADC, use bits D7 and D6 in the Loop Timer register to delay the key that occurs when there is activity on the IC bus Sampling interval and bit trials. This will result in a quiet period of time for each bit decision. In some cases, if there is too much activity on the interface line, this can increase the overall transition time. However, if the bit trial delay is extended by more than 1 microsecond, the transition is terminated.

When both D7 and D6 bits are 0, the bit trial and sampling interval delay mechanisms are implemented. The default settings for D7 and D6 are 0. To turn off both delay mechanisms, set D7 and D6 to 1.

serial interface

Control of the AD7997/AD7998 is performed over an ICcompatible serial bus. These devices are connected to this bus as slave devices under the control of a master device such as a processor.

serial bus address

Like all IC compatible devices, the AD7997/AD7998 have a 7-bit serial address. The 3 msb of this address for the AD7997/AD7998 are set to 010. There are two versions of the AD7997/AD7998, AD7997-0/AD7997-0 and AD7997-1AD7998-1. The two versions have three different IC addresses that can be selected by connecting the address select pins to AGND or V, or by leaving the pins floating (see Table 6). By giving the two versions different addresses, up to five AD7997/AD7998 devices can be connected to a single serial bus, or these addresses can be set to avoid conflicts with other devices on the bus. (See Table 6.) The serial bus protocol operates as follows.

The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA, while the serial clock line SCL remains high. This means that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, including the 7-bit address (MSB first) plus the R/W bit that determines the direction of data transfer, That is, whether the data is written to the slave device or read from the device.

The peripheral whose address corresponds to the address sent responds by pulling the data line low during the low cycle before the ninth clock pulse (called the acknowledge bit). While the selected device is waiting to read or write data from the bus, all other devices on the bus remain idle. If the R/W bit is 0, the master device writes to the slave device. If the R/W bit is 1, the master device reads from the slave device.

Data is sent over the serial bus in a sequence of 9 clock pulses, 8 bits of data followed by an acknowledgment bit from the data receiver. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition while the clock is high can be interpreted as a stop signal.

A stop condition is established when all data bytes are read or written. In write mode, the master asserts a stop condition by pulling the data line high during the 10th clock pulse. In read mode, the master device pulls the data line high for a low period before the ninth clock pulse. This is called non-recognition. The master then asserts the stop condition by taking the data line low during the low period before the 10th clock pulse and then high during the 10th clock pulse.

In one operation, any amount of data can be transferred over the serial bus, but it is not possible to mix reads and writes in one operation because the operation type is determined at the beginning and cannot be done without starting a new operation Subsequent changes.

Write to AD7997/AD7998

The AD7997/AD7998 can be written in three different ways, depending on the register being written to.

Write to the address pointer register for subsequent reads

In order to read from a particular register, the address pointer register must first contain the address of that register. If not, the correct address must be written to the address pointer register by performing a single-byte write operation, as shown in Figure 26. A write operation consists of the serial bus address and address pointer bytes. No data is written to any data registers. A read operation can then be performed to read the register of interest.

Write single-byte data to alarm status register or loop register

Both the alarm status register and the loop register are 8-bit registers, so only one byte of data can be written to each register. Writing a single byte of data to one of these registers consists of the serial bus write address, the address of the selected data register written to the address pointer register, and the data byte written to the selected data register. See Figure 27.

Write two bytes of data to limit, hysteresis, or configuration registers

Each of the four limit registers is a 16-bit register, so two bytes of data are required to write a value to any of them. Writing two bytes of data to one of these registers consists of the serial bus write address, the address of the selected limit register written to the address pointer register, and the two bytes of data written to the selected data register. See Figure 28.

If the host is addressing the AD7997/AD7998 for writes, it can write to multiple registers without re-trimming the ADC. After the first write operation to the first data register is complete, in the next byte, the host can select the next data register for the write operation by simply writing the address pointer byte. This eliminates the need to reconfigure the device to write to another data register.

Read data from AD7997/AD7998

Reading data from the AD7997/AD7998 is a 1-byte or 2-byte operation. Reading the contents of the alarm status register or the loop timer register is a single-byte read operation, as shown in Figure 29. This assumes that the specific register address was previously set by a single-byte write operation to the address pointer register, as shown in Figure 26. Once a register address is set, any number of reads can be performed from that particular register without writing to the address pointer register again.

If a read from a different register is required, the relevant register address must be written to the address pointer register, and any number of reads can then be performed from that register again.

Reading data from the configuration register, conversion result register, data register, data register, or hysteresis register is a 2-byte operation, as shown in Figure 30. The same rule applies to 2-byte reads and single-byte reads.

When reading data from a register (such as a conversion result register), if more than two read bytes are provided, the same or new data is read from the AD7997/AD7998 without reconfiguring the device. This allows the host to continuously read data from the data register without re-reading the AD7997/AD7998.

Alert/Busy PIN

The ALERT/BUSY pin can be configured as an ALERT output or a BUSY output, as shown in Table 12.

SMBus Alert

The AD7997/AD7998 alert output is an SMBus interrupt line for those devices that want to trade master capability for an extra pin. The AD7997/AD7998 is a slave-only device that uses an SMBus alarm to signal the host device that it wants to talk.

The SMBus alarm on the AD7997/AD7998 acts as an out of range indicator (a limit violation indicator).

The ALERT pins have an open-drain configuration that allows the ALERT outputs of several AD7997/AD7998s to be tied together when the ALERT pin is active low. D0 of the configuration register is used to set the active polarity of the alarm output. The power-on default is active low. The alarm function can be enabled or disabled by setting D2 of the configuration register to 1 or 0, respectively.

The host device can handle the alarm interrupt and simultaneously access all SMBus alarm devices via the alarm response address. Only the device that pulls the alarm low will acknowledge the Alarm Response Address (ARA). If multiple devices pull the ALERT pin low, during a slave address transfer, the highest priority (lowest address) device wins communication rights through standard IC arbitration.

The alarm output activates when the value in the conversion result register exceeds the value in the data register or falls below the value in the data register of the selected channel. This value is reset when a write to the configuration register sets D1 to 1, or when the N LSB returned by the conversion result is lower or higher than the value stored in the data register or data register, respectively. N is the value in the hysteresis register (see the limit register section).

The alarm output requires an external pull-up resistor that can be connected to a voltage other than V if the maximum voltage rating of the alarm output pin is not exceeded. The value of the pull-up resistor is application dependent, but should be as large as possible to avoid excessive sink current at the alarm output.

Busy

When the ALERT/BUSY pin is configured as a BUSY output, this pin is used to indicate when a conversion occurs. The polarity of the busy pin is programmed via Bit D0 in the configuration register.

Put the AD7997-1/AD7998-1 into Overdrive Mode

High-speed mode communication begins after the host addresses all devices connected to the bus with master code 00001XXX to indicate that a high-speed mode transfer is about to begin. No device connected to the bus is allowed to acknowledge the high-speed master code; therefore, this code is followed by a non-acknowledge (see Figure 31). The master must then issue a repeat start with the R/W bit followed by the device address. The selected device then confirms its address.

All devices continue to operate in high speed mode until a stop condition is issued by the master device. All devices return to fast mode when a stop condition is issued.

Address Selection (AS)PIN

The address select pins on the AD7997/AD7998 are used to set the IC address of the AD7997/AD7998 device. The AS pin can be tied to V, AGND, or left floating. The selection should be as close to the as pin as possible; avoid long tracks to introduce extra capacitance on the pin. This is important for floating point selects because the AS pin must be charged to the midpoint after the start bit during the first address byte. The extra capacitance on the AS pin increases the time it takes to charge to midpoint and can lead to incorrect decisions about the device address. When the AS pin is left floating, the AD7997/AD7998 can operate with capacitive loads up to 40 pF.

operating mode

When power is first applied to the AD7997/AD7998, the ADC is powered up in sleep mode and typically remains in this shutdown state when not converting. There are three ways to initiate a conversion on the AD7997/AD7998.

Mode 1 - using CONVST pin

The conversion pulse conversion signal can be initiated on the AD7997/AD7998 in the following ways. The conversion clock for this part is generated internally, so no external clock is required, except when reading from or writing to the serial port. On the rising edge of CONVST, the AD7997/AD7998 begin to power up (see point A in Figure 32). The power-on time for shutdown mode is approximately 1 microsecond for the AD7997/AD7998; to fully power up the part, the CONVST signal must be held high for 1 microsecond. After this time, CONVST can be lowered. This power-on time also includes the acquisition time of the ADC. The falling edge of the CONVST signal puts the track and hold into hold mode; a conversion is also initiated at this point (point B in Figure 32). When the transition is complete, after about 2 microseconds, the part returns to the off state (point C in Figure 32) and stays there until the next rising edge of const. The host can then read the ADC to obtain the conversion result. The address pointer register must point to the conversion result register to read back the conversion result.

If the CONVST pulse is not held high for more than 1 microsecond, the falling edge of CONVST will still initiate a conversion, but the result will be invalid because the AD7997/AD7998 are not fully powered up when the conversion occurs. To maintain the performance of the AD7997/AD7998 in this mode, it is recommended that the IC bus be kept quiet during conversions.

When operating the AD7997, bits C4 through C1 in the loop timer register and address pointer register should contain all 0s/AD7998 in this mode. For all other modes of operation, the CONVST pin should be tied low.

To select an analog input channel for conversion in this mode, the user must write to the configuration register and select the corresponding channel for conversion. Set up a series of channels to be converted for each CONVST pulse, setting the corresponding channel bits in the configuration register (see Table 11).

After the conversion is complete, the host can address the AD7997/AD7998 to read the conversion result. If further conversions are required, the ADCs can achieve typical throughputs of up to 121 kSPS when operating the AD7997-1/AD7998-1 in Mode 1 and reading after converting with 3.4mhz f.

Mode 2 – Command Mode

This mode allows conversions to be started automatically when a write operation occurs. To use this mode, command bits C4 through C1 in the address pointer byte shown in Table 7 must be programmed.

To select an analog input for conversion in this mode, the user must set bit C4 of the address pointer byte to C1 to indicate the channel to convert (see Table 26). This mode is not used when all four command bits are 0.

To select a sequence of channels to convert in this mode, first select the channels to be included in the sequence by setting the channel bits in the configuration register. Next, set the command bit in the address pointer byte to 0111. When the command bit of the address pointer byte is set to 0111, the ADC knows to look in the configuration register for the channel sequence to convert. The ADC starts converting on the lowest channel in the sequence and then on the next lowest channel until all channels in the sequence are converted. When a stop bit is received, the ADC stops the conversion sequence.

Figure 29 illustrates a 2-byte read operation of the conversion result register. This is usually done before writing to the address pointer register, so that the following read accesses the desired register, in this case the conversion result register (see Figure 26). If command bits C4 through C1 are set when the contents of the address pointer register are loaded, the AD7997/AD7998 begin to power up and convert on the selected channel. Power-up begins on the fifth SCL falling edge of the address point byte (see point A in Figure 33).

Table 26 shows the channel selection in this mode via command bits C4 to C1 in the address pointer register. The combined wake-up, acquisition, and conversion times take about 3 microseconds. After a write operation, the AD7997/AD7998 must be addressed again to indicate that a read operation is required. Then read from the conversion result register. This read accesses the conversion result of the channel selected by the command bits. If command bits C4 to C1 are set to 0111, and bits D4 and D5 are set in the configuration register, a 4-byte read is required. The first read accesses the data converted on V1. When reading, the transition occurs on V2. The second read accesses this data from V2. Figure 34 illustrates how this mode works; the user should first write to the configuration register to select the sequence of channels to convert before writing to the addressing section using the command bits set to 0111.

When operating the AD7997-1/AD7998-1 in Mode 2 of High Speed Mode 3.4mhz SCL, the conversion may not complete until the host attempts to read the conversion result. If this is the case, the AD7997-1/AD7998-1 hold the SCL line low during the ACK clock after the address is read until the conversion is complete. After the conversion is complete, the AD7997-1/AD7998-1 release the SCL line and the host can then read the conversion result.

After a conversion is initiated by setting the command bit in the address pointer byte, the AD7997/AD7998 stops the conversion if the AD7997/AD7998 receives a STOP or NACK from the host.

Mode 3 - Auto Cycle Interval Mode

Auto-conversion loops can be selected and enabled by writing a value to the loop timer register. The conversion period interval can be set on the AD7997/AD7998 by programming the relevant bits in the 8-bit period timer register, as decoded in Table 24. Only 3 LSBs are used to select the periodic interval; the 5 MSBs should contain 0s. When the 3 LSBs of the register are programmed with any configuration other than all 0s, a conversion occurs every X ms; the period interval X depends on the configuration of these 3 bits in the period timer register. There are seven different cycle time intervals to choose from, as shown in Table 24. After the conversion is complete, the part is powered down again until the next conversion occurs. To exit this mode of operation, the user must program the 3 LSBs of the loop timer register to contain all 0s.

To select a channel to operate in loop mode, set the corresponding channel bits D11 to D4 of the configuration register. If more than one channel bit is set in the configuration register, the ADC automatically cycles through the channel sequence starting with the lowest channel and working upwards in the sequence. After the sequence is complete, the ADC starts converting on the lowest channel again, continuing the looping sequence until the loop timer register contents are set to all 0s. This mode is useful for monitoring signals such as battery voltage and temperature, and only alerts when limits are violated.

Dimensions