The ISL1208 device is a low power real-time clock timing and crystal compensation, clock/calendar, power failure indicator, periodic or polling alarms, intelligent battery backup switch and battery backed user SRAM. This oscillator uses an external low cost 32.768kHz crystal. The real-time clock keeps track of hours, minutes, and seconds in separate registers. The device has a calendar to register the date, month, year and day of the week. This calendar is accurate to 2099 with automatic leap year correction

feature

Real Time Clock/Calendar - Tracks time in hours, minutes and seconds - day of the week, day, month, year

15 selectable frequency outputs

Single alarm - can be set to second, minute, hour, day, day or month of the week - single event or pulse interruption mode

Automatic battery backup or supercapacitor

Power Failure Detection

On-chip oscillator compensation

2 bytes of battery-backed user SRAM

I2C interface - 400kHz data transfer rate

400nA battery supply current

Same pinout as ST M41Txx and Maxim DS13xx devices

Small Package Options - 8 Ld MSOP and SOIC Packages

Lead-free plus annealed (RoHS compliant) available

application

Utility meter

HVAC equipment

Audio/Video Components

STB/TV

modem

Network routers, hubs, switches, bridges

cellular infrastructure equipment

Fixed broadband wireless equipment

Pager/PDA

POS equipment

Test Instruments/Fixtures

Office automation (copiers, fax machines)

household appliances

computer products

Other Industrial/Medical/Automotive

Absolute Maximum Ratings

Voltage on VDD, VBAT, SCL, SDA and IRQ pins

(relative to the ground). -0.5V to 7.0V

Voltage on the X1 and X2 pins

(relative to the ground). -0.5V to VDD+0.5 (VDD mode)

-0.5V to VBAT+0.5 (VBAT mode)

Storage temperature. -65°C to +150°C

Lead temperature (soldering, 10s). 300 degrees Celsius

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation of the device under the above or any other conditions stated in the operating section of this specification is not implied.

DC Operating Characteristics - RTC Temperature = -40°C to +85°C unless otherwise noted.

Unless otherwise specified, serial interface specifications exceed recommended operating conditions. (continued)

notes:

1. IRQ&FOUT is not activated.

2. LPMODE=0 (default).

3. To ensure proper timing, the VDD SR-specification must be followed.

4. Typical values are T=25°C and 3.3V supply voltage.

Typical performance curves at 25°C unless otherwise specified

General Instructions

The ISL1208 device is a low power real-time clock timing and crystal compensation, clock/calendar, power failure indicator, periodic or polling alarms, intelligent battery backup switching and battery backed user SRAM. This oscillator uses an external low cost 32.768kHz crystal. The real-time clock keeps track of hours, minutes, and seconds in separate registers. The device has a calendar to register the date, month, year and day of the week. This calendar is accurate to 2099 with automatic leap year correction. The powerful alarms of the ISL1208 can be set to any matching clock/calendar value. For example, every Tuesday or March 21st at 5:23am. The alarm status can be obtained by checking the status register, or the device can be configured to provide hardware interrupts via the IRQ pin. Alerts have repeating patterns allowing every minute, hour, day, etc. The device also provides an alternate power input pin. This VBATpin allows the device to automatically switch from VDD to VBAT by battery or with a supermap. This entire ISL1208 device is fully operational between 2.0V and 5.5V The clock/calendar part of the device remains fully operational down to 1.8V (standby mode).

Pin Description

The X1, X2, X1 and X2 pins are the inverting amplifiers, respectively. An external 32.768kHz quartz crystal is used together with the ISL1208 as a clock. Internal compensation circuitry provides accuracy over the high operating temperature range -40°C to +85°C. This oscillator compensation network can be used to calibrate crystal timing accuracy during manufacturing or external temperature active temperature sensor and microcontroller compensation. The device can also be powered directly from 32.768kHz at pin X1.

VBAT

This input provides an alternate supply voltage for the device. If the VDD supply is interrupted. This pin can be connected to a battery, a super cap or tied to the ground if not in use. IRQ/FOUT (Interrupt Output/Frequency Output) This dual function pin can be used as an interrupt or frequency output pin. IRQ/FOUT mode is controlled by the frequency output control bits of the control/status register. interrupt mode. The pin provides interrupt signal output. This signal informs the host processor that an action has occurred and is requested. This is an open channel effective low output. Frequency output mode. The pin output clock signal is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is open drain active low output.

Serial Clock (SCL)

The SCL input is used to clock all serial data in and out of the device. The input buffer on this pin is always active (not gated). when the VBAT pin is activated to minimize power consumption.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data to and from the device. It has an open drain output which can be either or other open drain or open collector output. Input In normal mode, the buffer is always active (not gated). Open-drain outputs require pull-up resistors. The output circuit controls the fall time of the output signal using a slope control pull-down. The circuit is designed for 400kHz I2C interface speed. It is disabled when the backup power supply on the VBAT pin is active. VDD, ground chip power and ground pins. The device will run on power from 2.0 volts to 5.5 volts. A 0.1µF capacitor is recommended to connect the VDD pin to ground.

Function description

Power Control Operation The power control circuit accepts VDD and VBAT inputs. Several types of batteries are available for use with Intersil RTC products. For example, a 3.0 volt or 3.6 volt lithium battery with the right battery size can power the 1208 for up to 10 years. Another option is to use an application suitable for VDD interrupts to one month. See the application section for more information.

Normal Mode (VDD) to Battery Backup Mode

(VBAT)

To transition from VDD mode to VBAT mode, two

The following conditions must be met:

Condition 1:

VDD

where VBATHYS≈50mV

Condition 2:

VDD

Where VTRIP≈2.2V

Backup battery mode (VBAT) to normal mode (video display)

ISL1208 device will switch from VBAT mode to VDD mode

When one of the following occurs:

Condition 1:

VDD>VBAT+VBATHYS

where VBATHYS≈50mV

Condition 2:

VDD>VTRIP+VTRIPHYS

where vtripy≈30mV

These power control cases are shown in Figures 9 and 10.

The I2C bus is disabled in battery backup mode to provide low power. Apart from that, all RTC functions are run in battery backup mode. Except for SCL and SDA, all inputs and outputs of the ISL1208 are active in battery backup mode unless register is disabled via control. User SRAM runs in battery backup mode down to 2V. Power failure detection The ISL1208 provides a real-time clock fault bit (RTCF) to detect a total power failure. It allows the user to determine that the device has powered up the device (VDD and VBAT) after losing all power. The normal power switch of the ISL1208 in low power mode is designed only when the VDD supply is lost. This will ensure that the device can accept a wide range of reliable switching to backup mode. Another mode, called low power mode, allows direct switching from VDD to VBAT without requiring VDD to drop below VTRIP. Since additional monitoring of VDD and VTRIP is no longer required, the circuit is turned off, using less power when operating from VDD. Power saving is typically 600nA at VDD=5V. Low power mode is via the LPMODE bit in the Control and Status register. Low power mode is useful in systems where VDD is normal and always higher than VBAT. The device will lag about 50mV from VDD to VBAT when VDD is below VBAT to prevent VDD from switching. In a system with VDD=5V and lithium backup VBAT=3V, low power mode can be used. However, it is not recommended that VDD=3.3V±10%, VBAT≥3.0V, and the IR voltage drop in the VDD line is limited. Intermediate™ Power Saver The ISL1208 has a™ Power Saver to prevent initial battery current drain before first use. For example, battery-backed rtcs are usually packaged on a circuit board that connects to the battery. To preserve battery life, the ISL1208 will not source from battery until the device is first sourced from VDD. After that, the device will switch to battery backup mode when VDD power is disconnected.

real time clock operation

The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain accurate internal representation of seconds, minutes, hours, weeks, days, months, and years. RTC also has leap year correction. The clock is also corrected for months with less than 31 days and it controls the 24-hour or AM/PM format. When the ISL1208 is powered up after losing VDD and VBAT, the clock will be clocked until at least one byte is written to the clock register.

Accuracy of real time clock

The accuracy of the real time clock depends on the frequency of the quartz crystal used as the time base for the RTC. Because the resonant frequency of a crystal is temperature dependent, the RTC performance will also depend on temperature. The frequency deviation of the crystal is the nominal frequency of the crystal from the crystal. For example, a frequency deviation of about 20ppm translates to about 1 minute per month. These parameters are available from the crystal manufacturer. The ISL1208 provides an on-chip crystal compensation network to adjust the load capacitance to adjust the oscillator frequency from -94ppm to +140ppm. See the Applications section for more details. Single event and interrupt alert modes are enabled by the ALME bit. Option to select single event or interrupt alarm mode bits via IM. Note that when the frequency output function is enabled, the alarm function is disabled. Standard alarms allow time, date and date of the alarm week, month, year. When a time alarm occurs in one-shot mode, the IRQ pin will be pulled low and the alarm status bit (ALM) will be set to "1". Pulse interrupt mode allows repeating or repeating alarm functions. Therefore, once an alarm is set, the device will continue to match the alarm for each occurrence of the alarm and now. So it alerts every minute (if only nth second is set) or year (if at least nth month is set). During Pulse Interrupt mode, the IRQ pin will be pulled low for 250ms and the alert status bit (ALM) will be set to "1". Note: The ALM bit can be reset by the user or cleared automatically using the auto-reset mode (see ARST bits). The alarm function enables/disables the backup mode using the FOBATB bit while on battery. For more information on alarms, see the alarm register description.

Frequency output mode

The ISL1208 can optionally provide a frequency output to signal using the IRQ/FOUT pin. The frequency output mode sets the frequency value from 0 to 32kHz by using the FO bit to select 15 possible outputs. The frequency output can use the FOBATB bit in battery backup mode. The general user SRAMISL1208 provides 2 bytes of user SRAM. SRAM will continue to operate in battery backup mode. However, it should be noted that the I2C bus is disabled in battery backup mode. I2C Serial Interface The ISL1208 has an I2C serial bus interface that provides access control and status registers as well as user SRAM. I2C serial interface with other industrial I2C serial bus protocol signals (SDA) and clock signals (SCL) using bidirectional data. Oscillator Compensation The ISL1208 provides timing correction options as crystal oscillator temperature changes manufacture calibration or actively calibrate. The total possible offset is typically -94ppm to +140ppm. Two available compensation mechanisms are as follows:

1. An Analog Trim (ATR) register that can be used to adjust the oscillator's single on-chip digital capacitor capacitance trim. A single digital capacitor is selectable from 9pF to 40.5pF (based on 32.758kHz). This translates to a calculated offset of about -34ppm to +80ppm. (See ATR description.)

2. A digital trim register (DTR) that can be used to adjust the timing counter by ±60ppm. (See DTR description.) Also provides the ability to adjust the crystal capacitance when the ISL1208 switches from VDD to battery backup mode. (See Battery Mode ATR Selection for details.) Register Description The battery backup registers can be read from or written to address [00h:13h] from byte "1101111x". The defined addresses and default values are shown in Table 1. Address 09h is unused. Reading or writing 09h will not affect the operation of the device, but should be avoided. The contents of a register can be accessed by performing a direct byte or page operation on any register by performing a register address. The register is divided into 4 parts. these are:

1. Real Time Clock (7 bytes): Addresses 00h to 06h.

2. Control and Status (5 bytes): Addresses 07h to 0Bh.

3. Alarm (6 bytes): Addresses 0Ch to 11h.

4. User SRAM (2 bytes): Addresses 12h to 13h. No address for more than 13 hours.

Writing to the RTC registers (00h to 06h) is allowed only if the WRTC bit (bit 4 of address 07h) is set to '1'. Multibyte read and write operations are limited to a number of sections per operation. Accessing another section requires a new action. A read or write can start at any address within the sector. The register address can be read at any time by performing a random read at any location. This will return the location of the contents of this register. By performing sequential reads. For RTC and alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the timing of the read. A sequential read does not result in an array from memory. At the end of the reading, the master offers to stop running and release the bus. After a read, the address remains at the previous address + 1, so the user can perform a current address read and continue reading the next register. It is not necessary to set the WRTC bit control and status, alarm and user SRAM registers before writing.

real time clock register

Addresses [00h to 06h] RTC Registers (SC, MN, HR, DT, MO, YR, DW) These registers describe the BCD representation of time. As such, SC (seconds) and MN (minutes) range from 0 to 59, HR (Hour) can be in 12-hour or 24-hour mode, DT (date) is 1 to 31, month is 1 to 12, and year is 0 To 99, DW (day of week) is 0 to 6. The DW register provides day-of-week status and uses three bits DW2 to DW0 to represent the week. The counter in the loop 0-1-2-3-4-5-6-0-1 Advance -2 - Assigning a value to a specific date The time of the week is arbitrary and may be determined by the system software designer. The default value is defined as "0". 24-hour format If the MIL bit of the HR register is "1", the RTC uses the 24-hour format. If the MIL bit is "0", the RTC uses the 12-hour format and the HR21 bit is used as the AM/PM indicator, with a "1" for PM. The clock defaults to 12-hour format HR21 time is "0". Leap years plus February 29 are defined as years divisible by 4. Years divisible by 100 are not leap years unless they are also divisible by 400. This means that 2000 is a leap year and 2100 is not. Island 1208 does not work for leap years in 2100. Control and Status Register Addresses [07h to 0Bh] The control and status registers consist of registers, interrupt and alarm registers, analog trimming and digital trimming registers. Status Register (SR) The status register is located at address 07h. This is a variable register that provides control or status of the RTC fault, battery mode, alarm trigger, clock counter, crystal oscillator enable and write protect auto-reset status bits.

The real-time clock fault bit (RTCF) is set to '1' after a total power failure. This is read only when the device is powered up after losing all power. This bit is set first regardless of whether VDD or VBAT is applied. The loss of only one supply does not set the RTCF bit to "1". A full power down after the first valid write to the RTC section will reset the RTCF bit to '0' (writing a single byte is sufficient). Battery Bit (BAT) This bit is set to '1' mode when the device goes into battery backup. This bit can be reset manually by the user or automatically by enabling the auto-reset bit (see ARST bit). Writing this bit in the SR can only set it to '0', not '1'. Alarm Bits (ALM) These bits inform if the alarm matches the real-time clock. If there is a match, the corresponding bit is set to '1'. This bit can be manually reset to '0' by the user, or it can be reset automatically by enabling the auto-reset bit (see ARST bit). Writes to this bit in SR can only be set to '0', not '1'. Note: A read operation of an alarm bit set by an alarm that occurs during SR will remain set after the read operation is complete. Writing the RTC Enable bit (WRTC) to the WRTC bit enables or disables the RTC timing register. The factory default setting for this bit is '0'. At initialization or power-up, WRTC must be set to "1" to enable the RTC. Completing a valid write (stop), the RTC starts counting. RTC internal 1Hz signal during valid write cycle. Crystal Oscillator Enable Bit (XTOSCB) This bit enables/disables the internal crystal oscillator. when? XTOSCB is set to '1', the oscillator is disabled, and the X1 pin allows an external 32kHz signal to drive the RTC. At power-up, the XTOSCB bit is set to '0'. Auto-Reset Enable Bit (ARST) This bit enables/disables the auto-reset of the BAT for the ALM-only status bits. When the ARST bit is set to '1', these effectively read the corresponding status register (with a valid stop condition). When ARST is cleared to "0", the user must manually reset the bat and almbit.

Frequency Output Control Bits (FO<3:0>) These bits enable/disable the frequency output function and select the output frequency of the IRQ/FOUT pin. See Table 4 for frequency selection. When the frequency mode is enabled, it will override the alarm mode of the IRQ/FOUT pin

Frequency Output and Interrupt Bit (FOBATB) This bit enables/disables FOUT/IRQ pin backup mode (ie VBAT supply active) during battery time. The FOUT/IRQ pin is disabled during battery backup mode when FOBATB is set to '1'. This means that the output and alarm output functions are disabled. When FOBATB is cleared to '0', the FOUT/IRQ pin is enabled in battery backup mode. Low Power Mode Bit (LPMODE) This bit enables/disables low power mode. With LPMODE="0", the device will be in normal mode, and when VDD

There are 6 analog trim bits, ATR0 to ATR5, in order to adjust the frequency compensation of the RTC in order to adjust the load capacitance value on the chip. Each bit has a different capacitance adjustment weight. For example, using Citizen CFS-206 crystals with different ATR bit combinations provides nominal frequency compensation from -34 to +80ppm. This analog trim and digital trim combine to achieve +140ppm of the -94 trim total. Valid on-chip series load capacitance, CLOAD, ranges from 4.5pF to 20.25pF with a midscale value of 12.5p (default). CLOAD is controlled via two digitally altered capacitors, CX1 and CX2, connected from the X1 and X2 pins to ground (see Figure 11). CX1 and CX2 are given by:

For example, CLOAD(ATR=00000)=12.5pF, CLOAD(ATR=100000)=4.5pF, CLOAD(ATR=011111)=20.25 lbf. The entire range of capacitance for the series load combinations went from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. Battery Mode ATR Selection (BMATR<1:0>) Because the crystal oscillator's accuracy depends on VDD/VBAT operation, the ISL1208 provides an adjustable capacitor between VDD and VBAT for switching between power supplies.