feature

Fault detected on 7 separate power supplies; 1 high voltage supply (2 V to 14.4 V); 4 positive voltage supplies (2 V to 6 V); 2 positive/negative voltage supplies (+2 V to +6 V and - 2 V to -6 V); watchdog detector input timeout delay programmable from 200 ms to 12.8 seconds; 4 general purpose logic inputs; programmable logic block combination and sequencing logic controls for all inputs and outputs 9 programmable Output Drivers: Open collector (requires external resistor) Open collector, internal pull-up to VDD; fast pull-up to VDD; open collector with VPn internal pull-up; fast internal start-up to VPn; internal charge pump High drive (for external N-channel FET PDO 1 to 4 only); EEPROM - 256 bytes of user EEPROM; industry standard 2-wire bus interface (SMBus); guaranteed PDO low with VPn, VH=1v.

application

Central office systems; servers; infrastructure network boards; high-density, multi-voltage system cards.

General Instructions

The ADM1060 is a programmable monitoring/sequencing device that provides a single-chip solution for multi-supply fault detection and sequencing in communication systems.

In central offices, servers, and other infrastructure systems, common backplane DC power is reduced to multi-board power through DC-DC converters. These multiple power supplies are used to power different parts of the board, such as 3.3v logic circuits, 5v logic circuits, DSP cores, and DSP I/O circuits. Some parts are often required to be powered up before others; for example, a DSP core may need to be powered up before DSP I/O and vice versa to avoid corruption, miscommunication, or latching. The ADM1060 helps with this, providing fault detection and sequencing/combination logic for up to 7 independent supplies. The seven power failure detectors include one high voltage detector (up to +14.4V), two bipolar voltage detectors (up to +6V or as low as -6V), and four positive and low voltage detectors (up to +6V). All detectors can be programmed to detect undervoltage, overvoltage, or out-of-window (undervoltage or overvoltage) conditions. The inputs to these power failure detectors are through the VH (high voltage) pin, the VBn (positive or negative) pin, and the VPn (positive only) pin. The VH supply or one of the VPn supplies is used to power the ADM1060, whichever is higher. This ensures that in the event of a power failure, the ADM1060 remains active for as long as possible, enabling a reliable fault flag to be asserted and an orderly system shutdown.

Other inputs to the ADM1060 include a watchdog detector (WDI) and four general purpose inputs (GPIn). A watchdog detector can be used to monitor the processor clock. If the clock does not toggle (low-to-high or high-to-low) within a programmable timeout period (up to 18 seconds), the fail flag will be asserted. These four general-purpose inputs can be configured as logic buffers or detect positive/negative edges and generate logic pulses or levels from these edges. Therefore, the user can input control signals from other parts of the system (for example, reset or power good) to gate the sequence of power supplies monitored by the ADM1060.

The ADM1060 has nine programmable driver outputs (PDOs). All nine outputs can be configured as logic outputs, which provide the end user with multiple functions such as reset generation, power good status, LDO enable and watchdog timeout assertion. PDOs 1 to 4 have the additional feature of being able to provide an internal charge pump high voltage for use as a gate drive for an external N-channel FET that can be placed in the path of one of the monitored supplies.

All inputs and outputs described previously are controlled by a Programmable Logic Block Array (PLBA). This is the logic core of the ADM1060. It consists of 9 macrocells, one for each PDO. These macrocells are essentially just wide AND gates. Any/all inputs can be used as inputs to these macrocells. The output of a macrocell can also be used as input to any macrocell other than itself (input to itself will result in a non-terminating loop). The PLBA output controls the PDO of the ADM1060 through a delay block where a delay from 0 ms to 500 ms can be programmed on the rising and/or falling edge of the data. This results in very flexible sequencing capabilities. So, for example, PDO1 can be programmed to not assert until the VP2, VP3, and VP4 supplies are in tolerance; VB1 and VH have been in tolerance for 200 ms; and PDO7 has been asserted. A simple ordering operation is to concatenate each PLB output into the input of the next PLB, so that PDO9 is not asserted until PDO8 is asserted, which in turn is not asserted until PDO7 is asserted, and so on.

All functions described here can be programmed via the provided industry standard 2-wire bus (SMBus). Device settings can be written to EEPROM memory to automatically program the device at power up. The EEPROM is organized in 512 bytes, half of which is used to program all functions on the ADM1060. The other 256 bytes of EEPROM are used for general purpose systems such as date codes and system IDs. It can also be accessed for read/write via a 2-wire interface. In addition, each output state can be overshoot directly from the serial interface, allowing further levels of control, such as in system-controlled soft power shutdown.

Absolute Maximum Ratings

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Thermal characteristics

28 lead TSSOP package: θJA=98°C/W

Typical performance characteristics

enter

Powering the ADM1060

The ADM1060 is powered by the highest voltage input on the positive-only power supply input (VPn) or the high-voltage power supply input (VH). The same pins are used for power failure detection (described below). The VDD arbiter on the device selects which power supply to use. The arbiter can be thought of as diodes or positive supplies together (as shown in Figure 17), the diodes are complemented by switches in a synchronous rectifier fashion to minimize voltage losses. This loss can be reduced to ~0.2 V, enabling the ADM1060 to be powered from supplies as low as 3.0 V. Note that power on the VBn pins cannot be used to power the device, even if the inputs on these pins are positive. Additionally, a minimum supply of 3.0 V must be present on one of the VPn pins to properly power up the ADM1060. A power supply of at least 4.5 V can be used on VH. This is because there is no synchronous rectification circuit on the VH pin, resulting in a voltage drop of about 1.5v across the diode of the VDD arbiter.

To isolate the on-chip power supply from noise, an external capacitor to ground is required. This capacitor should be connected to the VDDCAP pin as shown in Figure 17. Capacitors have another use during "power outages" (momentary power outages). Under these conditions, when the input supply VPn temporarily drops below VDD, the synchronous rectification switch is immediately turned off so that VDD is not pulled down. The VDD capacitor can then act as an energy store to keep the chip alive until the next highest supply takes over power to the device. A 1µF capacitor is recommended for this function. The minimum capacitance requirement is 0.1µF.

Note that if there are two or more supplies within 100 mV of each other, the supply that controls VDD first will remain in control. For example, if VP1 is connected to a 3.3V supply, VDD will be powered through VP1 to about 3.1V. If VP2 is connected to another 3.3v supply, VP1 will still power the device unless VP2 is 100mV higher than VP1.

Another capacitor is required at the VCCP pin of the ADM1060. This capacitor is the storage capacitor for the central charge pump. Again, a 1µF capacitor is recommended for this function. The minimum capacitance requirement is 0.1µF.

Programmable Power Failure Detector (SFD)

The ADM1060 has seven programmable power supply fault detectors (SFDs): one high voltage detector (+2 V to +14.4 V), two bipolar detectors (+1 V to +6 V, -2 V to -6 V ) and four positive-only voltage detectors (+0.6 V to +6 V). Inputs are applied to these detectors via the VH (high voltage power input), VBn (bipolar power input), and VPn (positive only input) pins, respectively. The SFD has detected a failure in any of these input power sources. Faults are defined as undervoltage (power supply is below a preprogrammed level), overvoltage (power supply is above a preprogrammed level), or out of window (power supply deviates from a preprogrammed overvoltage or undervoltage threshold). Only one fault type can be selected at a time.

Undervoltage (UV) faults are detected by comparing the input supply to a programmed reference (undervoltage threshold). If the input voltage falls below the undervoltage threshold, the output of the comparator goes high, thus judging a fault. The undervoltage threshold is programmed using an 8-bit DAC. Within a given range, the UV threshold can be set as:

The reference is programmed using a second comparator and DAC to detect overvoltage (OV) faults in exactly the same way.

All thresholds are programmed using 8-bit registers, one register for each of the seven UV thresholds and one register for each of the seven OV thresholds. User-programmed UV or OV thresholds are given by:

VT is the desired threshold voltage (UV or OV)

VR is the threshold voltage range

N is the decimal value of the 8-bit code

VB is the bottom of the threshold range

So the code for a given threshold is given by:

For example, if the user wishes to be at VP1, the code to be programmed in the PS1OVTH register (discussed later) would be:

Therefore, N=191 (1011111 in binary, or 0xBF)

The available threshold ranges and their resolutions are shown in Table 3. Note that the low end of the detection range is fixed at 33.33% of the top of the range. Also note that for a given SFD, the ranges overlap; for example, VH goes from 2v to 6v, then from 4.8v to 14.4v. This is to provide better threshold setting resolution when the power supply value is reduced.

Figure 18 illustrates the function of the programmable SFD (for a positive supply).

SFD comparator with hysteresis

The OV and UV comparators shown in Figure 18 always observe VPn through a potential divider. To avoid jitter (multiple transitions when the input is very close to a set threshold level), these comparators have digitally programmable hysteresis. The UV and OV hysteresis can be programmed in two registers that are similar but separate from the UV or OV threshold registers. Only the five LSBs of these registers can be set. When the supply voltage exceeds the allowable value, the hysteresis increases. Thus, the user can determine the degree to which the input must rise above the UV threshold again before the evaluation of the UV fault is lifted. Similarly, the user can determine how much the input must fall below the OV threshold again before the evaluation of the OV fault is canceled. The lag factor is given by:

Where: VH is the required hysteresis voltage; NTHRESH is the decimal value of the 5-bit hysteresis code.

Therefore, if a low-range threshold detector is selected, the maximum hysteresis is defined as:

The hysteretic programming resolution is the same as the threshold detection range, i.e. 37.5 mV for the high range, 15.6 mV for the mid range, 7.8 mV for the low range, and 4.7 mV for the ultra-low range.

Bipolar SFD

The two bipolar SFDs also allow detection of faults on the negative supply. The polarity bit in the setup register of this SFD (bit 7 in register BSnSEL, see register map on the back) determines whether the positive or negative input should be applied to VBn. When the SFD is in negative mode, only one range (-6 V to -2 V) is available. Note that a bipolar SFD cannot be used to power the ADM1060 even if the voltage on VBn is positive.

SFD fault type

SFD can assert three types of faults: OV fault, UV fault and out-of-window fault (UV fault and OV fault exist simultaneously). The desired fault type is programmed using the fault type selection bits (bits 0, 1 in the register). If the application requires the detection of separate fault conditions on one supply (for example, PDO1 is asserted if a UV fault occurs on a 3.3 V supply; PDO9 is asserted if a UV fault occurs on the same 3.3 V supply), then that supply will Needs to be applied to multiple input pins.

Fault filtering on SFD

The final stage of SFD is the fault filter. This block provides temporal filtering of the output of the SFD. This allows the user to remove any spurious transitions (such as supply bounces on open). This degumming function is in addition to the programmable hysteresis of the SFD. The fault filter timeout is programmable up to 100 microseconds. If a pulse appears at the input that is shorter than the programmed timeout, the pulse is masked and a signal change appears at the output. If an input pulse appears on the input for longer than the programmed timeout, the pulse will appear on the output. The output will be delayed (relative to the input) by the length of the programmed timeout.

Figure 19 shows the implementation of fault filtering.

Programming SFD on SMBus

The details of using SMBus will be described later, but the register names associated with the power failure detector block, the bitmap of these registers, and the function of each bit are described in the table below. The table below shows how to set the UV threshold, UV hysteresis, OV threshold, OV hysteresis, fault filtering, and fault type for each SFD on the ADM1060.

Watchdog Fault Detector

The ADM1060 has a watchdog fault detector. This can be used to monitor the processor clock to ensure proper operation. The probe monitors the WDI pin, expecting a low-to-high or high-to-low transition within a pre-programmed time period. The watchdog timeout period can be programmed from 200 milliseconds up to a maximum of 12.8 seconds.

If no transition is detected, both signals are asserted. One is to latch a high signal, indicating that a fault has occurred. Another signal is a low-high-low pulse that can be used as a reset signal for the processor core. The width of this pulse can be programmed from 10 microseconds to a maximum of 10 milliseconds. These two can select the watchdog signal as input to each plb (see PLBA section). They can also be inverted if desired; for example, if the processor needs a high-low-high-high pulse to reset. Thus, a fault on the watchdog can be used to pulse or latch the output on any or all of the nine PDOs.

The lock signal can be cleared low by reading LATF1 on the SMBus interface, then LATF2 (see the Fault Registers section). The RAM register list and the bitmap of the watchdog fault detector are shown below.

General Purpose Input (GPI)

The ADM1060 has four general purpose logic inputs (GPI). These are TTL/CMOS logic level compatible. Standard logic signals can be applied to the pins: reset generator reset, power signal, fault flag, manual reset, etc. These signals can be gated by other inputs monitored by the ADM1060 and used to control the state of the PDO. Inputs can simply be buffered, or logic transitions can be detected and pulsed outputs generated. The width of this pulse can be programmed from 10 microseconds to a maximum of 10 milliseconds. The configuration of the GPI is shown in the registers and bitmaps below.

GPIs also have glitch filters similar to those offered on SFDs. This allows the user to ignore spurious transitions on GPI. For example, a fault filter can be used to release a manual reset switch. The length of the fault filter can also be programmed.

Logic states of GPIs and other logic inputs

Each GPI can have a weak (10µA) pull-down current source. A current source can be connected to the input by programming the relevant bits in the PDEN register. This enables the user to control the condition of these inputs, pulling them to GND even if they are unused or floating.

Note that the SMBus address pins A0 and A1 and the WDI pin provide the same pull-down function. Registers are used to program which inputs are connected to the current source.

programming

programmable logic block array

The ADM1060 contains a Programmable Logic Block Array (PLBA). This block is the logical core of the device. The PLBA (and PDB see the Programmable Delay Blocks section) provide the sequencing functionality of the ADM1060. The assertion of the nine programmable driver outputs (PDOs) is controlled by the PLBA. The PLBA consists of 9 macrocells, one for each PDO channel. The main components of the macrocell are two wide AND-OR gates, as shown in Figure 20. Each AND gate represents a function (A or B) that can be independently used to control the assertion of the PDO pin. Each AND gate has 21 inputs:

• Logic outputs for all seven power failure detectors

• Four GPI logic inputs

• Watchdog fault detector (lock and pulse)

• Delayed output of any other macrocell (the output of a macrocell cannot be its own input, as this would result in a non-terminating loop).

All 21 inputs are hardwired to Function A and Function B and Gate. The user can then choose which inputs control the output. This is done with two control signals, mk (a mask bit, setting it ignores the associated input) and POL (a polarity bit, setting it inverts the input before applying it to the AND gate) . The effect of setting these bits is shown in Figure 20. The inversion gate shown is an XOR gate that produces the following truth table:

The last two entries in the truth table show that with the Invert (POL) bit set, the XOR output is always the opposite of the input.

Similarly, the ignore gate shown is an OR gate, producing the following truth table:

Here you can see that once that mk bit is set, the OR output is always 1 no matter what the input is, so ignore it. Figure 21 is a detailed diagram of the 21 inputs and registers required for programming. Shown is for function A of PLB1 only, but function B and all functions in the other eight PLBs are programmed in exactly the same way. The enable register allows the user to use function A and/or function B. The outputs of functions A and/or B are input to a programmable delay block (PDB), where the delay can be programmed on the rising and falling edges of the input (see the Programmable Delay Block section). The output of this PDB block can be programmed to toggle before any PDO pins are asserted.

The control bits for these macrocells are stored in local latches, which are loaded at power-up. These latches can also be updated via the serial interface. The registers that contain the macrocell control bits and the function of each bit are defined in the following table.

Figure 21 highlights all 21 inputs for a given function and the registers/bits that need to be set in order to properly adjust the 21 inputs. The figure shows only Function A of Programmable Logic Block 1 (PLB1), but all functions are programmed the same way.

For example, if the user wishes to assert PLBOUT for about 200 ms after all supplies are within specification (PLBOUT can be used to drive the LDO's enable pin), then power-fail detectors VBn, VH, and VPn are required to control this function. Functional programming such as:

1. The ignore bits of all other inputs (GPIs, PDBs, WDI) in the relevant P1xxxIMK registers are set to 1. So the function of these inputs and the input to the gate will be 1 regardless of their state.

2. Since the SFD asserts a 1 under fault conditions and a 0 when the power supply is within the allowable range, the SFD output needs to be inverted before being applied to the function. Therefore, the relevant bits in the P1SFDPOL register are set (see Table 38).

3. The function is enabled (bit 1 of register P1EN see Table 36).

4. Set the rise time of 200 ms (see the register diagram for the register P1PDBTIM).

Programmable Delay Block

Each output of the PLBA is fed into an individual Programmable Delay Block (PDB). A PDB enables the user to add a delay to a logic block output before being applied to a PDO or one of the other PLBs (the output of a PLB can be an input to any other PLB, but not itself). The PDB operation is similar to that of the fault filter (discussed in the SFD section). However, there is an important difference between these two functions. The delay on the falling edge of the PDB input can be programmed independently of the rising edge. This allows the user to program the pulse length output from the PDB. So, for example, the pulse width from the watchdog fault detector can be adjusted, or the user can ensure that the supply monitored by an sfd is within its UV/OV range for a programmed period of time before asserting the PDO. A delay of 0 ms to 500 ms can be programmed in the PnPDBTIM register. Every four bits are used to program rising and falling edges.

After programming, the PDB works as follows. If the user programs a delay on a rising edge (for example, 200ms), the PDB looks for a rising edge on the input. Once it sees the edge, it starts the timer. If the input is still high and the timer reaches 200ms, the PDB outputs a rising edge immediately. If the input goes low before the timer reaches 200 ms, the PDB has no output edge and the timer resets. Since there is separate control over the falling edge, if no delay is programmed on the falling edge, the delay defaults to 0 ms and a falling edge on the input will appear immediately on the output. If the falling edge delay is programmed, the PDB works exactly the opposite of the rising edge. Likewise, if a delay of 200 ms is programmed on the falling edge, the PDB looks for a falling edge on the input. Once it sees the edge, it starts the timer. If the input remains low and the timer reaches 200 ms, the output transitions from high to low. A valid rising edge must be present at the output to activate the falling edge delay. The function of the PDB is shown in Figure 22.

In addition to additional timing flexibility, programmable delays provide a coarse form of filtering. Much the same way that glitch filters work, the input must be high (or low) for a programmed period of time before it can be seen on the output. Transients shorter than the programmed timeout will not appear on the output. The bitmap for the registers that control the rising and falling edges is shown in Table 38.

output

Programmable driver output

The ADM1060 has nine programmable driver outputs (PDOs). These are the logical outputs of the device. Each PDO is usually controlled by one PDB. Thus, the pdo can be set to assert when conditions on the PDB are met, e.g. sfd is in tolerance, level on GPI is correct, watchdog timer has not timed out, etc. PDOs can be used for many functions; for example, to provide a well-powered signal when all SFDs are within tolerance, and to provide a reset generator output if one of the SFDs is out of spec (it can be used as a DSP or other microprocessor's status signal), or provide an enable signal for the LDO on the power supply that the ADM1060 is monitoring.

There are a number of pull-up options on the PDO that allow the user to program the output level.

The outputs can be programmed as:

• Open (allows user to connect external pull-up resistors)

• Open drain, weak pull-up to V

• Push and pull to V

• Open drain with weak pull-up capability to VPn

• Push and Pull to VPn

• Internal charge pump high drive (12 V)

The last option is only available on PDO1-4. This allows the user to directly drive the gate of an N-channel FET in the power path. The desired pull-up is selected by appropriate programming of Bits 0 to 3 in PnPDOCFG (see Table 40).

The data driving each pdo can come from one of three inputs. These inputs are in the PnPDOCFG register. The input is:

• (delayed) output of the associated PLB (enabled by setting bit CFG4 to 1)

• Data driven directly through the SMBus interface (enabled by setting bit CFG5 to 1). When set in this mode, the data from the PDB is disabled and the data on the PDO is the data on the CFG4. Therefore, the PDO can be software controlled to initiate software power up/down.

• On-chip clock (enabled by setting bit CFG6 to 1). The 100 kHz clock can be used to clock external devices such as LEDs.

See the register map in Table 40 for more details on these data patterns.

The default setting for each PDO is to be pulled low by a weak (20 kΩ) pull-down resistor. This is also the setting when the PDO is powered up until the registers are loaded and the programming condition is locked. The output is actively pulled low as soon as 1v or more is seen on any VPn or VH. The output is high impedance until there is a 1V supply on the chip. This provides a known condition for the pdo during power up. The internal pull-down can be overdriven by tying an external pull-up of the appropriate value from the PDO pin to the desired pull-up voltage. The 20 kV resistance must be considered when calculating the proper value. For example, if PDOn needs to be pulled up to 3.3v, and 5v can be used as an external power supply, the pull-up resistor value is given by:

therefore,

The register list and bitmap for pdo are shown in Table 39 and Table 40.

status/failure

Fault/Status Reporting on the ADM1060

As mentioned earlier, any number of PDOs can be programmed to assert on a set of pre-programmed conditions. These conditions could be failures on SFDs, state changes on GPIs, watchdog detector timeouts, etc. Due to the flexibility of the ADM1060 and the choice of combinations available, the PDO's assertion does not tell the user what caused it to assert (unless it is programmed to use only one input assertion).

To enable the user to debug the cause of the PDO assertion, several registers on the ADM1060 provide status and fault information for the various individual functions overseen by the device.

status register

A number of status registers indicate the logic state of all functions controlled by the ADM1060. These logic states include the output of the UV and OV comparators of each of the seven sfds, the logic output of the sfd itself, the logic state of the gpi, the error condition on the WDI, and the logic state of each of the nine pdos. The contents of these registers are read-only and can be read through the SMBus interface at any time. The register and bitmap of these status registers are described in the table below.

fault register

The ADM1060 also provides fault reporting. For example, if a failure occurs that causes the PDO to change its state, the user can determine which function actually failed. This is accomplished by providing a "fault plane" consisting of two registers, LATF1 and LATF2, that the system controller can read out of the ADM1060 via SMBus. As shown in Table 41, each bit in both registers (with one important exception, see below) is assigned to one input of the device.

Each bit represents the logic state of its distribution function, i, eg, the logic output of sfd and WDI, and the logic level on the GPI input.

The important exception is the MSB of the LATF1 register. This is the ANYFLT bit. This bit goes high if one of the other bits in the two registers fails. A fault is defined as a change in polarity since the last read of the fault register. Once ANYFLT goes high, the contents of both registers are latched, preventing more than one of the other bits from changing polarity until the contents of the registers are read. Therefore, the first fault input can be determined.

The order in which registers are read is determined by whatever. As long as ANYFLT remains 0, only LATF1 is read. There are two reasons for this. First, ANYFLT=0 means that no fault has occurred, therefore, the contents of LATF2 do not need to be read. The second and more important reason is that reading register LATF2 actually resets the ANYFLT bit to 0. So if a fault occurs on the SFD after LATF1 is read but before LATF2 is read, ANYFLT will change to 1 indicating that a fault has occurred, but will reset to 0 after LATF2 is read, thus erasing the fault log. In conclusion, LATF2 should only be read if ANYFLT=1. Reading the registers in this sequence ensures that the contents are not reset until the fault is logged via the SMBus, thus ensuring that the monitoring processor or CPLD knows which function monitored by the ADM1060 caused the fault. The fault function is determined by comparing the contents of the fault plane (that is, the contents of the two registers) with the previously read value and determining which bit has changed polarity.

The function of the fault plane is best illustrated with an example. For example, taking VP1 as an example, the input power is 5.0v. Set a UV/OV window of 4.5v to 5.5v on VP1. Each time the contents of LATF1 and LATF2 are read, power is ramped in and out of this window. The recorded values are as follows:

1. VP1:LATF1=LATF2=00000000 at 5 V. This is to be expected. The power supply is within tolerance and the SFD output is 0, so there is no fault.

2. VP1 at 4.2V: LATF1=10001000, LATF2=00000000. The SFD output has changed state to 1, so ANYFLT will go high.

3. VP1 at 5.0V: LATF1=10000000, LATF2=00000000. The SFD output has changed state to 0, so ANYFLT goes high again.

4. VP1 at 5.8 V: LATF1=10001000, LATF2=00000000. The SFD output changes state from 0 to 1 again, so ANYFLT goes high.

5.4. VP1 at 2 V: LATF1=10000000, LATF2=00000000. At first glance this seems incorrect as the SFD output should be 1 (4.2v is an undervoltage fault). However, during the gradual decrease from 5.8V to 4.2V, the power supply enters the UV/OV window, the SFD output changes from 1 to 0, ANYFLT is set high, and the register contents are locked. These values were read before being reset by reading LATF2.

Two mask registers are also provided, allowing the user to ignore errors on a given function. The bits of the error mask register are mapped in the same way as the bits of the fault register, but the ANYFLT bit cannot be masked. Setting a 1 in the error mask register will cause the equivalent bit in the error register to always remain 0, regardless of whether the function has an error or not.

programming

Download configuration at boot

The configuration of the ADM1060—UV/overvoltage thresholds, fault filter timeouts, PLB combinations, PDO pullups, etc.—is determined by the contents of the RAM. The RAM consists of local latches that set the configuration. These latches are double buffered and actually consist of two identical latches (Latch A and Latch B). The update of the double-buffered latch first updates Latch A, then Latch B. The advantages of this architecture are described below. These latches are volatile memory and lose their contents when power is removed. Therefore, upon power-up, the configuration in RAM must be restored. This is achieved by downloading the contents of the EEPROM (non-volatile memory) to a local latch. This download takes place in several steps.

1. When the device is not powered, the pdo is high impedance.

2. As soon as 1v appears on any input connected to the V arbiter (VH or VPn), pdo is pulled (weakly ground) to GND.

3. Once the supply voltage is higher than the device's undervoltage lockout (UVLO is 2.5v), the EEPROM starts downloading to RAM.

4. The EEPROM downloads its contents to all latches As.

5. Once the contents of the EEPROM are completely downloaded, the device controller outputs a control pulse that enables all latches As to be downloaded to all latches Bs, thus completing the configuration download. Attempting to communicate with the device before this download is complete will result in a NACK from the ADM1060.

Update configuration

Once the device is powered up and all configuration settings are loaded from the EEPROM into the RAM registers, the user may wish to change the functional configuration on the ADM1060; for example, changing the UV or OV limits of the SFD, the fault output of the SFD, the timeout of the watchdog detector, where The rise delay of a pdo is turned on.

The ADM1060 offers many options that allow the user to update the configuration in different ways through the SMBus interface. All these options are controlled in register UPDCFG. The options are:

1. Update the configuration in real time. The user writes to RAM via SMBus and the configuration is updated immediately.

2. Update A latches "offline", then update all B latches at the same time. Using this method, the configuration of the ADM1060 remains unchanged and continues to operate in the original setting until an instruction to update the B latch is issued.

3. Change the EEPROM register content offline, and then download the modified EEPROM content to the RAM register. Again, using this method, the configuration of the ADM1060 remains unchanged and continues to operate in the original settings until a change is commanded.

Instructions downloaded from the EEPROM in Option 3 above are also a useful way to restore the original EEPROM contents if modifications to the configuration are not satisfactory and the user wishes to return the ADM1060 to a known mode of operation.

This type of operation is possible due to the topology of the ADM1060. Local (volatile) registers or RAM are double buffered latches. Setting Bit 0 of the UPDCFG register to 1 will keep the double-buffered latch on at all times. If bit 0 is set to 0, when a RAM write occurs on the SMBus, only the first side of the double-buffered latch is written. Then, the user must write 1 to bit 1 of the UPDCFG register. This generates a pulse to update all second latches simultaneously. EPROM writing works similarly.

The last bit in this register is used to enable EEPROM page erase. If this bit is set high, the contents of the EEPROM page can all be set to 0. If low, the page contents cannot be erased, even if the command code for page erase has been programmed in the SMBus.

The bitmap of register UPDCFG is shown in Table 56. Figure 24 shows a flow diagram for the download and subsequent configuration update at power up.

internal register

The ADM1060 contains a large number of data registers. A brief description of the main registers follows. More detailed instructions are provided in the relevant sections of this data sheet.

address pointer register. This register contains the address to select one of the other internal registers. When writing to the ADM1060, the first byte of data is always a register address, which is written to the address pointer register.

configuration register. These registers provide control and configuration for various operating parameters of the ADM1060.

Polarity register. These registers define the input polarity to the PLBA.

mask register. These registers allow masking of individual inputs to the PLBA and masking of faults in the fault reporting registers.

Electrically Erasable Programmable Read-Only Memory

The ADM1060 has 512 bytes of nonvolatile, electrically erasable programmable read-only memory (EEPROM) from register addresses 0xF800 to 0xF9FF. Unlike data in volatile registers, this can be used to permanently store data that will not be lost if the ADM1060 is powered down. Although called read-only memory, EEPROM can be written to (and read from) over the serial bus in exactly the same way as other registers. The only major difference between EEPROM and other registers is

1. The EEPROM location must be empty to write. If it contains data, it must be deleted first.

2. Writing to EEPROM is slower than writing to RAM.

3. Writes to EEPROM should be limited as its write/cycle life is typically 10000 write operations due to the usual wear-out mechanism of EEPROM.

The EEPROM is divided into 16 (0 to 15) pages of 32 bytes each. Pages 0 through 6, starting at address 0xF800, hold configuration data for applications (PLB, SFD, GPIs, WDI, PDO, etc.) on the ADM1060. These EEPROM addresses are the same as RAM register addresses, prefixed with 0xF8. Keep page 7. Pages 8 to 15 are for customer use. Data can be downloaded from EEPROM to RAM in two ways:

1. When powered on, pages 0 to 6 will be downloaded.

2. Setting bit 2 of the UPDCFG register (0x90) performs user download pages 0 to 6.

serial bus interface

Control of the ADM1060 is performed through the Serial System Management Bus (SMBus). Under the control of the master device, the ADM1060 is connected to this bus as a slave device. After power up, the ADM1060 takes about 2 ms to download from its EEPROM. Therefore, access to the ADM1060 will be restricted until the download is complete.

Identifying the ADM1060 on SMBus

The ADM1060 has a 7-bit serial bus slave address. When the device is powered up, it will use the default serial bus address. The five msbs of the address are set to 10101, and the two lsbs are determined by the logic states of pins A1 and A0. This allows four ADM1060s to be connected to one SMB. The device also has several identification registers (read only) that can be read across the SMBus. these are:

General SMBus Timing

Figure 25 and Figure 26 show timing diagrams for typical read and write operations using SMBus. The SMBus specification defines specific conditions for different types of read and write operations, which will be discussed later. The general SMBus protocol operates as follows:

1. The host initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA, while the serial clock line SCL remains high. This means that the data flow will follow. All slave peripherals connected to the serial bus respond to the Start condition and shift in the next 8 bits, including the 7-bit slave address (MSB first) and an R/W bit, the latter Determines the direction of data transfer, i, e. Whether the data is written or read from the device (0=write, 1=read).

The peripheral whose address corresponds to the sending address responds by pulling the data line low during the low cycle before the ninth clock pulse (called the acknowledge bit) and holding it low during the high cycle of that clock pulse. All other devices on the bus are now idle while the selected device is waiting to read or write data from it. If the R/W bit is 0, the master will write to the slave. If the R/W bit is 1, the master will read from the slave.

2. The data is sent in the sequence of 9 clock pulses through the serial bus, and the 8-bit data is followed by the confirmation bit of the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high can be interpreted as a stop signal.

If the operation is a write operation, the first data byte after the slave address is the command byte. This tells the slave what to do next. It can be an instruction like telling the slave to expect a block write, or it can just tell the slave the address of a register to which subsequent data is to be written.

Since data can only flow in one direction as defined by the R/W bits, it is not possible to send commands to the slave device during a read operation. Before a read operation, a write operation may first need to be performed to tell the slave what kind of read operation and/or the address to read the data from.

3. A stop condition is established when all data bytes are read or written. In write mode, the master will assert the stop condition by pulling the data line high during 10 clock pulses. In read mode, the master will release the SDA line during the low period before the ninth clock pulse, but the slave will not pull it low. This is called non-recognition. The master will then assert the stop condition by taking the data line low for the low period before the 10 clock pulses and then high during the 10 clock pulses.

SMBus protocol for RAM and EEPROM

The ADM1060 contains volatile registers (RAM) and nonvolatile EEPROM. User RAM occupies address locations from 0x00 to 0xDF, while EEPROM occupies addresses from 0xF800 to 0xF9FF.

Data can be written to and read from RAM and EEPROM as a single data byte.

Data can only be written to unprogrammed EEPROM locations. To write new data to a programmed location, it first needs to be erased. EEPROM erasing cannot be done at the byte level; the EEPROM is arranged in 16 pages of 32 bytes and the entire page must be erased.

Page Erase is enabled by setting Bit 3 to 1 in register UPDCFG (Address 0x90). If this option is not set, page erase is not possible even if the command byte (0xFE) has been programmed on the SMBus.

write operation

The SMBus specification defines several protocols for different types of read and write operations. Those used in the ADM1060 are discussed below. The following abbreviations are used in the chart:

The ADM1060 uses the following SMBus write protocols:

send bytes

In this operation, the master sends a single command byte to the slave as follows:

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave asserts an ACK on SDA.

4. The host sends the command code.

5. Slave asserts ACK on SDA.

6. The primary server asserts a stop condition on SDA and the transaction ends.

In the ADM1060, the send bytes protocol serves two purposes:

1. Write the register address to RAM for subsequent single-byte reads from the same address or block read, or write from that address. As shown in Figure 28.

2. Erase one page of EEPROM memory. EEPROM memory can only be written to if it is not programmed. Before writing to one or more programmed EEPROM memory locations, one or more pages containing those locations must be erased. Erase EEPROM memory by writing a command byte.

The master sends a command code that tells the slave to delete the page. The ADM1060 command code for page erase is 0xFE (1111110 binary). Note that in order to page erase, the page address must be given in the previous write transaction (see Write Bytes below). Additionally, Bit 3 in register UPDCFG (Address 0x90) must be set to 1.

Once the ADM1060 receives the command byte, the page erase begins. The master device can send a stop command immediately after sending the command byte. Page erase takes about 20ms. If the ADM1060 is accessed before the erase is complete, it will respond without confirmation.

write byte/word

In this operation, the master device sends a command byte and one or two data bytes to the slave device as follows:

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave asserts an ACK on SDA.

4. The host sends the command code.

5. Slave asserts ACK on SDA.

6. The host sends a data byte.

7. Slave asserts ACK on SDA.

8. The host sends a data byte (or can assert stop at this point).

9. Slave asserts ACK on SDA.

10. The master asserts a stop condition on SDA to end the transaction.

In the ADM1060, the write byte/word protocol serves three purposes:

1. Write a single byte of data to RAM. In this case, the command bytes are RAM addresses from 0x00 to 0xDF, and the (only) data bytes are the actual data. As shown in Figure 30.

2. Set the 2-byte EEPROM address for subsequent read, write, block read, block write, or page erase. In this case, the command byte is the upper byte of the EEPROM address from 0xF8 to 0xF9. The (unique) data byte is the low-order byte of the EEPROM address. As shown in Figure 31.

Note that for page erase, since pages consist of 32 bytes, only the three msbs of the low address byte are significant. The low-order 5 bits of the low-order byte of the EEPROM address only specify the address within the page and are ignored during the erase operation.

3. Write a single byte of data to the EEPROM. In this case, the command bytes are the high-order bytes 0xF8 to 0xF9 of the EEPROM address. The first data byte is the low-order byte of the EEPROM address, and the second data byte is the actual data. As shown in Figure 32.

block write

In this operation, the master device writes a block of data to the slave device. The starting address for block writing had to be set previously. In the case of the ADM1060, this is done with a send byte operation to set the RAM address, or a write byte/word operation to set the EEPROM address.

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave asserts an ACK on SDA.

4. The master sends a command code telling the slave to expect a block write. The ADM1060 command code for block writes is 0xFC (1111100 binary).

5. Slave asserts ACK on SDA.

6. The master sends a data byte that tells the slave how many data bytes will be sent. The SMBus specification allows up to 32 data bytes to be sent in a block write.

7. Slave asserts ACK on SDA. 8. The host sends N data bytes.

9. Slave asserts ACK on SDA after each data byte.

10. The master asserts a stop condition on SDA to end the transaction.

Unlike some EEPROM devices that limit block writes to page boundaries, when performing block writes to EEPROM, there are no restrictions on the starting address, except:

1. There must be at least N locations from the start address to the highest EEPROM address (0xF9FF) to avoid writing invalid addresses.

2. If the address crosses a page boundary, both pages must be cleared before programming.

Note that the ADM1060 has a clock extension function for writing to EEPROM. It takes about 250 microseconds to program an EEPROM byte, which will limit repeated or block write operations to the SMBus clock. The ADM1060 pulls SCL low and stretches the clock pulse when no more data can be received.

read operation

The ADM1060 uses the following SMBus read protocols:

receive bytes

In this operation, the master device receives a single byte from the slave device as follows:

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the read bit (high).

3. The addressed slave asserts an ACK on SDA.

4. The host receives a data byte.

5. The captain did not confirm on SDA.

6. The primary server asserts a stop condition on SDA and the transaction ends.

In the ADM1060, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address was previously set by a send byte or write byte/word operation. As shown in Figure 34.

block read

In this operation, the master device reads blocks of data from the slave device. The starting address for block reads had to be set previously. In the case of the ADM1060, this is done with a send byte operation to set the RAM address, or a write byte/word operation to set the EEPROM address. The block read operation itself consists of a send byte operation, which sends a block read command to the slave, followed by a repeated start, and a read operation that reads multiple data bytes, as follows:

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave asserts an ACK on SDA.

4. The master sends a command code telling the slave to expect a block read. The ADM1060 command code for block reads is 0xFD (1111101 binary).

5. Slave asserts ACK on SDA.

6. The host asserts the Repeated Start condition on SDA.

7. The master sends the 7-bit slave address followed by the read bit (high).

8. Slave asserts ACK on SDA.

9. The ADM1060 sends a byte count data bytes to tell the host how many data bytes are needed. The ADM1060 will always return 32 data bytes (0x20), which is the maximum allowed by the SMBus 1.1 specification.

10. The captain asserts ACK on SDA.

11. The host receives 32 data bytes.

12. The master asserts an ACK on SDA after each data byte.

13. The master asserts a stop condition on SDA to end the transaction.

Error correction

The ADM1060 provides the option to issue a PEC (Packet Error Correction) byte after a write to RAM, write to EEPROM, block write to RAM/EEPROM, or block read RAM/EEPROM. This enables the user to verify that the data received or sent by the ADM1060 is correct. The PEC byte is an optional byte sent after the last data byte is written or read from the ADM1060. The agreement is as follows:

1. The ADM1060 sends a PEC byte to the host. If the PEC bytes are incorrect, the host should check the PEC bytes and issue another read block.

2. A NACK is generated after the PEC byte to indicate the end of the read.

Note: PEC bytes are calculated using CRC-8. Frame Check Sequence (FCS) CRC-8 compliant polynomial:

See the SMBus1.1 specification for more information. Figure 36 shows an example of reading a block with optional PEC bytes.

Dimensions

[1] At least one Vpn must be ≥3.0 V if used as a power supply. If used as a power supply, VH must be ≥4.5 V.

[2] Specifications are not production tested, but are supported by characterization data at initial product release.

[3] % threshold accuracy can only be achieved on parts pre-programmed by analog equipment. For more information, please contact.

[4] The logic inputs will accept input high voltages up to 5.5 V, even if the device is operating at a supply voltage lower than 5 V.

[V] Durability qualified to 100,000 cycles per JEDEC Standard 22 Method A117 and measured at -40°C, +25°C and +85°C.

[VI] For EEPROM programming and erasing, the minimum V=3.0V requires 0°C to +85°C, and the minimum V=4.5V requires -40°C to 0°C.

[7] Retention life equivalent at junction temperature (T) = 55°C per JEDEC Standard 22 Method A117.

[VIII] Test timing specifications at logic levels V=0.8v (falling edge) and V=2.0v (rising edge).

[9] Contact factory for evaluation board.