The ISL6740 , ISL6741 series of adjustable frequency, low power, pulse width modulation (PWM) voltage mode (ISL6740) current mode (ISL6741) controllers are designed for full-bridge half-bridge power conversion applications ranging from bridging and push-pull configurations. These controllers provide a very flexible oscillator with precise control of frequency, duty cycle and dead time. This advanced BiCMOS design features low operating current, adjustable switching frequency up to 1MHz, adjustable soft-start, internal and external overtemperature protection, fault notification and bidirectional synchronization signal, allowing the oscillator to be locked to a parallel cell or external clock for noise-sensitive applications .

1. Add "-T*" suffix to tape and reel. See TB347 reel specifications for details.

2. These Intersil lead-free plastic packaged products feature a special lead-free material set, molding compound/mold connection material, and 100% matte tinplate plus annealing (e3 finish, i.e. RoHS compliant, SnPb and lead-free soldering compatible operate). Intersil lead-free products are MSL classified at lead-free peak reflow temperatures that meet or exceed IPC/JEDEC J STD-020 lead-free requirements.

3. For the Moisture Sensitivity Level (MSL), see the Device Information\ISL6740 and ISL6741 pages. See techbrief TB363 for more information on MSL.

feature

Precise duty cycle and dead time control

95µA startup current

Adjustable Delay Over Current Shutdown and Restart (ISL6740)

Adjustable short-circuit shutdown and restart

Adjustable oscillator frequency up to 2 MHz

two-way synchronization

inhibit signal

Internal overheat protection

Use a thermistor or sensor

Adjustable soft start

Adjustable Input Undervoltage Lockout

fault signal

Line, Load and Temperature

Lead-free available (RoHS compliant)

application

Telecom and Datacom Power Supplies

Wireless base station power supply

file server power

Industrial Power Systems

DC Transformers and Bus Regulators

Absolute Maximum Ratings (Note 6) Thermal Information

Supply voltage, VDD. Ground -0.3V to +20.0V

OUTA, OUTB, signal pins. Ground -0.3V to VREF

VREF. Ground -0.3V to 6.0V

Peak gate current. 0.5A

Electrostatic discharge classification

Human body model (per MIL-STD-883 method 3015.7). 1500 volts

Charger model (according to EOS/ESD DS5.3, 4/14/93). 1000 volts

operating conditions

temperature range

ISL6740Ix. -40°C to +105°C

ISL6741Ix. -40°C to +105°C

Supply voltage range (typical). 9 VDC - 16 VDC

Thermal Resistance (Typical) θJA (Celsius/Watt) θJC (Celsius/Watt)

16 lead SOIC (Note 4, 5). 74 33

16 lead TSSOP (Note 4, 5). 30/98

maximum junction temperature. -55°C to +150°C

Maximum storage temperature range. -65°C to +150°C

Lead-free reflow profile.

NOTE: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to these conditions may adversely affect the product

reliability, resulting in failures not covered under warranty.

notes:

4. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air. See Technical Bulletin TB379.

5. For θJC, the "case temp" position is taken at the top center of the package.

6. All voltages are related to ground.

Operating conditions recommended by electrical codes unless otherwise stated. Refer to the "Functional Block Diagrams" above for typical application schematics on pages 2 and 3 and pages 4 through 6. 9V

Operating conditions recommended by electrical codes unless otherwise stated. Refer to the "Functional Block Diagrams" above for typical application schematics on pages 2 and 3 and pages 4 through 6. 9V

notes:

7. Ensure compliance with data sheet limits by one or more methods: production testing, characterization, and/or design.

8. The sync pulse width is greater than this value or CT discharge time.

9. This is the maximum duty cycle achievable using the specified values for RTC, RTD and CT. Use other values for these components to obtain larger or smaller maximum duty cycles. See equations 2 to 4.

Pin Description

VDD—VDD is the power supply connection for the integrated circuit. To optimize noise immunity, bypass VDD to GND with ceramic capacitors as close as possible to the VDD and GND pins. The total supply current IDD depends on the load applied to the outputs OUTA and OUTB. The total IDD current is the quiescent current and the average output current. Knowing the operating frequency, fSW, and the output load capacitance, the charge per output, Q, the average output current can be calculated by the formula: SYNC - Bidirectional Synchronization Signal for Coordinated Switching Frequency of Multiple Units. Synchronization may be accomplished by connecting a synchronization signal to each unit or using an external master clock signal. Oscillator timing regardless of the synchronization method used. with maximum oscillator frequency control. Oscillator frequencies above 900 kHz are not recommended for self-synchronization. For higher switching frequencies clocks with pulse widths less than half the oscillator period must be used. RTC - This is the oscillator timing capacitor charging current control pin. A resistor is connected from this pin to ground. This current through the resistor determines the charging current. The charging current is nominally twice the current. The PWM maximum on time is determined by the timing capacitor charge duration. RTD - This is the oscillator timing capacitor discharge current control pin. A resistor is connected from this pin to ground. The current flowing through the resistor determines the magnitude of the discharge current. The discharge current is nominally 50 times this current. The PWM dead time is determined by the timing capacitor discharge duration. The CT-Oscillator timing capacitor is connected between this pin and ground. VERROR—Inverting input of the PWM comparator. A voltage is incorrectly applied to this pin to control the duty cycle. An increased signal level increases the duty cycle. Nodes may be driven with external error amplifiers or optocouplers. ISL6740, ISL6741 have built-in soft-start function. Soft-start is implemented as a clamp for erroneous voltage inputs. OTS - Non-inverting input comparator for overtemperature shutdown. The signal input at this pin is related to the internal threshold of VREF/2. If the voltage on this pin exceeds the threshold, the fault signal is asserted and the output is disabled until the condition is cleared. There is a nominal 25µA switched current source for hysteresis. The amount of hysteresis can be changed by changing the signal into this pin. OTS can be used to monitor parameters other than temperature, such as voltage. A monitor required for the upper limit of any signal can use an OTS comparator. Fault - Whenever an output is made, the fault signal is asserted high and OUTA and OUTB are disabled. On over temperature fault, input UV fault, VREF UV fault or over current (ISL6740) or short circuit shutdown fault. The faulty controller area network is used to disable the synchronous rectifier when the output is disabled.

The fault is a tri-state output during a soft-start cycle. Adding a pull-up or pull-down resistor to VREF to ground determines the fault state during soft-start. This feature allows the designer to use a fault signal to enable or disable the output synchronous rectifier during soft-start. UV - Undervoltage Monitor Input Pin. Resistor divider input source voltage and GND set the undervoltage lockout threshold. Compare this signal to an internal 1.00V reference to detect undervoltage or inhibit conditions. This is the input to the current sense comparator. The IC has a PWM comparator (ISL6741) for peak current mode control and an overcurrent protection comparator. This overcurrent comparator threshold is set to 0.600V nominal. At the end of each switching cycle, the CS pin is shorted to ground. Input resistors may be required depending on the impedance of the current sensing source, due to the internal clock and external power switches. This delay may allow for overlap so that the current signal is still active. If the current sense source is low impedance, it will result in increased power loss. ISL6740 - Exceeding the overcurrent threshold will initiate a delayed shutdown sequence. Once an overcurrent condition is detected, the soft-start charging current source is disabled. This soft-start capacitor begins to discharge the supply through 25µA, and if it discharges below 4.25V (sustained overcurrent threshold), a shutdown condition occurs and the OUTA and OUTB outputs are forced low. The soft-start cycle begins when the voltage reaches 0.27V (reset threshold) during soft-start. An overcurrent condition must be reset by the delayed shutdown control. If the overcurrent condition ceases, no shutdown has occurred after the shutdown threshold has been reached. The SS charging current is re-enabled and the soft-start voltage is allowed to resume.

The ISL6741-ISL6741 current mode controller does not shut down due to overcurrent conditions. A pulse-in-peak current-mode control limit current-limiting characteristic of the output current to an acceptable level GND - the reference and power ground for all functions. A low impedance layout is necessary due to high peak currents and high frequency operation. Traces are strongly recommended for ground planes and shorts. OUTA and OUTB—alternating half-cycle output stages. Each output features 0.5A peak current for driving logic level power MOSFETs or MOSFET drivers. Each output provides very low overshoot and overshoot impedance. VREF-5.00V reference voltage output. +1%/-2% tolerance over wire, load and operating temperature. Bypass with a 0.047µF to 2.2µF ceramic capacitor to ground. Capacitor ranges beyond this can cause oscillations. SS - Connect a soft-start timing capacitor to this pin and GND that controls the duration of the soft-start. The value of the capacitor is determined at startup, controls the overcurrent shutdown delay (ISL6740), and the restart cycle for overcurrent and short-circuit faults. SCSET - Sets the duty cycle threshold circuit condition corresponding to a short circuit. A resistor divider between RTC and GND or RTD and ground, or a voltage between 0V and 2V can be used to adjust the SCSET threshold. If an RTC or RTD is used, impedance to ground affects oscillator timing and components should be considered when determining oscillator timing. Connecting SCSET to GND will disable short-circuit shutdown

Function description

feature

The ISL6740 and ISL6741 PWMs are ideal for low-cost bridge and push-pull topologies for applications requiring precise duty cycle and dead time control. With many protection and control functions, a highly flexible design with minimal external components is possible. Among the many features are current mode control (ISL6741), adjustable soft-start, overcurrent protection, thermal protection, bidirectional synchronization, fault indication and adjustable frequency. Oscillators ISL6740 and ISL6741 have a programmable frequency range of 2 MHz with programmable resistors and capacitors. The oscillator frequency is set using three timing elements, RTC, RTD and CT. The switching period can be thought of as a timed sum of capacitor charge and discharge durations. The charging time is determined by RTC and CT. Discharge time determined by RTD and CT

where tC and tD are the charge and discharge times, respectively, tSW is the free-running period of the oscillator, and f is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual time will be slightly longer than the calculated time due to the internal propagation delay of 10ns/conversion. This delay directly affects the switching duration, but also causes the timing capacitor peak-to-valley to overshoot the voltage threshold, effectively increasing the voltage across the peak-to-peak voltage timing capacitor. Also, if the charge is low if the discharge current is used, the error will increase because of the input impedance of the CT pin. The maximum duty cycle D and the percentage of dead time DT can be calculated as:

A synchronous oscillator can be implemented together with a synchronous pin applied to the synchronous pin or by connecting multiple ICs. If an external master clock signal is used, the oscillator should run at a higher frequency than the desired synchronization frequency. The pulse width of the external master clock signal should be greater than 20ns. Synchronization During the first process, the circuit does not respond to external signals \60% of the oscillator switching period. Self-synchronization is not recommended for oscillator frequencies above 900 kHz. For higher switching frequencies, the width of the external clock with pulses must be less than half the oscillator period. The sync input is edge-triggered and its duration does not affect oscillator operation. However, the dead time is affected by the synchronization frequency. A higher frequency signal input applied to synchronization will shorten the dead time. The shortened dead time is a result of premature capacitor charging cycles terminated by an external sync pulse. Therefore, when the timing discharge cycle begins, the capacitor is not fully charged. When an external master clock is used, or if the devices have different operating frequencies in parallel.

soft start operation

ISL6740, ISL6741 have the use of external capacitors and internal current source. Soft start reduces stress and inrush current during startup. During startup, the soft-start circuit clamps the error voltage indirect input (VERROR pin) to a value equal to the soft-start value. The soft-start clamp does not actually clamp the wrong voltage input as is the case in many implementations. More precisely the PWM comparator has two inverting inputs, keeping the voltage under control. The output pulse width increases as the soft-start capacitor increases and the voltage rises. This increases the duty cycle from zero to adjust the pulse width period during soft start. When the soft-start voltage exceeds the error voltage, the soft-start is completed. Soft-start occurs during start-up, followed by recovery from fault conditions or overcurrent/short circuit shutdown. The soft-start voltage is limited to 4.5V. The fault signal output loops high impedance during soft start. A pull-up resistor to VREF or a pull-down resistor to ground should be added during soft-start to achieve the desired fault state.

gate drive

The ISL6740 and ISL6741 are capable of sourcing and sinking 0.5A peak current, but are primarily used in conjunction with a MOSFET driver due to the 5V drive level. To limit the peak current through the IC, an external resistor can be placed between the IC's totem pole output (OUTA or OUTB) and the gate of the MOSFET. This small series resistor also damps the input by parasitic inductance in the circuit board and FET traces Capacitor. Undervoltage monitor and inhibit UV input for input source undervoltage lockout and disable function. Shutdown fault occurs if node voltage falls below 1.00V a UV. This may be caused by low supply voltage or through an intentionally grounded pin, to disable the output. There is a nominal 10µA switched current source used to create the hysteresis. The current source activates the fault only during UV/Inhibit; otherwise, it is inactive and does not affect the node voltage. The magnitude of the hysteresis is divided by the external resistor Voltage divider impedance. If the resistor divider impedance results in too little hysteresis, a series resistor between the UV pin and the voltage divider can be used to add hysteresis. When the UV/Suppression faults, the soft-start cycle begins to clear. Switch current source The resulting voltage lags and the external impedance is usually small as the input voltage is scaled down to the desired resistor divider ratio UV threshold level. A small capacitor placed between the UV may require the input and ground to filter noise

overcurrent operation

ISL6740 - Once the soft start cycle is complete. If an overcurrent condition is detected, the soft-start charging current source is disabled and the soft-start capacitor is allowed to discharge through the 15µA source. At the same time, a 50 μs retriggerable one-shot timer activates. After overcurrent, it remains active for 50μs and stops. If the soft-start capacitor discharges more than then 0.25V to 4.25V, the output is disabled and the fault signal is asserted. This state continues until the soft-start voltage reaches 270mV, at which point a new soft-start cycle is initiated. If the overcurrent state stops for at least 50μs before the soft-start and the voltage reaches 4.25V, the soft-start charging current returns to normal operation, allowing the soft-start voltage to recover. The duration of the OC off period can be increased by adding a resistor between VREF and SS. The resistor value must be large enough so that the specified minimum SS does not exceed the discharge current. Using a 422kΩ resistor, for example, will cause a small current to be injected into the SS, effectively reducing the discharge current. This will increase rest time by about 60%, nominally. An external pull-up resistor will also shorten the duration of SS, so its effect should be considered when choosing the value of the SS capacitor. The latch resistor between OCVREF and SS can also be turned off by using a lower value. If the SS node is not allowed to discharge below the SS reset threshold, the IC will not be able to recover from an overcurrent fault. The resistor value must be low enough that the maximum specified discharge current is sufficient to pull SS below 0.33V. For example, a 200kΩ resistor to prevent SS from discharging below ~0.4V. Also, an external pull-up resistor will reduce the SS duration, so its effect should be considered when choosing the value of the SS capacitor. ISL6741 - Overcurrent causes the pulse-by-pulse duty cycle reduction that occurs in any peak current mode controller. This results in a well-controlled drop in output voltage increasing the current beyond the overcurrent threshold. An overcurrent condition in the ISL6741 will not cause shutdown

short circuit operation

Short circuit conditions are defined as current limit and duty cycle reduction. The duty cycle of the degree reduction can be adjusted by the user using the SCSET input. A resistor divider between an RTD or RTC and ground to RCSET sets the threshold capacitor, CT, that is compared to the voltage on the timing. The resistive divider percentage corresponds to a fraction of the maximum duty cycle of the short circuit that may exist. A short circuit condition exists if the timing capacitor voltage does not exceed the threshold before the overcurrent pulse is detected. If 8, the shutdown and soft-start cycle will begin within 32 oscillator cycles of the short-circuit event. Connecting SCSET to GND will disable this feature. Since the current from the RTC and RTD determines the charging and discharging current of the timing capacitor, the SCSET divider must be included in the timing calculation. Usually the resistor between RTC and GND is connected by the two center nodes to the series resistor of SCSET. Alternatively, SCSET2V can be set with a voltage between 0V and 0V. This voltage is divided by 2 to determine the corresponding maximum duty cycle current limit activation during short circuit. For example, if the maximum duty cycle is 95% and 1V applied to SCSET, then the short circuit duty cycle is 50% of 95% or 47.5%.

fault condition

If VREF is below 4.65V (UV input), a fault will occur. When below 1.00V, thermal protection will be triggered, or if the OTS is faulty. When a fault is detected, the OUTA and OUTB outputs are disabled, the fault signal is asserted, and the soft-start capacitor is fast. When the fault condition clears and the soft-start voltage is below the reset threshold, the soft-start cycle begins. The fault signal loops in high impedance during soft start. An overcurrent condition that causes shutdown (ISL6740), or a short-circuit shutdown can also result in the assertion of the fault signal. The difference between the current fault and the fault described before is that the soft-start capacitor did not discharge very quickly. The start-up of a new soft-start cycle is delayed when the soft-start capacitor discharges at a rate of 15 μA. This enables the minimum average output current. Thermal protection provides two methods of over-temperature protection. This first method is an on-board temperature sensor, which protects with a lag of about 15°C if the junction temperature exceeds 145°C. The second method uses an internal comparator with a 2.5V reference (VREF/2). The comparator's non-inverting input is accessible through the OTS pin. A thermistor or thermal sensor located in or near the relevant area may be related to this input. A nominal 25µA switched current source is used to create hysteresis. The current source is active only during the OT fault; otherwise, it is inactive and does not affect the node voltage. The magnitude of the hysteresis is the external resistor divider impedance. Either a positive temperature coefficient (PTC) or a negative temperature