feature

Low power quad 16-bit DAC; 14-lead TSSOP on-chip 1.25 V/2.5 V, 5 ppm/°C reference; power down to 400 mA at 5 V and 200 mA at 3 V; 2.7 V to 5.5 V supply; guaranteed monotonicity by design; power-on reset to zero-scale or mid-scale; 3 power-down functions; hardware LDAC with LDAC override; CLR function to programmable code; SDO daisy-chain option; rail-to-rail run.

application

Process Control; Data Acquisition Systems; Portable Battery-Powered Instruments; Digital Gain and Offset Adjustment; Programmable Voltage and Current Sources; Programmable Attenuators.

General Instructions

The AD5666 is a low power, four-bit, 16-bit, buffered voltage-output DAC. The part operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design.

The AD5666 has an on-chip reference with an internal gain of 2. The AD5666-1 has a reference voltage of 1.25 V 5 ppm/°C with a full-scale output of 2.5 V; the AD5666-2 has a reference voltage of 2.5 V 5 ppm/°C with a full-scale output of 5 V. The on-board voltage reference is turned off at power-up, allowing the use of an external voltage reference. Open internal references by writing to the DAC.

This section contains a power-on reset circuit that ensures that the DAC output powers up to 0 V (POR-pin low) or midscale (POR-pin high) and remains powered up at that level until a valid write occurs. This section includes a power-down feature that reduces the device's current consumption to 400mA at 5 V and provides software-selectable output loading in power-down mode for any or all DAC channels.

All DAC outputs can use the LDAC function, adding a user-selectable DAC channel function that can be updated simultaneously. There is also an asynchronous CLR that clears all DACs to a software-selectable code—0 V, midscale, or full scale.

The AD5666 features a versatile 3-wire serial interface that operates at clock frequencies up to 50 MHz and is compatible with standard SPI® and QSPI™, Microwire™ and digital signal processor interface standards. On-chip precision output amplifiers achieve rail-to-rail output swing.

Product Highlights

1. Four-bit, 16-bit DAC.

2. On-chip 1.25 V/2.5 V, 5 ppm/℃ benchmark.

3. Provide 14 lead TSSOP.

4. Optional power-on reset to 0 V or mid-scale.

5. Power-off capability. When powered down, the DAC typically consumes 200na at 3v and 400na at 5v.

Timing Characteristics

All input signals are specified with tr=tf=1 ns/V (10% to 90% of voltage) and are timed from a voltage level of (V+V)/2. See Figures 3 and 5. V=2.7V to 5.5V. All specifications T to T unless otherwise stated.

Absolute Maximum Ratings

T=25°C unless otherwise noted.

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Typical performance characteristics

the term

Relative accuracy

For a DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation in the lsb from a straight line passing through the endpoints of the DAC transfer function. Figure 6 shows a typical INL versus code plot.

Differential nonlinearity

Differential Nonlinearity (DNL) is the difference between the measured variation of any two adjacent codes and the ideal 1lsb variation. Monotonicity is assured by differential nonlinearity specified to a maximum of ±1 LSB. The monotonicity of the DAC is guaranteed by design. Figure 7 shows a typical DNL versus code plot.

offset error

Offset error is the difference between the measured actual voltage and the ideal voltage, expressed in millivolts in the linear region of the transfer function. The offset error is measured on the AD5666 and the code 512 is loaded into the DAC register. It can be negative or positive and is expressed in millivolts.

Zero code error

A zero code error is a measure of the output error when a zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. Since the output of the DAC cannot go below 0 V, the zero code error is always positive in the AD5666. This is due to a combination of offset errors in the DAC and output amplifier. Zero code errors are expressed in millivolts. Figure 13 shows a typical zero-code error vs.

temperature.

gain error

Gain error is a measure of DAC span error. It is the slope deviation of the DAC transfer characteristic from ideal, expressed as a percentage of the full-scale range.

Zero code error drift

Zero-code error drift is a measure of zero-code error as a function of temperature. Expressed in μV/°C.

Gain Error Drift

Gain error drift is a measure of the change in gain error with temperature. Expressed in (ppm of full scale)/°C.

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V-1 LSB. Full-scale error is expressed as a percentage of full-scale range. Figure 13 shows a typical full-scale error versus temperature plot.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault region in nV-s and is measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000). See Figure 29.

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to the change in V for the full-scale output of the DAC. It is measured in decibels. V remains at 2V and V varies by ±10%.

DC crosstalk

DC crosstalk is the DC change in the output level of one DAC as the output of another DAC changes. It is measured by the full-scale output change of one DAC (or soft power off and on) while monitoring the other DAC held at mid-scale. It is expressed in microvolts.

DC crosstalk caused by load current changes is a way to measure the effect of load current changes on one DAC on another DAC held at midscale. It is expressed in microvolts per milliampere.

reference feedthrough

Reference feedthrough is when the ratio of the signal amplitude at the DAC output to the reference input is not updated (ie, LDAC is high) when the DAC outputs. It is expressed in decibels.

digital feedthrough

Digital feedthrough is a measurement of pulses injected into the DAC's analog output from the device's digital input pins, but measured when the DAC is not writing (sync held high). It is specified in nV-s and is measured by a full-scale change on the digital input pins, i.e. from all 0s to all 1s, or vice versa.

digital crosstalk

Digital crosstalk is a glitch pulse that is mid-scale transferred to the output of one DAC in response to a full-scale code change (all 0s to all 1s, and vice versa) in the input register of the other DAC. It is measured in standalone mode and expressed in nV-s.

Analog crosstalk

Analog crosstalk is a glitch pulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading an input register with a full-scale code change (all 0s to all 1s and vice versa) high while holding LDAC high, then pulsing LDAC low, and monitoring the DAC whose digital code has not changed Output. The fault area is denoted by nV-s.

DAC-to-DAC crosstalk

DAC-to-DAC crosstalk is a glitch pulse transferred to the output of one DAC due to a change in the digital code of one DAC and a subsequent change in the output of the other DAC. This includes digital and analog crosstalk. It is by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) measuring LDAC low and monitoring the output of the other DAC. The fault energy is expressed in nV-s.

Double the bandwidth

Amplifiers within a DAC have limited bandwidth. Multiplying bandwidth is one measure. A sine wave on the reference appears in the output (loading the full-scale code to the DAC). The octave bandwidth is the frequency at which the output amplitude drops 3db below the input.

Total Harmonic Distortion (THD)

Total Harmonic Distortion is the difference between an ideal sine wave and an attenuated sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. It is in decibels.

theory of operation

Section D/A

The AD5666 DAC is fabricated in a CMOS process. The structure consists of a series of DACs and an output buffer amplifier. These parts include an internal 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure 40 shows a block diagram of the DAC architecture.

Because the input encoding of the DAC is straight binary, the ideal output voltage when using an external reference is given by:

The ideal output voltage and internal reference when used are given by:

Where: D = Load into DAC register. 0 to 65535 (16 bits) for AD5666. N=DAC resolution.

resistor string

The resistor string section is shown in Figure 41. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines from which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

internal reference

The AD5666 has an on-chip reference with an internal gain of 2. The AD5666-1 has a reference voltage of 1.25 V 5 ppm/°C and a full-scale output of 2.5 V. The AD5666-2 has a reference voltage of 2.5 V 5 ppm/°C and a full-scale output of 5 V. The on-board voltage reference is turned off at power-up, allowing the use of an external voltage reference. Internal references are enabled by writing to the control register.

An internal reference associated with each part is available at the V pin. A buffer is required if the reference output is used to drive an external load. When using the internal reference, it is recommended to place a 100 nF capacitor between the reference output and GND to maintain reference stability.

Single channel power down is not supported when using internal references.

output amplifier

The output buffer amplifier produces rail-to-rail voltages at its output with an output range of 0 V to V. The amplifier is capable of driving 2 kΩ loads in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier are shown in Figure 19 and Figure 20. The slew rate is 1.5v/µs, the range settling time is 10µs, and the range is 1/4 to 3/4.

serial interface

The AD5666 has a 3-wire serial interface (synchronous, SCLK compatible with SPI, QSPI, and MICROWIRE interface standards and most DSPs. See Figure 3 for a timing diagram for a typical write sequence.

Pull the sync line low at the beginning of the write sequence. Data from the data line is recorded into a 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the AD5666 compatible with high-speed DSPs. On the 32 falling clock edge, the last data bit is clocked and performs the programming function, ie, a change of DAC register contents and/or a change of mode operation. During this phase, the sync line can be held low or high. In both cases, it must be brought up at least 15 ns before the next write sequence, so that the falling edge of synchronization can initiate the next write sequence. Because the sync buffer draws more current at V=2v than at V=0.8v, between write sequences, SYNC should be idle low for lower-power in-parts. However, as mentioned earlier, synchronization must be improved again before the next write sequence.

input shift register

The input shift register is 32 bits wide (see Figure 42). The first four are not important. The next four bits are the command bits C3 to C0 (see Table 8), followed by the 4-bit DAC address bits A3 to A0 (see Table 9), and finally the 16-bit data word. The data word consists of a 16-bit input code followed by 4 bits that are not relevant to the AD5666 (see Figure 42). These data bits are transferred to the DAC register on the falling edge of SCLK 32.

Sync outage

In a normal write sequence, the sync line is held low for at least 32 falling edges of SCLK, and the DAC is updated on 32 falling edges. However, if at 32Nd falling edge, it acts as an interrupt for the write sequence. The shift register is reset and the write sequence is considered invalid. Neither an update of the DAC register contents nor a change in operating mode occurs (see Figure 43).

Daisy chain

For systems that contain multiple DACs, or where the user wishes to read the contents of the DACs for diagnostic purposes, the SDO pin can be used to chain multiple devices together and provide serial reads.

Daisy-chain mode is enabled by a software executable DCEN command. Command 1000 is reserved for this DCEN function (see Table 7). Daisy-chain mode can be enabled by setting a bit (DB1) in the DCEN register. The default setting is standalone mode with bit DCEN=0. Table 9 shows the state of the bits corresponding to the operating mode of the device.

SCLK is continuously applied to the input shift register when synchronization is low. If more than 32 clock pulses are applied, the data will fluctuate out of the shift register and appear on the SDO line. This data is clocked on the rising edge of SCLK and is valid on the falling edge. By connecting this wire to the DIN input of the next DAC in the chain, a multi-DAC interface is constructed. Each DAC in the system requires 32 clock pulses; therefore, the total number of clock cycles must equal 32N, where N is the total number of devices in the chain.

Sync will be high when the serial transfer to all devices is complete. This prevents any further data from being recorded into the input shift register.

If sync is set high before 32 clocks into the part, it is considered an invalid frame and the data is discarded. The serial clock can be a continuous clock or a gated clock.

A continuous SCLK source should only be used if synchronization can be kept at the correct number of clock cycles low. In gated clock mode, when a burst clock containing the exact number of clock cycles must be used, a high sync must be performed after the last clock to lock the data.

Internal reference register

By default, on-board reference is turned off at power on. This allows external references to be used when needed by the application. The user-programmable reference register can turn on/off the on-board reference by setting bit DB0 high or low (see Table 9). Command 1000 is reserved for this internal REF setup command (see Table 7). Table 11 shows how the state of the bits in the input shift register corresponds to the operating mode of the device.

power-on reset

The AD5666 includes a power-on reset circuit that controls the output voltage during power-up. By connecting the POR pin low, the AD5666 outputs power up to 0 V; by connecting the POR pin high, the AD5666 outputs power up to midscale. The output will remain powered on at this level until a valid write sequence is issued to the DAC. This is useful in applications where it is important to know the state of the DAC's output during power-up. There is also a software executable reset function that resets the DAC to a power-on reset code. Command 0111 is reserved for this reset function (see Table 7). During power-on reset, any events on the LDAC or CLR are ignored.

Power down mode

The AD5666 contains four independent modes of operation.

Command 0100 is reserved for the power down function (see Table 7). These modes are software programmable by setting two bits in the control register, Bit DB19 and Bit DB18. Table 11 shows how the state of the bits corresponds to the operating mode of the device. Any or all DACs (DAC D to DAC A) can be powered down to the selected mode by setting the corresponding four bits (DB7, DB6, DB1, DB0) to 1. The contents of the input shift register during power-down/power-up operations are shown in Table 12. When using the internal reference, only all channel power down to the selected mode is supported.

When both bits are set to 0, the part operates normally with a normal power consumption of 700µA and a voltage of 5V. However, for the three power-down modes, the supply current drops to 400Na at 5V (200Na at 3V). Not only does the supply current drop, but the output stage also switches from inside the amplifier's output to a network of resistors of known value. The advantage of this is that the output impedance of the component is known when the component is in power down mode. There are three different options. The output is internally connected to GND via a 1kΩ or 100kΩ resistor, or left open (tri-stated). The output stage is shown in Figure 44.

When the power-down mode is activated, the bias generator, output amplifier, resistor string and other associated linear circuits are turned off. The internal reference will only be powered down when all channels are powered down. However, when powered down, the contents of the DAC registers are not affected. For V=5V and V=3V, the time to exit power-down is typically 4 μs (see Figure 28).

Any combination of DACs can be powered up by setting PD1 and PD0 to 0 (normal operation). The output powers up to the value in the input register (LDAC low) or the value in the DAC register before power down (LDAC high).

clear code register

The AD5666 has an asynchronous hardware CLR pin clear input. The CLR input is falling edge sensitive. Turning the CLR line low will clear the input registers and DAC registration with the data contained in the user-configurable CLR register and set the analog output accordingly. This function can be used for system calibration to load zero scale, mid scale, or full scale for all channels. These clear code values are obtained by the user by setting two bits, DB1 and DB0, in the control register (see Table 13). The default setting clears the 0 V output. Command 0101 is reserved for loading the clear code register (see Table 7).

Components Write this part down next. If the CLR is activated during a write sequence, the write will abort.

When the output begins to change, the CLR pulse activation time for the falling edge of CLR is typically 280ns. However, if it is outside the DAC linear region, it typically takes 520ns after execution to output the CLR at which it begins to change (see Figure 38).

The contents of the input shift register during the load clear code register operation are shown in Table 14

LDAC function

The outputs of all DACs can be updated simultaneously using the hardware LDAC pins.

Synchronous LDAC: After reading new data, the DAC register is updated on the falling edge of 32 SCLK pulses. As shown in Figure 3, LDAC can be permanently low or pulsed.

Asynchronous LDAC: The output does not update the time written to the input register at the same time. When LDAC goes low, the DAC register is updated with the contents of the input register.

Alternatively, the software LDAC function can be used to update the outputs of all DACs simultaneously by writing to input register n and updating all DAC registers. Command 0011 is reserved for this software LDAC function.

The LDAC register provides the user with additional flexibility and control over the hardware LDAC pins. This register allows the user to select a combination of channels to be updated simultaneously when implementing the hardware LDAC pins. Setting the LDAC bit register for a DAC channel to 0 means that the update of that channel is controlled by the LDAC pin. If this bit is set to 1, the channel will be updated synchronously; that is, the DAC register will be updated after new data is read, regardless of the state of the LDAC pin.

It effectively holds the LDAC pin low. (See Table 15 for LDAC register operating modes.) This flexibility is useful in applications where the user wishes to update selected channels simultaneously while the remaining channels are being updated synchronously.

Write to the DAC using command 0110 to load the 4-bit LDAC registers (DB3 to DB0). The default value for each channel is 0; that is, the LDAC pin is functioning properly. Setting the bit to 1 means that the DAC channel is updated regardless of the state of the LDAC pin. The contents of the input shift register are shown in Table 16 during the load LDAC register mode of operation.

Power Bypass and Ground

When accuracy is important in a circuit, double check considers the power and ground return layout on the board. The printed circuit board containing the AD5666 should have separate analog and digital sections. If the AD5666 is in a system where other devices require an AGND to DGND connection, it should only be connected at one point. This ground point should be as close as possible to the AD5666.

The power supply to the AD5666 should be bypassed with 10µF and 0.1µF capacitors. The capacitor should be physically located as close to the device as possible, ideally, the 0.1µF capacitor should be right across from the device. The 10µF capacitors are of the tantalum bead type. Importantly, 0.1µF capacitors have low effective series resistance (ESR) and low effective series inductance (ESI), typical of common ceramic capacitors. This 0.1µF capacitor provides a low impedance ground path for high frequency transient current induced internal logic transitions.

Power lines should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power line. Clocks and other fast switching digital signals should be shielded from the rest of the board by digital ground. Avoid crossover of digital and analog signals as much as possible. When the traces cross on opposite sides of the board, make sure they run at right angles to each other to reduce the effect of feedthrough through the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane, and the signal traces are placed on the solder side. However, this is not always possible with 2-layer boards.

Dimensions

[1] The temperature range is -40°C to +105°C, typically 25°C.

[2] Linearity computed using a reduced code range of 512 to 65024. The output is unloaded.

[3] Guaranteed by design and characterization; not production tested.

[4] The interface is not active. All DACs activated. The DAC output is unloaded.

[5] All four DACs are powered down.

[6] The temperature range is -40°C to +105°C, typically 25°C.

[7] Linearity computed using a reduced code range of 512 to 65024. The output is unloaded.

[8] Guaranteed by design and characterization; not production tested.

[9] The interface is not active. All DACs activated. The DAC output is unloaded.

[10] All four DACs are powered down.

[11] Guaranteed by design and characterization; not production tested.

[12] See the Terminology section.

[13] The temperature range is -40°C to +105°C, typically 25°C.

[14] The maximum SCLK frequency is 50 MHz, V=2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

[15] Measured with the load circuit of Figure 16. tDetermines the maximum SCLK frequency in daisy-chain mode.

[16] Daisy-chain mode only.

[17] Z = RoHS compliant parts.