This family of fully featured hot-swap power controllers targets applications in the +2.5V to +12V range. The ISL6115 for +12V control, the ISL6116 for +5V, and the ISL6117 for +3.3V and ISL6120 for +2.5V control are applied. Each has a hardwired undervoltage (UV) monitoring and reporting threshold level approximately 80% of the aforementioned voltage. The ISL6115 has an integrated charge pump that allows the use of an external N-channel to control rail MOSFETs up to +16V while other devices use a +12V bias to fully enhance the N-channel pass FET. All integrated circuits feature programmable overcurrent (OC) detection, current regulation (CR), time delay to latch-up and soft-start. The current regulation level is set by 2 external resistors; RISET sets CR Vth, the other is a low ohmic sensing element, CR-Vth is developed. The CR duration is determined by an external capacitor on the CTIM pin, which charges 20µA once it reaches the CR-Vth level. If the voltage on the CTIM capacitor reaches 1.9V on the IC, then the gate is quickly pulled down and the output latches through the FET. Although this series is designed for high-side switch control ISL6116, ISL6117, ISL6120 can also be used in low-side configuration for controlling higher voltage potentials.

feature

Hot-swappable single power distribution control (ISL6115 for +12V, ISL6116 for +5V, ISL6117 for +3.3V and ISL6120 (for +2.5V)

Overcurrent Fault Isolation

Programmable Current Regulation Levels

Programmable current regulation time

latch

Rail-to-Rail Common Mode Input Voltage Range (ISL6115)

Internal charge pump allows use of N channels

+12V control MOSFET (ISL6115)

Undervoltage and Overcurrent Lockout Indicators

Adjustable ramp

Protection when turned on

Two-stage overcurrent detection provides fast

Response to various fault conditions

Very short response time of 1 microsecond

Lead-free available (RoHS compliant)

application

Distribution control

Hot-swappable components and circuits

notes:

1. Please refer to TB347 for reel specifications. Add "-T" suffix for tapes and reels.

2. These Intersil lead-free plastic packaged products feature a special lead-free material kit, molding compound/mold accessory material and 100% matte tinplate plus annealed (e3 termination finish, RoHS compliant and compatible with both SnPb and no lead soldering operations). Intersil lead-free products are classified as MSL meeting or exceeding the lead-free requirements of IPC/JEDEC J STD-020 at lead-free peak reflow temperatures.

3. For Moisture Sensitivity (MSL), see the device information page of the ISL6115. For more information on MSL, see Technical Bulletin TB363.

Absolute Maximum Ratings TA=+25°C Thermal Information

Seller Due Diligence. -0.3V to +16V. -0.3V to VDD+8V

Ethan, Purwood, Prang, CTIM, East. -0.3V to VDD+0.3V

Electrostatic discharge rating

mannequin. 5 kV

operating conditions

VDD supply voltage range (ISL6115). +12V±15%

VDD supply voltage range (ISL6116, 17, 20). +12V±25%

temperature range (TA). 0°C to +85°C

Thermal Resistance (Typical, Note 4) θJA (°C/Watt)

8 Ld SOIC package. 98

Maximum Junction Temperature (Plastic Packaging). +150 degrees Celsius

Maximum storage temperature range. -65°C to +150°C

Lead-free reflow profile.

NOTE: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to this condition may have adverse effects

Product reliability, resulting in failures not covered under warranty.

notes:

4. In free air, measure JA with components mounted on a high-efficiency thermal conductivity test board. See Technical Brief for details on TB379.

5. Unless otherwise specified, all voltages are relative to ground

Electrical Specifications VDD=12V, TA=TJ=0°C to +85°C, unless otherwise specified. Temperature limits are determined by characterization, not production tested. Blackbody limits apply over the operating temperature range, -40°C to +85°C.

Electrical Specifications VDD=12V, TA=TJ=0°C to +85°C, unless otherwise specified. Temperature limits are determined by characterization, not production tested. Blackbody limits apply to operating temperature range, -40°C to +85°C (continued)

notes:

6. Limits determined by characterization, without production testing.

7. Unless otherwise specified, parameters with minimum and/or maximum limits are 100% tested at +25°C.

Instructions and Operations

Members of this family of integrated circuits are single-supply universal hot-swap distribution controllers for applications in the +2.5V to +12V supply range. The ISL6115 is targeted for +12V switching applications while the ISL6116 is targeted for +5V, the ISL6117 for +3.3V and the ISL6120 for +2.5V applications. Each IC has a hardwired undervoltage (UV) threshold level higher than the specified voltage. These ICs feature highly accurate programmable features, programmable time current regulation (CR) level delay latching and programmable soft start turnHon ramps all set with minimal external passive components. ICs also include severe OC protection switches that immediately turn off the MOSFETs for fast load current transients, such as an absolute short circuit that causes CR Vth to exceed the programmed level by 150 mV. In addition, the IC has UV indicator and OC latch indicator. The functionality of this PGOOD feature is enabled only once the IC is biased, monitoring and reporting any UV condition on the ISEN pin. During initial power-up, the IC can be isolated from the voltage directly connected to the load by keeping the external N-channel MOSFET off or applying the supply rail for true hot-swap capability. The PWRON pin must be pulled low for the device to shut down by holding down the external N-channel MOSFET. Holding high or floating the IC with the Prang pin will be in true hot-swap state mode. In both cases, the IC turns on the supply rail in a soft-start mode to prevent the current from emergencies. On turn-on, the external gate capacitor of the N-channel MOSFET is charged with a 10µA current to generate a programmable ramp (soft-start source turn-on). The internal ISL6115 oil charge pump powers the gate drive gate of the 12V power switch to ~VDD+5V, for the other three ICs, the gate drive voltage is limited to the chip bias, VDD. The load current is passed through an external current sense resistor. When the voltage across the sensor exceeds the user-set CR voltage threshold (see Table 1 for riser programming resistance values and the resulting nominal current regulation threshold voltage, VCR) the controller enters the current regulation mode. At this point, suspend the capacitor, charge the power supply with 20µA of current on the CTIM pin, and limit the time-lock time at the controller input current. The length of the current limit time The latch duration is determined by the single CTIM capacitor external capacitor (see Table 2) value and the resulting nominal current limit timeout The duration of the latch from the CTIM pin (pin 6) to ground. The programmed current level remains until the OC event passes or the timeout expires. If the former, then the N-channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once the CTIM is charged to 1.87V, the signal timeout period has elapsed, and the internal latch is set to quickly pull the FET gate to 0V to turn off the N-channel MOSFET switch, isolating the erroneous load.

Note: Nominal vertical height = vertical height x 20μA.

Note: Nominal timeout = CTIM x 93k 61527.

The IC responds to severe overcurrent loads (defined as voltages >150mV on the sense resistor by driving the N-channel MOSFET gate to 0V immediately for approximately 10µs. The gate then slowly raises the voltage, turning on the N-channel MOSFET for programmed current This is the start of a time-out period. During UV conditions, the PGOOD signal is pulled low when connected to logic or VDD via a resistor supply. This pin is the UV fault indicator. For OC lockout indication, the monitor CTIM , pin 6. This pin will quickly rise from 1.9V to VDD once it times out. See 12 to 16 text for related waveforms. The IC resets after the OC latch off state is low on the PWRON pin and is leveled by the PWRON pin is driven high.

Application Notes

Design applications where the CR Vth setting is very tight (25 mV or less) have twice the risk to consider. Sensitivity to noise affects the absolute CR-Vth value. This can be done with a 100pF capacitor through the RSENSE resistor. Due to the overcurrent comparator, the voltage pin on ISET must be 20mV above IC ground initially (from ISET*RSET) or time out before CTIM arrives (from gate charging). If it does not occur, the IC may falsely report an overcurrent without a fault start-up fault. Circuits with high load capacitance and initially low load current are susceptible to this unexpected behavior. Do not signal and do not pull the PWRON input to >5V. Exceeding 6 volts will cause the internal charge pump to malfunction. The external N-channel MOSFET drives the MOSFET switch into (linear region) high rDS(on) during soft-start and time-out delays when the IC is in its current limit mode. The external N-channel mosfet may be damaged or damaged due to excessive internal power dissipation during the CR limit and timing requirements to avoid the following conditions. See manufacturer's data sheet. Short CR times provide the best reliability and application solution for FET MTFs when driving particularly large capacitive loads after longer soft-start times to prevent current regulation charging. The physical layout of the resistors is important to avoid false overcurrents. Ideally, trace the wiring between the RSENSE resistors to the IC as directly as possible and with zero current in the short sense lines (see Figure 1).

Use ISL6116 as -48V

The low-side hot-swap power controller must keep the chip supplying 10V to 16V on the -48V bus in order to provide the required VDD. This can be done with an appropriate regulator between the voltage rail and pin 5 (VDD). By using a regulator, designers can ignore bus voltage variations. However, a low-cost alternative is to use a Zener diode (see Figure 2 for typical 5A load control); this option is described in detail below. Note that in this configuration, the PGOOD feature (pin 7) does not work because the ISEN pin voltage is always less than the UV threshold. The relevant waveforms are shown in Figure 17 to Figure 20-48V and other high voltage applications.

Biasing the ISL6116 Table 3 gives the biasing of the ISL6116 in ±48V applications. The formulas and calculations that derive these values are also shown in Follow Equations.

When using the ISL6116 to control -48V, a Zener diode can be used to provide +12V bias to the chip. If a zener is used, the current limiting resistor should also be utilized. Several items must be considered when choosing the value of the current limiting resistor (RCL) and the zener diode (DD1): Variation in VBU (in this case -48V nominal)

Chip supply current conditions required for all functions

Power rating of the RCL.

Rated current of DD1

The ISL6115EVAL1Z board ISL6115EVAL1Z defaults to a side switch controller with a +12V high CR level set at ~1.5A. The ISL6115EVAL1Z schematic and table are shown in Figure 214 representing the bill of materials. Bias and load connection points are provided along with test points for each IC pin. With J1 installed, the ISL6115 will deviate from + is switching the 12V supply (VIN). Connect the load to VLOAD+. The PWRON pin is pulled high internally, enabling the ISL6115, if it fails the PWRON test point or J2 to drive at low speed. When R3 = 750, CR Vth is set to 15 volts and the ISL6115EVAL1Z has a 10m sense resistor (R1) with a nominal CR level of 1.5A. A 0.01µF delay-time blocking capacitor locks the output after an OC event. The ISL6115EVAL1Z board also includes an evaluation of each of the ISL6116, ISL6117, and ISL6120 ICs in high-end applications. Remove J1 and provide a separate +12V IC bias supply through the VBIAS test point. Reconfiguring the ISL6115EVAL1Z board for later versions can be done by changing RSENSE and/or the supplied FETs for higher current ratings. ISL6116EVAL1 Board The ISL6116EVAL1 is configured by default for a negative value a~2.4A CR low side switch controller level. See Table 4 for the ISL6116EVAL1 schematic and bill of materials and parts description. This basic configuration is capable of controlling two large minimal positive or negative potential changes. Deviation and load connection points are at TP1 to TP8 of each IC pin except the test point. The terminals, J1 and J4 for bus voltage and return, respectively, are negative potential connected to J4. The load J3 board between terminals J2 is now configured for evaluation. This enables the device by logging in, using TTL's TP9 signal. The ISL6116EVAL1 includes a level-shift circuit with opto-couplers for the PWRON input. Standard TTL logic can be converted to a -V chip control reference. When controlling positive voltage, PWRON can be accessed at TP8. The ISL6116EVAL1 is equipped with a high-voltage linear regulator that facilitates providing chip bias from ±24V to ±350V. Can be removed and replaced with the Zener and resistor biasing schemes discussed earlier. High Voltage Regulators and Power Supplies Intersil no longer offers discrete devices but can buy from other semiconductor manufacturers. Reconfiguring the ISL6116EVAL1 board for higher CR levels can be done by changing the RSENSE and RISET resistance values of the provided FETs with a 75A rating. If the evaluation voltage is >60V, the spare FET must be selected with sufficient BVDSS.