Signal monitor

The Signal Monitor block provides additional information about the signal being digitized by the ADC. The signal monitor calculates the rms input amplitude, peak amplitude, and/or the number of samples whose amplitude exceeds a certain threshold. At the same time, these functions can be used to gain insight into signal characteristics and estimate the peak/average ratio of the input signal or even the shape of the complementary cumulative distribution function (CCDF) curve. This information can be used to drive the AGC loop to optimize the range of the ADC in the presence of a real signal.

The signal monitor result value can be obtained from the part by reading Register 0x116 back to Register 0x11B using the SPI port or the Signal Monitor SPORT output. The output contents of the SPI-accessible Signal Monitor register are set by the two Signal Monitor Mode bits in the Signal Monitor Control Register (Address 0x112). Both ADC channels must be configured in the same signal monitor mode. Provides separate SPI-accessible 20-bit Signal Monitor Results (SMR) registers (Address 0x116 to Address 0x11B) for each ADC channel. Any combination of signal monitor functions can also be output to the user via the serial motion interface. These outputs are enabled using the Peak Detector Output Enable, RMS Magnitude Output Enable, and Threshold Crossing Output Enable bits in the Signal Monitor Motion Control Register (Address 0x111).

For each signal monitor measurement, the programmable signal monitor period register (SMPR) controls the duration of the measurement. The period is programmed as the number of input clock cycles in the 24-bit Signal Monitor Period registers located at Address 0x113, Address 0x114, and Address 0x115. This register is programmable from 128 samples to 16.78 (2 million) samples.

Since the dc offset of a dc can be significantly larger than the signal of interest (affecting the results from the signal monitor), a dc correction circuit is included as part of the signal monitor block to make the dc offset zero before measuring the power .

Peak Detector Mode

The amplitude of the input port signal is monitored for a programmable period (determined by the SMPR) to give the detected peak. This feature is enabled by programming a logic 1 in the Signal Monitor Mode bit in the Signal Monitor Control Register (Address 0x112) or by setting the Peak Detector Output Enable bit in the Signal Monitor Motion Control Register (Address 0x111). Before activating this mode, the 24-bit SMPR must be programmed.

When this mode is enabled, the value in the SMPR is loaded into the watchdog period timer and the countdown begins. The amplitude of the input signal is compared to the value in the internal peak level hold register (not accessible to the user), and the greater of the two values is updated as the current peak level. The initial value in the peak hold register is set to the current ADC input semaphore, and the comparison continues until the watchdog period timer reaches a count of 1.

When the watchdog period timer reaches count 1, the 13-bit value in the peak level holding register is transferred to the signal monitor holding register (inaccessible to the user) and can be read through the SPI port or output through the motion serial interface. Reload the watchdog period timer with the value in SMPR and restart the countdown. Furthermore, the value in the peak hold register is reset to the size of the first input sample and the compare and update process explained previously continues.

Figure 67 is a block diagram of the peak detector logic. The SMR register contains the absolute magnitude of the peak detected by the peak detector logic.

RMS/MS amplitude mode

In this mode, the root mean square (rms) or root mean square (ms) amplitude of the input port signal is integrated (by adding an accumulator) over a programmable period (determined by the SMPR) to give the input signal rms or ms amplitude. This mode is set by programming a logic 0 in the Signal Monitor Mode bit in the Signal Monitor Control Register (Address 0x112) or by setting the rms Amplitude Output Enable bit in the Signal Monitor Motion Control Register (Address 0x111). Before activating this mode, the 24-bit SMPR representing the cycle in which integration is performed must be programmed.

When rms/ms amplitude mode is enabled, the value from SMPR is loaded into the watchdog period timer and the countdown begins immediately. Each input sample is converted to floating point format and squared. It is then converted to 11-bit fixed-point format and added to the contents of the 24-bit accumulator. Integration will continue until the watchdog period timer reaches a count of 1.

When the watchdog period timer reaches count 1, the square root of the value in the accumulator is taken and transferred (after some formatting) to the signal monitor holding register, which can be read via the SPI port or via the SPORT serial port output. Reload the watchdog period timer with the value in SMPR and restart the countdown. Additionally, the value of the accumulator is reset to the first input sample signal power, and the accumulator continues with subsequent input samples.

Figure 68 illustrates the RMS monitoring logic.

For RMS magnitude mode, the value in the Signal Monitor Result (SMR) register is a 20-bit fixed-point number. The following formula can be used to determine the rms value in decibel full scale (dBFS) from the MAG value in the register:

where the second term in the equation becomes 0 if the signal monitoring period (SMP) is a power of 2.

For ms-magnitude mode, the value in SMR is a 20-bit fixed point number. The following formula can be used to determine the ms magnitude (decibel full scale (dBFS)) from the MAG value in the register:

where the second term in the equation becomes 0 if SMP is a power of 2.

overrun mode

In the threshold crossing mode of operation, the amplitude of the input port signal is monitored for a programmable period of time (determined by the SMPR) to count the number of times it crosses some programmable threshold. This mode is achieved by programming logic 1x (where x is a don't care bit) in the Signal Monitor Mode bits in the Signal Monitor Control Register (Address 0x112) or by setting the Threshold Crossover Output in the Signal Monitor Motion Control Register (Address 0x111) enable bit to set. Before activating this mode, the user needs to program the 24-bit Signal Monitor Period Register (Address 0x113 to Address 0x115) and the 13-bit Fine Upper Threshold Register (Address 0x106 and Address 0x107) for each individual input port. The same high threshold registers are used for signal monitoring and gain control (see ADC Overrange and Gain Control section).

After entering this mode, the value from SMPR is loaded into the watchdog period timer and the countdown begins. On each input clock cycle, the amplitude of the input signal is compared to a previously programmed fine upper threshold register. If the magnitude of the input signal is greater than the value set in the fine upper threshold register, the value in the internal count register (not accessible to the user) is incremented by 1.

The initial value of the internal count register is set to 0. Comparing and incrementing this value will continue until the watchdog period timer reaches a count of 1.

When the watchdog period timer reaches count 1, the value in the internal count register is transferred to the signal watchdog holding register (not accessible to the user), which can be read through the SPI port or output through the motion serial port.

Reload the watchdog period timer with the value in SMPR and restart the countdown. The internal count register is also cleared to the value 0. Figure 69 illustrates the threshold crossing logic. The value in the SMR register is the number of samples greater than the fine upper threshold register.

Additional control bits

For added flexibility in the signal monitoring process, two control bits are provided in the Signal Monitoring Control Register (Address 0x112). They are the signal monitor enable bit and the complex power calculation mode enable bit.

Signal Monitor Enable Bit

The Signal Monitor Enable bit, located in Register 0x112, Bit 0, enables the operation of the Signal Monitor block. If the signal monitor function is not required in a specific application, this bit should be cleared (default) to save power.

Complex power calculation mode enable bit

When this bit is set, the part assumes that channel A is digitizing the I data and channel B is digitizing the Q data of the complex input signal (or vice versa). In this mode, the reported power is equal to

If the Signal Monitor Mode bits are set to 00, this result is displayed in the Signal Monitor DC Value Channel A register (Address 0x10D and Address 0x10E). The Signal Monitor DC Value Channel B register (Address 0x10F and Address 0x110) continues to calculate the Channel B value.

DC correction

Since the dc offset of a dc can be significantly larger than the signal being measured, a dc correction circuit is included to make the dc offset zero before measuring the power. The DC correction circuit can also switch to the main signal path, but this may not be appropriate if the a dc is digitizing a time-varying signal with significant DC content (eg GSM).

DC correction bandwidth

The DC correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 ms/sec). Bandwidth is controlled by writing to the 4-bit dc correction bandwidth register located in Register 0x10C, Bits[5:2].

The following formula can be used to calculate the bandwidth value of the DC correction circuit:

where: k is the 4-bit value programmed in Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13).

fCLK is the AD9600 ADC sampling rate in Hertz.

DC Correction Readback

The current DC correction value can be read in Register 0x10D and Register 0x10E (Channel A) and Register 0x10F and Register 0x110 (Channel B). The DC correction value is a 10-bit value that can span the entire input range of the ADC.

DC Correction Freeze

Setting the DC Correction Freeze bit (Register 0x10C, Bit 6) stops the DC correction in its current state and continues to use the last updated value as the DC correction value. Clearing this bit will restart dc correction and add the current calculated value to the data.

DC Correction Enable Bit

Setting Bit 0 (DC Correction of SM Enable Bit) in Register 0x10C enables dc correction for use in signal monitor calculations. Setting Bit 1 (DC Correction of Signal Path Enable Bits) in Register 0x10C causes the calculated DC correction value to be added to the output data signal path.

Motion Output Signal Monitor

SPORT is a serial interface with three output pins: SMI SCLK (Motion Clock), SMI SDF (Motion Frame Sync), and SMI SDO (Motion Data). Motion is the master, driving all three motion output pins on the chip.

SMI symptom self-rating scale

Data and frame sync are driven on the positive edge of SMI SCLK. SMI SCLK has three possible baud rates: 1/2, 1/4 or 1/8 ADC clock rate, based on motion control. Additionally, by using the SPORT SMI SCLK sleep bit, the SMI SCLK can be strobed to remain low when the signal monitor block is not sending any data. When SMI SCLK is not needed, disabling it with this bit reduces coupling errors in the return signal path. However, this has the disadvantage of spreading out the frequency content of the clock; if desired, the SMI SCLK can be left enabled to simplify frequency planning.

SMI SDF

SMI SDFS is Serial Data Frame Synchronization. It defines the start of the frame. A motion frame contains data from two data paths. Data in datapath A is sent after frame synchronization, followed by data in datapath B.

SMI SDO

SMI SDO is the serial data output of the block. Data is sent MSB on the first positive side after SMI SDFS. Each data output block includes one or more rms values, peak level values for each data path and threshold crossing value commands. If enabled, data is sent, first rms, then peak value and threshold crossing value, as shown in Figure 70.

Built-in Self-Test (BIST) and Output Test

The AD9600 includes built-in test functions that verify the integrity of each channel and facilitate board-level debugging. A BIST feature is included to verify the integrity of the AD9600's digital datapath. Various output test options are also provided to place predictable values on the outputs of the AD9600.

Built-in Self-Test (BIST)

BIST is a thorough test of the digital portion of the selected AD9600 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath, starting from the ADC block output. The BIST sequence runs for 512 cycles and then stops. The BIST signature value for Channel A or Channel B is placed in Register 0x24 and Register 0x25. If a channel is selected, its BIST signature will be written to both registers. If two channels are selected, the results of the two channels are XORed and placed in the BIST signature register.

During the test, the output was not disconnected; therefore, the PN sequence can be observed at runtime. The PN sequence can continue from its last value or start from the beginning, depending on the value programmed in Register 0x0E, Bit 2. BIST signature results vary according to channel configuration.

output test mode

The output test options are shown in Table 22. When the output test mode is enabled, the analog portion of the ADC is disconnected from the digital backend block, and the test mode runs through the output formatting block. Some test patterns are bound by the output format, and some are not bound by the output format. The seed value for the PN sequence test can be used to force the generator to remain in reset mode by setting Bit 4 or Bit 5 of the Test Mode Register (Address 0x0D). These tests can be done with or without an analog signal (if present, the analog signal is ignored), but they do require an encoding clock. For more information, see the AN-877 Application Note, Interfacing with High Speed ADCs via SPI.

Channel/Chip Synchronization

The AD9600 has a sync input that provides the user with flexible sync options to sync internal blocks. The clock divider synchronization feature helps ensure synchronized sampling clocks between multiple ADCs. The SYNC input can also be used to synchronize the signal monitor block, allowing the characteristics of the input signal to be measured over a specific period of time. The input clock divider can synchronize at one occurrence or every occurrence of the synchronization signal. The signal monitor block synchronizes on each sync input signal.

The sync input is internally synchronized to the sample clock; however, to ensure that there are no timing uncertainties between multiple sections, the sync input signal should be externally synchronized to the input clock signal for the setup and hold times shown in Table 5. The sync input should be driven with a single-ended CMOS type signal.

Serial Port Interface (SPI)

The AD9600SPI allows the user to configure the converter for a specific function or operation through the structured register space provided within the ADC. This can provide users with additional flexibility and customization depending on the application. The address is accessed through the serial port and can be written or read through the port. Memory is organized into bytes, which can be further divided into fields, which are recorded in the memory-mapped section. For detailed operational information, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Configuration using SPI

There are three pins that define the SPI: SCLK, SDIO, and CSB (see Table 19). The SCLK pin is used to synchronize read and write data between ADCs. The SDIO pin is a dual purpose pin that allows data to be sent to and read from the internal ADC memory mapped registers. The CSB pin is an activelow control that enables or disables read and write cycling.

The falling edge of CSB and the rising edge of SCLK together determine the start of the frame. An example of serial timing and its definition can be found in Figure 72 and Table 5.

Other modes involving CSB are also available. CSB can be held low indefinitely, which will permanently enable the device; this is called streaming. CSB can be suspended high between bytes to allow for additional external timing. When CSB is tied high, the SPI function is put into high impedance mode. This mode turns on any auxiliary functions of the SPI pins.

In the command phase, a 16-bit command is sent. The data follows the instruction phase and its length is determined by the W0 and W1 bits. W0 and W1 represent the number of data bytes to be transferred for read or write. The value represented by W1:W0+1 is the number of bytes to transfer.

All data consists of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether to issue a read or write command. This allows the serial data input/output (SDIO) pins to change the input direction to the output direction.

In addition to word length, the instruction stage determines whether the serial frame is a read or write operation, allowing the serial port to be used to program the chip and read the contents of on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pins to change from input to output at the appropriate point in the serial frame.

Data can be sent in MSB first mode or LSB first mode. MSB first mode is the default mode at power-on and can be changed through the SPI port configuration register (address 0x00). For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

hardware interface

The pins described in Table 19 form the physical interface between the user programming device and the AD9600 serial port. When using the SPI interface, the SCLK pin and the CSB pin are used as inputs. The SDIO pins are bidirectional and act as inputs during the write phase and as outputs during readback.

The SPI interface is flexible enough to be controlled by FPGAs or microcontrollers. One SPI configuration method is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9600 to prevent these signals from transitioning at the converter inputs during critical sampling.

Some pins have dual functions when the SPI interface is not used. When pins are tied to AVDD or ground during device power-up, they are associated with specific functions. The Theory of Operation section describes the bundleable functions supported by the AD9600.

Configuration without SPI

In applications that do not interface with the SPI control registers, the SDIO/DCS pins, SCLK/DFS pins, SMI SDO/OEB pins, and SMI SCLK/PDWN pins serve as independent CMOScompatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, the CSB chip select should be tied to AVDD, which will disable the serial port interface.

SPI accessible functions

Table 21 briefly describes the general SPI-accessible features available on many analog devices, including high-speed ADCs, including the AD9600. These features are described in detail in the AN-877 application note, which interfaces to high-speed ADCs via SPI. The specific functional sections of the AD9600 parts are described in the Memory Mapped Register Descriptions.

memory map

read memory map

Each row in the memory-mapped register table (Table 22) has eight bit positions. The memory map is divided into four parts: Chip Configuration Registers (Address 0x00 to Address 0x02), Channel Index and Transfer Registers (Address 0x05 and Address 0xFF), ADC Function Register (Address 0x08 to Address 0x25), and Digital Features Control Register (Address 0x100 to address 0x11B).

The leftmost column of the memory map represents the register address number, and the default value is displayed in the second rightmost column. (MSB) Bit 7 column is the beginning of the given default hex value. For example, the default value of address 0x18 (VREF select register) is 0xC0, which means that bit 7 = 1, bit 6 = 1, and the remaining bits are 0. This setting is the default reference selection setting. The default value uses a 2.0 V peak-to-peak reference voltage. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers (from Register 0x100 to Register 0x11B) are documented in the Memory Mapped Register Descriptions section.

open location

All addresses and bit positions not included in Table 22 are not currently supported by this device. Unused bits in valid address locations should be written with 0. These locations only need to be written if part of the address location is open (for example, address 0x18). If the entire address location is open (for example, address 0x13), this address location should not be written.

Defaults

When the AD9600 comes out of reset, key registers are loaded with default values. The default values for the registers are given in the memory-mapped register table (Table 22).

logic level

Logic level terms are explained as follows:

• "Bit is set" is synonymous with "Bit is set to Logic 1", or "A logic 1 is being programmed for a bit."

• "Clear a bit" is synonymous with "bit is set to Logic 0", or "A logic 0 is being written to the bit."

transfer register map

Address 0x08 to address 0x18 are hidden. Writing to these addresses does not affect part of the operation until a transfer command is issued by writing 0x01 to address 0xFF and setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit (Bit 0 of Register 0xFF) is set. Internal updates occur when the transfer bit is set and the bit is automatically cleared.

channel-specific registers

Some channel setup functions, such as signal monitor thresholds, can be programmed individually for each channel. In these cases, the channel address location is repeated inside each channel. These registers are designated as local registers in Table 22 and can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, subsequent writes affect the registers of both channels. During a read cycle, only channel A or channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value of channel A.

On the other hand, registers designated as global registers in Table 22 affect entire sections or channel characteristics that are not allowed to be set independently between channels. The settings in Register 0x05 do not affect the global registers.

memory map

All addresses and bit positions not included in Table 22 are not currently supported by this device.

Memory Mapped Register Description

Refer to Application Note AN-877, Interfacing with High Speed ADCs via SPI, for information on the functions of Register 0x00 controls to Register 0xFF.

Synchronization Control (Register 0x100)

Bit 7 - Signal Monitor Sync Enable

Bit 7 enables the sync pulse from the external sync input to the Signal Monitor block. When both bit 7 and bit 0 are high, the sync signal is passed. This is continuous sync mode.

Bits[6:3] - reserved

Bit 2 clock divider, next sync only

If the Master Sync Enable bit (Address 0x100[0]) is high and the Clock Divider Sync Enable bit (Address 0x100[1]) is high, the Clock Divider Next Sync Only bit (Address 0x100[2]) allows the clock divider to synchronize to the first sync pulse it receives, and ignore the rest of the sync pulses. The clock divider synchronization enable bit (Address 0x100[1]) is reset after synchronization.

Bit 1 Clock Splitter Sync Enable

Bit 1 gates the sync pulse to the clock divider. When both bit 1 and bit 0 are high, the sync signal is passed. This is continuous sync mode.

Bit 0 Master Sync Enable

Bit 0 must be high to enable synchronization.

Fast Detect Control (Register 0x104) Bits[7:4] - Reserved

Bits[3:1] - fast detection mode selection

These bits set the mode of the fast detect output pins according to Table 14.

Bit 0 - Fast Detection Enable

Bit 0 is used to enable fast detect output pins. When the fast detect output pin is disabled, the output goes into a high impedance state. In LVDS mode, when fast detect output pins are interleaved, the output will go to high-Z only when both channels are off (power down/standby/output disabled). If only one channel is turned off (power down/standby/output disabled), the fast detect output pin will repeatedly activate the channel's data.

Coarse Upper Threshold (Register 0x105)

Bits[7:3] - reserved

Bits[2:0] - Coarse Upper Threshold

These bits set the level required to assert the coarse upper threshold indication (see Table 18).

Fine Upper Threshold (Register 0x106 and Register 0x107)

Register 0x106, Bits[7:0] - Fine Upper Threshold[7:0]

Register 0x107, Bits[7:5] - Reserved

Register 0x107, Bits[4:0] - Fine Upper Threshold[12:8]

These registers provide fine-grained upper thresholds. This 13-bit value is compared to the 10-bit amplitude from the ADC block. If the ADC amplitude exceeds this threshold, the output indicator is set.

Fine Lower Threshold (Register 0x108 and Register 0x109)

Register 0x108, Bits[7:0] - Fine Lower Threshold[7:0]

Register 0x109, Bits[7:5] - Reserved

Register 0x109, Bits[4:0] - Fine Lower Threshold[12:8]

These registers provide a good lower threshold. This 13-bit value is compared to the 10-bit amplitude from the ADC block. If the ADC amplitude is less than this threshold, the F_LT indicator is set.

Increase Gain Hold Time (Register 0x10A and Register 0x10B)

Register 0x10A, Bits[7:0] - Increase Gain Hold Time[7:0]

Register 0x10B, Bits[7:0] - Increase Gain Hold Time[15:8]

These registers are programmed with the dwell time in ADC clock cycles. The signal must be below the fine lower threshold before the Gain Increase (IG) indicator is acknowledged.

Signal Monitor DC Correction Control (Register 0x10C)

Bit 7—Reserved

Bit 6 - DC Correction Freeze

When bit 6 is set high, the dc correction is not updated to the signal monitor block; therefore, the block continues to hold its calculated last dc value.

Bits[5:2] - DC Correction Bandwidth

These bits set the averaging time for the DC correction function of the power monitor. This 4-bit word sets the bandwidth of the correction block according to the following equation:

where: k is the 4-bit value programmed in Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13).

fCLK is the AD9600 ADC sampling rate in Hertz.

Bit 1—DC Correction for Signal Path Enable

Setting Bit 1 high will add the output of the DC measurement block to the data in the signal path to remove the DC offset from the signal path.

Bit 0-DC correction for signal monitor enable

Bit 0 enables the DC correction function in the Signal Monitor block. DC correction is an averaging function that a signal monitor can use to remove DC offsets in a signal. Removing this direct current from the measurement results in a more accurate reading.

Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)

Register 0x10D, Bits[7:0] - DC Value Channel A[7:0]

Register 0x10E, Bits[7:6] - Reserved

Register 0x10E, Bits[5:0] - DC Value Channel A[13:8]

These read-only registers hold the latest dc offset value calculated by the channel A's signal monitor.

Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)

Register 0x10F Bits[7:0] - DC Value Channel B[7:0]

Register 0x110, Bits[7:6] - Reserved

Register 0x110, Bits[5:0] - DC Value Channel B[13:8]

These read-only registers hold the latest dc offset value calculated by the channel B's signal monitor.

Signal Monitor Motion Control (Register 0x111) Bit 7 - Reserved

Bit 6 - RMS/MS amplitude output enable

These bits make 20-bit rms or ms measurements into motion outputs.

Bit 5 Peak Detector Output Enable

Bit 5 enables 10-bit peak measurement as output on motion.

Bit 4 - Threshold Crossover Output Enable

Bit 4 enables the 10-bit threshold measurement as an output on motion.

Bits[3:2] - Motion SMI SCLK division

The value of these bits sets the division ratio of the motion SMI SCLK to the input clock. The value 0x01 set is divided by 2 (the default), the value 0x10 set is divided by 4, and the value 0x11 set is divided by 8.

Bit 1 - Motion SMI SCLK Sleep

Setting bit 1 high will cause the SMI SCLK to remain low when the signal monitor block has no data to transfer.

Bit 0 - Signal Monitor Motion Output Enable

When set, bit 0 causes the signal monitor's motion output to begin shifting the resulting data out of the signal monitor block.

Signal Monitor Control (Register 0x112)

Bit 7 - Complex Power Calculation Mode Enable

This mode assumes that I data appears on one channel and Q data appears on the other. The reported result is the composite power, measured as:

Bits[6:4] - reserved

Bit 3 Signal Monitor RMS/MS Select

Setting Bit 3 low selects the rms power measurement mode. Set bit 3 high to select ms power measurement mode.

Bits[2:1] - Signal Monitor Mode

Bits 2 and 1 set the signal monitor mode for the data output of Register 0x116 to Register 0x11B. Set Bits 2 and 1 to 00 to select the rms/ms amplitude output, set these bits to 01 to select the peak power output, and set Bit 1 to 10 or 11 to select the threshold crossing output.

Bit 0 - Signal Monitor Enable

Setting bit 0 high enables the signal monitor block.

Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0] - Signal Monitor Period[7:0]

Register 0x114, Bits[7:0] - Signal Monitor Period[15:8]

Register 0x115, Bits[7:0] - Signal Monitor Period[23:16]

This 24-bit value sets the number of clock cycles for the signal monitor to perform its operation. Although this register defaults to 64 (0x40), the minimum value for this register is 128 (0x80) cycles, and writing a value less than 128 may result in inaccurate results.

Signal Monitor Results Channel A (Register 0x116 to Register 0x118)

Register 0x116, Bits[7:0] - Signal Monitor Result Channel A[7:0]

Register 0x117, Bits[7:0] - Signal Monitor Result

Channel A[15:8]

Register 0x118, Bits[7:4] - Reserved

Register 0x118, Bits[3:0] - Signal Monitor Result

Channel A[19:16]

This 20-bit value contains the result calculated by the Signal Monitor block for Channel A. The content depends on the setting in Register 0x112, Bits[2:1].

Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)

Register 0x119, Bits[7:0] - Signal Monitor Result Channel B[7:0]

Register 0x11A, Bits[7:0] - Signal Monitor Results

Channel B[15:8]

Register 0x11B, Bits[7:4] - Reserved

Register 0x11B, Bits[3:0] - Signal Monitor Results

Channel B[19:16]

This 20-bit value contains the result computed by Channel B's Signal Monitor block. The content depends on the setting in Register 0x112, Bits[2:1].

application information

Design Guidelines

When designing the AD9600 into a system, designers should familiarize themselves with these guidelines before beginning design and layout, which discuss special circuit connections and layout requirements for specific pins.

Power and Grounding Recommendations

When connecting power supplies to the AD9600, designers should use two separate 1.8V supplies: one for AVDD and DVD, and one for DRVDD. AVDD and DVDD power supplies, although from the same source, should be isolated using ferrite beads or filter chokes and have separate decoupling capacitors. Users can use several different decoupling capacitors to cover high and low frequencies. These should be located close to the PC board level entry point and close to the part pins with the smallest trace length.

When using the AD9600, a single PC board ground plane should be sufficient. Optimum performance is easily achieved with proper decoupling and intelligent partitioning of the analog, digital, and clock sections of the PC board.

Exposed Blade Hot Slug Recommendations

For optimum electrical and thermal performance of the AD9600, the exposed baffle on the bottom of the ADC must be connected to analog ground (AGND). A continuously exposed (no solder shield) copper plane on the PCB should match the exposed blade pin 0 of the AD9600. Additionally, the copper plane should have multiple vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB, and these vias should be filled or stuffed with non-conductive epoxy.

To maximize coverage and adhesion between the ADC and the PCB, a silkscreen is required to divide the continuous plane on the PCB into several uniform sections. This provides several connection points between the ADC and the PCB during reflow. Using a continuous plane with no partitions ensures that there is only one connection point between the ADC and the PCB. Refer to the evaluation board layout diagrams (Figure 84 to Figure 91) for examples of PCB layouts. For more information on packaging and PCB layout for chip scale packages, see AN-772 Application Note, Design and Manufacturing Guidelines for Lead Frame Chip Scale Packages (LFCSP).

CML

The CML pin should be separated from ground using a 0.1µF capacitor, as shown in Figure 47.

Indian Rupee

The AD9600 requires the user to place a 10 kΩ resistor from the RBIAS pin to ground. This register sets the primary current reference for the ADC core and should have at least a 1% tolerance.

Reference decoupling

The VREF pin should be externally decoupled to ground in parallel with a low ESR 1.0µF capacitor and a 0.1µF ceramic low ESR capacitor.

SPI port

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade the converter's performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9600 to prevent converter inputs for these signals during critical sampling.

Evaluation Committee

The AD9600 evaluation board provides all the support circuitry required to operate the ADC in various modes and configurations. The converter can be driven differentially using a dual balun configuration (default) or the AD8352 differential driver. ADCs can also be driven single-ended. A separate power supply pin is provided to isolate the DUT from the AD8352 driver circuitry. Each input configuration can be selected by properly connecting different components (see Figure 74 to Figure 83). Figure 73 shows a typical bench characterization setup used to evaluate the ac performance of the AD9600.

Signal sources used for analog inputs and clocks with very low phase noise (<1ps rms jitter) are key to achieving optimum converter performance. To achieve the specified noise performance, the analog input signal also needs to be properly filtered to remove harmonics and reduce integrated or broadband noise at the input.

See Figure 74 through Figure 91 for complete schematics and layouts demonstrating routing and grounding techniques that should be applied at the system level.

power supply

The EV kit comes with a wall-mounted switching power supply that provides a maximum output of 6 volts, 2 amps. Connect the power source to a wall outlet rated for 100 VAC to 240 VAC at a frequency of 47 Hz to 63 Hz. The power output is a 2.1mm inner diameter circular jack that connects to J16's PCB. Once mounted on the PC board, the 6 V power supply will be blown and regulated before being connected to 6 low voltage drop linear regulators (providing proper bias for the various parts of the board).

The evaluation board can be operated with an external power supply by removing L1, L3, L4, and L13 to disconnect the voltage regulator provided by the switching power supply. This enables the user to individually bias each section of the board. Use P3 and P4 to connect a different power supply for each section. AVDD and DVDD require at least one 1.8v power supply with a current capacity of 1a; DRVDD recommends a separate 1.8v to 3.3v power supply. To operate the evaluation board with the AD8352 driver, a separate 5.0V supply (AMP VDD) and 1 A current capability are required. In order to operate the evaluation board with the alternate SPI option, a separate 3.3V analog power supply (VS) is required in addition to other power supplies. The 3.3V supply (VS) should also have 1A current capability. Using solder jumper SJ35 allows the user to separate AVDD and DVD if desired.

input signal

When connecting the clock and analog sources to the evaluation board, use a clean signal generator with low phase noise, such as a Rohde & Schwarz SMA100A or Agilent HP8644 signal generator or equivalent, and 1 m of shielded RG-58 50Ω coaxial cable. Enter the desired frequency and amplitude of the ADC. The AD9600 evaluation board for Analog Devices can accept a ~2.8V pp or 13dBm sine wave input. When connecting an analog input source, a multipole narrowband bandpass filter with 50Ω termination is recommended. TTE, Allen Avonics, and K&L Microwave offer good choices of such bandpass filters. If possible, connect the filter directly to the evaluation board.

Parallel CMOS outputs interface directly with analog

Device standard ADC data acquisition board (HSC-ADCEVALCZ). For more information on the ADC data acquisition board and its optional settings, visit /FIFO.

output signal

Default Action and Jumper Selection Settings

Below is a list of default and optional settings or modes allowed on the AD9600 evaluation board.

POWER

Connect the switching power supply provided with the evaluation kit between 47 Hz to 63 Hz and the P500's rated 100 V ac to 240 V ac wall outlet.

VIN

The evaluation board is set up for a double-balanced configuration analog input with an optimal 50Ω impedance match between 70MHz and 200MHz. For more bandwidth response, the differential capacitors on the analog inputs can be changed or removed (see Table 10). The common mode of the analog input is developed from the center tap of the transformer through the CML pin of the ADC (see the Analog Input Considerations section).

VREF

VREF was set to 1.0V by connecting the sense pins to ground and adding a jumper wire (pin 1 to pin 2) to header J5. This results in the ADC operating at 2.0 V pp full scale. To put the ADC in 1.0v pp mode (VREF=0.5v), a jumper should be placed on header J4. The evaluation committee also includes a separate external reference option. To use an external reference, connect pin 1 of J6 to pin 2 of J6 and provide an external reference at TP5. The Voltage Reference section details the proper use of the VREF option.

Indian Rupee

RBIA requires a 10 kΩ resistor (R503) to ground. This pin is used to set the ADC core bias current.

clock

The default clock input circuit is derived from a simple baluncoupled circuit using a high bandwidth 1:1 impedance ratio balun (T5) which adds a very low amount of jitter to the clock path. The clock input is terminated in 50Ω and AC coupled to handle single-ended sine wave inputs. The transformer converts the single-ended input to a differential signal, which is truncated before entering the ADC clock input. When using the AD9600 input clock divider, clock frequencies up to 625mhz can be input into the evaluation board through connector S5.

PDWN

To enable the power-down function, connect J7 and short the PDWN pin to AVDD.

Central Bank for Settlement

The CSB pin is pulled up internally, setting the chip to external pin mode to ignore SDIO and SCLK information. To connect the control of the CSB pin to the SPI circuit on the evaluation board, connect pin 1 of J21 to pin 2 of J21.

SCLK/DFS system

If the SPI port is in external pin mode, the SCLK/DFS pin sets the output data format. If the pin is left floating, the pin will pull down internally, setting the default data format condition to offset binary. Connecting Pin 1 of J2 to Pin 2 of J2 sets the format to two's complement. If the SPI port is in serial pin mode, connect pin 2 of J2 to pin 3 of J2 to connect the SCLK pin to the onboard SPI circuit (see the Serial Port Interface (SPI) section).

SDIO/DCS system

If the SPI port is in external pin mode, the SDIO/DCS pin action sets the duty cycle stabilizer. If the pin is left floating, the pin is pulled up internally, setting the default condition to "enable DCS". To disable DCS, connect pin 1 to pin 2. If the SPI port is in serial pin mode, connect pin 2 of J1 to pin 3 of J1 to connect the SDIO pin to the onboard SPI circuit (see the Serial Port Interface (SPI) section).

Alternate Clock Configuration

Two clocking options are available on the AD9600 evaluation board. The first option is to use an on-board crystal oscillator (Y1) to provide the clock input to the part. To make this crystal work, resistors R8 (0Ω) and R85 (10 kΩ) should be installed and resistors R82 and R30 should be removed.

The second option is to use a differential LVPECL clock and use the AD9516-4 (U2) to drive the ADC input. When using this option, the AD9516-4 priming pump filter assembly needs to be filled (see Figure 78). See the AD9516-4 data sheet for more information.

To configure the clock input (from S5) to drive the AD9516 reference input instead of directly driving the ADC, the following components need to be added, removed, and/or changed.

1. Delete R32, R33, R99, and R101 in the default clock path.

2. Fill C78 and C79 with 0.001µF capacitors and R78 and R79 with 0Ω resistors in the clock path.

Additionally, the unused AD9516 outputs (one lvd and one LVPECL) are routed to optional connectors S8 through S11 on the evaluation board.

Alternative analog input driver configuration

This section provides a brief description of an alternative analog input driver configuration using the AD8352. When using this drive option, some additional components need to be populated. For more details on the AD8352 differential driver, including its operation and optional pin settings, see the AD8352 data sheet.

To configure the analog input to drive the AD8352 instead of the default transformer option, the following components need to be added, removed, and/or changed for Channel A. In addition, the corresponding components of channel B should be changed.

1. Delete C1, C17, C18 and C117 in the default analog input path.

2. Fill C8 and C9 with 0.1µF capacitors in the analog input path. To drive the AD8352 in differential input mode, fill in transformer T10; resistors R1, R37, R39, R126, and R127; and capacitors C10, C11, and C125.

3. Populate the optional amplifier output path with the desired components, including an optional low-pass filter. Install 0Ω resistors R44 and R48. Resistors R43 and R47 should be increased (typically 100Ω) to increase the output impedance shown by the AD8352 to 200Ω.

Evaluation Board Layout

Dimensions

[1] Measured with a low input frequency, full-scale sine wave with approximately 5 pF load on each output bit.

[2] Input capacitance refers to the effective capacitance between a differential input pin and AGND. The equivalent analog input structure is shown in Figure 8.

[3] Standby power was measured using DC input, CLK+ and CLK- pins inactive) set to AVDD or AGND.

[4] For complete definitions, see the AN-835 application note for high-speed ADC testing and evaluation.

[5] Crosstalk measured at 100 MHz with -1 dBFS on one channel and no input on alternate channel.

[6] Measure the output propagation delay from 50% transition of CLK+ and CLK- pins to 50% transition of output data pin under 5 pF load.

[7] The wake-up time depends on the value of the decoupling capacitor.