feature

Signal-to-Noise Ratio = 60.6dbc (61.6dbfs) to 70mhz, 150ms/sec; SFDR = 81dBc to 70MHz, 150ms/sec; Low Power: 825mW at 150MSPS; 1.8V Analog Supply Operation; 1.8V To 3.3 V CMOS output power supply or 1.8 V LVDS power supply; integer 1 to 8 input clock divider; IF (IF) sampling frequency up to 450 MHz; internal analog-to-digital converter (ADC) voltage reference; integrated ADC sample and hold input; flexible Analog Inputs: 1 V pp to 2 V pp range; 650 MHz bandwidth differential analog input; ADC clock duty cycle stabilizer; 95 dB channel isolation/crosstalk; serial port control; user-configurable built-in self-test (BIST ) function; energy saving power-down mode; integrated receive function; fast detection/threshold bit; composite signal monitor.

application

Point-to-point radio receivers (GPSK, QAM); diversity radio systems; I/Q demodulation systems; smart antenna systems; digital predistortion; general software radio; broadband data applications; data acquisition; nondestructive testing.

Product Highlights

1. Integrated dual 10-bit 150 MSPS/125 MSPS/105 MSPS analog-to-digital converters.

2. Fast over-range detection and serial output signal monitoring.

3. Signal monitor block with dedicated serial output mode.

4. Proprietary differential input maintains good SNR performance at input frequencies up to 450mhz.

5. The AD9600 is powered by a 1.8V power supply and has a separate digital output drive power supply to accommodate 1.8V to 3.3V logic families.

6. The standard serial port interface supports various product features and functions, such as data formatting (offset binary, two's complement or gray coding), enabling clock DCS, power down mode and voltage reference mode.

7. The AD9600 is compatible with the AD9627-11, AD9627 and AD9640, allowing easy migration from 10-bit to 11-bit, 12-bit or 14-bit.

General Instructions

The AD9600 is a dual 10-bit 105 MSPS/125 MSPS/150 MSPS ADC. It is designed to support communication applications requiring low cost, small size and versatility.

The dual ADC core adopts a multi-stage differential pipeline structure and integrates output error correction logic. Each ADC features a wideband, differential sample-and-hold analog input amplifier that supports multiple user-selectable input ranges. An integrated voltage reference simplifies design considerations. A duty cycle stabilizer is provided to compensate for changes in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The AD9600 has several features that simplify the automatic gain control (AGC) function in communication receivers. For example, the fast detection feature allows four bits of input stage information to be output with very short delays, enabling fast overrange detection.

In addition, the programmable threshold detector allows monitoring the amplitude of the input signal with short delays using the ADC's four fast detect bits. If the input signal level exceeds a programmable threshold, the fine upper threshold indicator goes high. Since this threshold is set from four msb, the user can quickly adjust the system gain to avoid overrange conditions.

Another AGC-related function of the AD9600 is the signal monitor. This block allows the user to monitor the composite amplitude of the input signal, which helps to set the gain to optimize the dynamic range of the overall system.

ADC output data can be routed directly to two external 10-bit output ports. These outputs can be programmed from 1.8 V to 3.3 V CMOS or 1.8 V LVD. In addition, flexible power-off options provide significant power savings.

Equivalent Circuit

Typical performance characteristics

AVDD=1.8 V, DVDD=1.8 V, DRVDD=3.3 V, sample rate=150 MSPS, DCS enabled, 1 V internal reference, 2 V pp differential input, VIN=-1.0 dBFS, 64k samples, T=25°C, Unless otherwise indicated.

theory of operation

The AD9600 dual ADC design can be used for signal diversity reception, where the ADCs operate identically on the same carrier, but from two separate antennas. ADCs can also be operated with separate analog inputs. The user can use appropriate low-pass or band-pass filtering at the ADC input to sample any f/2 frequency band from dc to 200mhz with little loss of ADC performance. While allowing analog input operation up to 450mhz, the ADC distortion increases as frequencies approach the higher end of the range.

In non-dispersive applications, the AD9600 can be used as a baseband receiver with one ADC for the I input data and the other for the Q input data.

A synchronization function is provided to allow timing to be synchronized across multiple channels or multiple devices.

Programming and control of the AD9600 is accomplished using a 3-bit SPI-compatible serial interface.

ADC Architecture

The AD9600 architecture consists of a dual front-end sample-and-hold amplifier (SHA) and a pipelined switched-capacitor ADC. In the digital correction logic, the quantized outputs from each stage are combined into a final 10-bit result. The pipelined architecture allows the first stage to operate on new input samples, while the remaining stages operate on previous samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline (excluding the last stage) consists of a low-resolution flash ADC connected to a switched-capacitor digital-to-analog converter (DAC) and an interstage residual amplifier (a multiplying digital-to-analog converter (MDAC)). The residual amplifier amplifies the difference between the reconstructed DAC output and the flash input in the next stage of the pipeline. One bit redundancy is used per stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage of each channel contains a differential SHA that can be ac or dc coupled in differential or single-ended mode. The output scratch block aligns the data, corrects errors, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted. During power down, the output buffers go into a high impedance state.

Analog Input Considerations

The analog input to the AD9600 is a differential switched capacitor SHA designed for optimum performance when dealing with differential input signals.

The clock signal alternately switches the SHA between sample mode and hold mode (see Figure 45). When the SHA switches to sampling mode, the signal source must be able to charge and stabilize the sampling capacitor within half a clock cycle. Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. A parallel capacitor can be placed at the input to provide dynamic charging current. This passive network creates a low-pass filter at the input of the ADC; therefore, the exact value depends on the application.

In undersampling (if sampling) applications, any parallel capacitors should be reduced. Combined with the drive source impedance, the shunt capacitor limits the input bandwidth. See AN-742 Application Note, Frequency Domain Response of Switched Capacitor ADCs; AN-827 Application Note, A Resonance Method for Interfacing a Switched Capacitor to Amplifier ADC Corporation and the Analog Dialogue article "Transformer-Coupled Front Ends for Wideband A/D Converters" (p. Volume 39, April 2005) for more information. In general, the exact value depends on the application.

For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched.

An internal differential reference buffer generates positive and negative reference voltages that define the input range of the ADC core. The span of the ADC core is set by the buffer to be 2 × VREF.

Input common mode

The analog inputs of the AD9600 have no internal dc bias. Therefore, in AC-coupled applications, the user must provide this bias externally. Set the device to V=0.55×AVDD for best performance, but the device can operate over a wider range with reasonable performance (see Figure 44). An on-board common-mode voltage reference is included in the design, available from the CML pin. When the common mode analog input voltage is set by the CML pin voltage (usually 0.55 × AVDD). The CML pin must be separated from ground by a 0.1µF capacitor, as described in the Applications Information section.

Differential Input Configuration

Best performance is achieved when driving the AD9600 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and flexible interface to ADCs. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9600 (see Figure 46), and the driver can be configured in a Sallen key filter topology to limit the frequency band of the input signal.

For baseband applications where signal-to-noise ratio is a critical parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 47. The CML voltage can be connected to the center tap of the transformer secondary winding to bias the analog input.

Signal characteristics must be considered when selecting a transformer. Most RF transformers have saturation frequencies below a few megahertz. Excessive signal power can cause the core to saturate, resulting in distortion.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is insufficient to achieve the true SNR performance of the AD9600. For applications where signal-to-noise ratio is a critical parameter, differential double balun coupling is recommended. An example is shown in Figure 49.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is insufficient to achieve the true SNR performance of the AD9600. For applications where signal-to-noise ratio is a critical parameter, differential double balun coupling is recommended. An alternative to using a transformer-coupled input at the frequency of the second Nyquist zone is exemplified by using the AD8352 differential driver. An example is shown in Figure 50. See the AD8352 data sheet for more information.

In any configuration, the value of the shunt capacitor C depends on the input frequency and source impedance and may need to be reduced or removed. Table 10 lists suggested values for setting up the RC network. However, the actual value depends on the input signal; therefore, Table 10 should only be used as a starting guide.

Single-ended input configuration

Single-ended inputs can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance is degraded due to the large input common mode swing. If the source impedances at each input are matched, there should be little impact on the SNR performance. Figure 48 details a typical single-ended input configuration.

voltage reference

A stable and accurate voltage reference is built into the AD9600. The input range can be adjusted by changing the reference voltage applied to the AD9600, using the internal reference voltage or an externally applied reference voltage. The input range of the ADC tracks linear changes in the reference voltage. This section summarizes the various reference modes. The Reference Decoupling section describes the best PCB layout practices for reference.

Internal reference connection

The comparator within the AD9600 senses the potential at the sense pin and configures the reference into four possible modes, as shown in Table 11. If the sensor is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 51), setting VREF to 1.0 V. Connecting the sensor pin to VREF switches the reference amplifier output to the sensor pin, completing the loop and providing a 0.5 V reference output. As shown in Figure 52, if the resistor divider is connected outside the chip, the switch will again select the sense pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

If the AD9600's internal reference is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 53 depicts the effect of the load on the internal reference voltage.

Xref Operations

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 54 shows the typical drift characteristics of the internal reference in 1.0V mode.

When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 15). Internal buffers generate positive and negative full-scale references for the ADC core. Therefore, the external reference voltage must be limited to 1.0V maximum.

Clock Input Considerations

For best performance, the AD9600 sample clock inputs (CLK+ and CLK-) should be clocked with differential signals. Signals are typically AC coupled to the CLK+ and CLK- pins through transformers or capacitors. These pins are internally biased (see Figure 55) and do not require external biasing.

Clock input options

The AD9600 has a very flexible clock input structure. The clock input can be CMOS, LVDS, LVPECL, or a sine wave signal.

Regardless of the type of signal used, the jitter of the clock source is of greatest concern, as described in the Jitter Considerations section.

Figure 56 and Figure 57 show the preferred method of clocking the AD9600 (clock frequencies up to 625 MHz). Low-jitter clock sources use RF baluns or RF transformers to convert from single-ended to differential signals.

For clock frequencies between 125 MHz and 625 MHz, an RF balun configuration is recommended; for clock frequencies between 10 MHz and 200 MHz, an RF transformer is recommended. The clock skew of the AD9600 is limited to approximately 0.8V pp differential by a secondary transformer or balun's back-to-back Schottky diodes.

This helps prevent large voltage fluctuations of the clock from being fed through the rest of the AD9600, while maintaining fast rise and fall times for signals that are critical for low jitter performance.

If a low-jitter clock source is not available, another option is to AC-couple the differential PECL signal to the sampling clock input pins, as shown in Figure 58. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers have excellent jitter performance.

A third option is to AC couple the differential LVDS signal to the sample clock input pins, as shown in Figure 59. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers have excellent jitter performance.

In some applications, a single-ended CMOS signal can be used to drive the sample clock input. In this application, CLK+ should be driven directly from the CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 60). Although the CLK+ input circuit power supply is AVDD (1.8 V), this input is designed to tolerate input voltages up to 3.6 V, thus providing a variety of options for driving logic voltages.

input clock divider

The AD9600 includes an input clock divider capable of dividing the input clock by an integer value between 1 and 8. If a distribution ratio other than 1 is selected, the duty cycle stabilizer will automatically be enabled.

The AD9600 clock divider can be synchronized using an external synchronization input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after a register write. A valid synchronization causes the clock divider to reset to its initial state. This synchronization feature allows the clock dividers of multiple devices to be aligned to ensure simultaneous input sampling.

clock duty cycle

A typical high-speed ADC uses two clock edges to generate various internal timing signals. Therefore, these ADCs may be sensitive to the clock duty cycle. Typically, a ±5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics. The AD9600 contains a duty cycle stabilizer (DC) that retimes the non-sampling (or falling) edges to provide an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9600. When the SDIO/DCS pins are used as DCS, the noise and distortion performance is nearly flat over a wide range of duty cycles, as shown in Figure 43.

Jitter on the rising edge of the input is an important issue that is not reduced by the internal stabilization circuit. The duty cycle control loop is generally not suitable for clock frequencies less than 20 MHz. If the clock rate may change dynamically, the time constant associated with the loop needs to be considered. This requires a 1.5µs to 5µs latency after the dynamic clock frequency is increased or decreased before the DCS loop relocks to the input signal. During this time, the loop is unlocked, the DCS loop is bypassed, and the internal device timing depends on the duty cycle of the input clock signal. In this application, the operating clock stabilizer can be appropriately disabled. In all other applications, it is recommended to enable the DCS circuit to maximize AC performance.

Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given input frequency (f), the drop in signal-to-noise ratio due to jitter (t) can be calculated as:

In this equation, rms aperture jitter represents the root mean square of all jitter sources, including clock input, analog input signal, and ADC aperture jitter. If the undersampling application is particularly sensitive to jitter (see Figure 62).

In situations where aperture jitter may affect the dynamic range of the AD9600, the clock input should be treated as an analog signal. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock source. If the clock was generated from another type of source (by gating, division, or other methods), it should be retimed with the original clock in the last step.

See the AN-501 application note and AN-756 application note for more in-depth information on the jitter performance of the ADC.

Power Consumption and Standby Modes

As shown in Figure 63, the power consumed by the AD9600 is proportional to its sampling rate. In CMOS output mode, the digital power consumption depends primarily on the strength of the digital drivers and the load on each output bit.

The maximum DRVDD current (I) can be calculated as:

where N is the number of output bits (22 in the case of the AD9600 with fast detect output pins disabled).

This maximum current occurs when each output bit switches on every clock cycle, i.e. a full-scale square wave at the Nyquist frequency f/2. In practical applications, the DRVDD current is determined by the switching quantity of the average output bits, which is determined by the sampling rate and the characteristics of the analog input signal. Reducing the capacitive loading of the output driver can minimize digital power consumption. The data in Figure 63 was acquired under the same operating conditions as the typical performance characteristics, with a 5 pF load on each output driver.

By asserting PDWN mode (either through the SPI port or by asserting the PDWN pin high), the AD9600 is put into power-down mode. In this state, the ADC typically dissipates 2.5mW. When powered down, the output drivers are in a high impedance state. Asserting the PDWN pin low returns the AD9600 to its normal operating mode. Note that PDWN refers to the digital output drive power supply (DRVDD), which should not be exceeded.

In power-down mode, low power consumption is achieved by turning off the reference, reference buffer, bias network, and clock. Internal capacitors are discharged when entering power-down mode and must be recharged when normal operation resumes. Therefore, the wake-up time is related to the time spent in power-down mode: the shorter the power-down period, the shorter the wake-up time.

When using the SPI port interface, the user can place the ADC in power-down or standby mode. Standby mode allows the user to keep the internal reference circuit powered up when a faster wake-up time is required. See the Memory Mapped Register Descriptions section for details.

digital output

The AD9600 output driver can be configured to interface with 1.8 V to 3.3 V logic families by matching DRVDD to the digital supply of the interface logic.

In CMOS output mode, the output drivers are sized to provide enough output current to drive various logic families. However, large drive currents tend to cause current glitches on the power supply and can affect the performance of the converter. Applications that require the ADC to drive large capacitive loads or large sectorized outputs may require external buffers or latches.

When operating in external pin mode, the output data format can be selected for offset binary or two's complement by setting the SCLK/DFS pin (see Table 12). As described in the Memory Mapped Register Description section, when using SPI control, the data format can be selected for offset binary, two's complement, or gray code.

Digital output enable function (OEB)

The AD9600 has flexible tri-state capability for digital output pins. Tri-state mode can be enabled by using the SMI SDO/OEB pin or the SPI interface. If the SMI SDO/OEB pin is low, the output data driver is enabled. If the SMI SDO/OEB pin is high, the output data driver is in a high impedance state. This output enable function is not intended for fast access to the data bus. Note that OEB refers to the digital output driver supply (DRVDD) and should not exceed this supply voltage.

When the device uses the SPI interface, the data and fast detect output pins for each channel can be independently asserted three times by using the output enable bar bit in Register 0x14.

opportunity

The AD9600 provides latched data with a pipeline delay of 12 clock cycles. The data output is available one propagation delay (t) after the rising edge of the clock signal.

The length and loading of the output data lines should be minimized to reduce transients within the AD9600. These transients degrade the dynamic performance of the converter. The minimum typical conversion rate of the AD9600 is typically 10 MSPS. Dynamic performance may degrade when clock rates are below 10ms/sec.

Data Clock Out (DCO)

The AD9600 provides two data clock output (DCO) signals for capturing data in external registers. Data output is valid on the rising edge of DCO unless polarity is changed via SPI. See the timing diagrams shown in Figure 2 and Figure 3 for more information.

ADC overrange and gain control

In receiver applications, it is desirable to have a mechanism to reliably determine when the converter will be clipped. The standard overflow indicator provides post-mortem information about the state of the analog input, but its usefulness is limited. Therefore, it is helpful to have a programmable threshold below full scale that allows the time to reduce the gain before clipping actually occurs. Furthermore, since the input signal can have a significant slew rate, the latency of this function is a major concern. Highly pipelined converters can have significant delays. A good compromise is to use the output bits of the first stage of the ADC for this function. The latency of these output bits is very low and the overall resolution is not high. Peak input signals are typically between 6dB and 10dB below full scale to full scale. A 3-bit or 4-bit output provides sufficient range and resolution for this function.

Through the SPI port, the user can provide a threshold above which the overrange output will be activated. The output should remain low as long as the signal is below this threshold. The fast detect output pins can also be programmed through the SPI port so that one of the pins can act as a legacy overrange pin for customers currently using this feature. In this mode, all 12 bits of the converter are checked in the traditional way, and the output is high in what is usually defined as overflow. In either mode, the size of the data (but not the sign of the data) is considered when evaluating the condition. Threshold detection responds equally to positive and negative signals outside the expected amplitude range.

Quick Test Overview

The AD9600 contains circuitry that facilitates fast overrange detection, allowing a very flexible implementation of external gain control. Each ADC has four fast detect output pins that output information about the current state of the ADC's input levels. The function of these pins is programmable through the fast detect mode select bits and fast detect enable bits in Register 0x104, allowing range information to be output from multiple points in the internal datapath. Depending on the programmable threshold levels, these pins can also be programmed to indicate if an overrange or overrange condition exists. Table 14 shows the six configurations that can be used for fast detect pins.

1. The fast detection pins configured in CMOS mode are FD0A/FD0B to FD9A/FD9B, and the fast detection pins configured in LVDS mode are FD0+/FD0- to FD9+/FD9-.

2. See the ADC Overrange (OR) and Gain Switch section for more information on OR, C_UT, F_UT, F_LT, IG, and DG.

ADC fast amplitude

When the fast detect output pin is configured to output ADC fast amplitude (ie, when the fast detect mode select bit is set to 0b000), the information presented is from having only a two clock cycle delay (in CMOS output mode) ADC levels of early converter stages. Using the fast detect output pin in this configuration provides the earliest indication of the liquid level. Since this information is provided early in the data path, there is significant uncertainty in the level indicated. Table 15 shows the nominal levels as well as the uncertainty shown by the ADC fast amplitude.

A subset of the fast detect output pins are available when the fast detect mode select bits are set to 0b001, 0b010, or 0b011. In these modes, the fast detect output pins have a delay of 6 clock cycles. Table 16 shows the corresponding ADC input levels when the fast detect mode select bits are set to 0b001 (that is, when the ADC fast amplitude is displayed on the FD[3:1] pins).

When the fast detect mode select bits are set to 0b010 or 0b011 (ie, when ADC fast amplitude is present on the FD[3:2] pins), no LSB is provided. The input range for this mode is shown in Table 17.

ADC overrange (or)

The ADC overrange indicator is asserted when overrange is detected at the ADC input. The overrange condition is determined at the output of the ADC pipeline and is therefore subject to a 12 clock cycle delay. An input overrange will be indicated by this bit 12 clock cycles after it occurs.

Gain switch

The AD9600 includes circuitry useful in applications where a large dynamic range is present or where gain ranging converters are used. This circuit allows digital thresholds to be set so that upper and lower thresholds can be programmed. Fast detect mode select bits=010 to fast detect mode select bits=101 support various combinations of gain switching options.

One use is to detect when the ADC will reach full scale under certain input conditions. The result is an indicator that can be used to quickly insert the attenuator to prevent the ADC from overdriving.

Coarse Threshold (C_UT)

The coarse upper threshold indicator is asserted if the ADC fast amplitude input level is greater than the level[2:0] programmed in the coarse upper threshold register at Address 0x105. The coarse upper threshold output is output two clock cycles after the input exceeds the level, thus providing a quick indication of the input signal level. A rough upper threshold value is shown in Table 18. This indicator remains asserted for at least two ADC clock cycles, or until the signal falls below the threshold level.

Fine Upper Threshold (F_UT)

If the input volume exceeds the value programmed in the Fine Upper Threshold Register located at Address 0x106 and Address 0x107, the Fine Upper Threshold Indicator is asserted. Compare the 13-bit threshold register with the signal amplitude at the ADC output. This comparison is affected by the ADC clock delay, but is accurate in terms of converter resolution. The fine threshold size is defined by the following equation:

Fine Lower Limit (F_LT)

The fine lower threshold indicator is asserted if the input magnitude is less than the value programmed in the fine lower threshold registers at Address 0x108 and Address 0x109. The Fine Low Threshold Register is a 13-bit register that is compared to the amplitude of the signal output by the ADC. This comparison is affected by the ADC clock delay, but provides an accurate comparison with the converter resolution. The fine threshold size is defined in Equation 1.

The operation of the F_UT and F_LT indicators is shown in Figure 66.

Incremental Gain (IG) and Decrement Gain (DG)

The incremental gain and decremented gain indicators are designed to be used together to provide information for external gain control. The Decrement Gain Indicator works with the Coarse Upper Threshold bit and is asserted when the input magnitude is greater than the 3-bit value in the Coarse Upper Threshold register (Address 0x105). Similarly, the incremental gain indicator corresponds to the fine lower threshold bit, but the incremental gain indicator is only asserted when the input amount is less than the value programmed in the fine lower threshold register after the dwell time has elapsed. This pause time is set by the 16-bit Gain Increase Pause Time registers (Address 0x10A and Address 0x10B) and is in units of ADC input clock cycles, ranging from 1 to 65535. The Fine Low Threshold Register is a 13-bit register that is compared to the amplitude of the ADC output. This comparison is affected by the ADC clock delay, but allows for a finer, more precise comparison. The fine threshold size is defined in Equation 1 (see the Fine Upper Threshold (F_UT) section).

The attenuation gain output is affected by the fast detect output pin, which provides a quick indication of a potential overrange condition. The assertion of the incremental gain indicator is based on a comparison at the ADC output, requiring the input amplitude to remain below a precisely programmable level for a predefined period of time before signaling an external circuit to increase the gain.

The operation of the IG and DG indicators is shown in Figure 66.