Features

Very low power consumption:

– At VDD=5V, typically 1 m

Ability to operate in astable mode

CMOS output capable of rail-to-rail swing

High output current capability

– Sink : 100mA typical

– Power supply: 10mA typical

Outputs are fully compatible with CMOS, TTL and MOS

Low supply current reduces peaking during output transitions

Single Supply Operation from 2V to 15V

Functionally interchangeable with the NE555 ; has the same pins

– High reliability automotive applications – Configuration control and printing support

– Compliant with automotive standards

application

precise timing

pulse generation

sequential timing

Delay generation

pulse width modulation

pulse position modulation

Linear Ramp Generator

sketch

Overview

The TLC555 is a precision timing device for general purpose timing applications up to 2.1 MHz.

Functional block diagram

Pin numbers apply to all packages except FK packages. A reset can override TRIG, which can override THRES.

Feature description

Monostable operation

For monostable operation, any of these timers can be connected as shown in Figure 3. If the output is low, apply a negative going pulse on the flip-flop (TRIG), set the flip-flop (Q goes low), drive the output high, then turn off Q1. The capacitor C is then charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG returns high, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges from C to Q1.

Monostable Operation Circuit

When the trigger voltage is below the trigger threshold, monostable operation is initiated. Once started, the sequence ends only if TRIG is up to at least 10 microseconds before the end of the timing interval. When the flip-flop is grounded, the comparator can store up to 10 microseconds, which limits the minimum monostable pulse width to 10 microseconds. Due to the threshold level and saturation voltage of Q1, the output pulse duration is approximately tw = 1.1 RAC. Figure 4 is a graph of the time constants for different RA and C values. Both the threshold level and the charge rate are proportional to the supply voltage VCC. Therefore, the timing interval is independent of the supply voltage as long as the supply voltage remains constant over the time interval.

Simultaneous application of negative-going trigger pulses to reset and trigger during timed intervals, starting from the positive edge of the reset pulse, discharges C and reinitializes the cycle. The output remains low as long as the reset pulse is low. To prevent false triggering, it must be connected to VCC when reset is not used.

Stable operation

Adding a second resistor, RB, to the circuit of Figure 3 and connecting the trigger input to the threshold input causes the timer to fire automatically and operate as a multivibrator. Capacitor C is charged through RA and RB and then discharged through RB only. Therefore, the duty cycle is controlled by the values of RA and RB.

This unstable connection causes capacitor C to charge and discharge between the threshold voltage level (≈0.67 × VCC) and the trigger voltage level (≈0.33 × VCC). In a monostable circuit, the charge and discharge times (hence, frequency and duty cycle) are independent of the supply voltage.

Decoupling the control voltage from ground with a capacitor can improve operation. This should be evaluated for individual applications.

Note A: Decoupling the control voltage from ground with a capacitor can improve operation. This should be evaluated for individual applications.

Typical Unstable Waveform

Trigger and Threshold Voltage Waveforms

Typical waveforms generated during astable operation. The output high-level duration tH and low-level duration tL can be calculated as follows:

Application Information

The TLC555 timer device uses resistor and capacitor charge delays to provide programmable time delays or operating frequencies. This section provides a simplified discussion of the design process. typical application

typical application

Missing Pulse Detector

Circuits can be used to detect missing pulses in a series of pulses or abnormally long intervals between consecutive pulses. As long as the pulse interval is less than the timing interval, the timing interval of the monostable circuit is continuously retriggered by the input pulse train. Long pulse intervals, missing pulses, or terminated pulse trains allow timed intervals to be completed

Missing pulse detection circuit

Design requirements

Input fault (missing pulse) must be input high. Since the timing capacitor (C) remains discharged, there is no way to detect that the input is stuck low.

Detailed design procedure

Select RA and C so that RA×C>[Max Normal Input High Time]. RL improves VOH, but it's not required

TTL compatibility.

Apply Curve

Missing Pulse Detector Complete Timing Waveform

pulse width modulation

The operation of the timer can be modified by adjusting the internal threshold and trigger voltage, which is done by applying an external voltage (or current) to CONT. Figure 14 shows the circuit used for pulse width modulation. The continuous input pulse train triggers the monostable circuit, and the control signal modulates the threshold voltage. Figure 15 shows the resulting output pulse width modulation. When displaying a sine wave modulated signal, any waveform can be used.

VDD (5V to 15V)

Note A: The modulating signal can be directly or capacitively coupled to continuous. For direct coupling, the effect of modulation source voltage and impedance on timer bias should be considered.

The modulation signal can be coupled directly or capacitively to the controller. For direct coupling, consider the effect of modulation source voltage and impedance on timer bias.

Pulse Width Modulation Circuit

Design requirements

The VOL and VOH levels of the clock input must be less than and greater than 1/3vdd, respectively. The modulation input can be changed from ground to VDD. The application must tolerate non-linear transfer functions; the relationship between modulation input and pulse width is not linear because the capacitive charge is based on the RC of a negative exponential curve.

Detailed design procedure

Choose RA and C so that RA×C=1/4[cycle of clock input]. RL improves VOH, but TTL compatibility doesn't require it.

Apply Curve

Pulse Width Modulation Waveform

pulse position modulation

Any of these timers can be used as a pulse position modulator. This application adjusts the threshold voltage and thus the time delay of the free-running oscillator. Figure 17 shows the triangular wave modulated signal for such a circuit; however, any waveform can be used.

Note A: The modulating signal can be directly or capacitively coupled to continuous. For direct coupling, the effect of modulation source voltage and impedance on timer bias should be considered.

The modulation signal can be coupled directly or capacitively to the controller. For direct coupling, consider the effect of modulation source voltage and impedance on timer bias.

Pulse Position Modulation Circuit

Design requirements

Both DC and AC coupled modulation inputs change the upper and lower voltage thresholds of the timing capacitors. Both frequency and duty cycle vary with modulation voltage.

Detailed design procedure

The nominal output frequency and duty cycle can be determined using the equations in . RL improves VOH, but TTL compatibility doesn't require it. 9.2.3.3 Application Curve Unstable Operation

Pulse Position Modulation Waveform

sequence timer

Many applications, such as computers, require signals for initialization conditions during startup. Other applications, such as test equipment, require sequential activation of test signals. These timing circuits can be connected to provide this sequential control. Timers can be used in various combinations of unstable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 18 shows a sequencer circuit that may be used in many systems

Note A: S turns off instantaneously at t=0.

S closes instantaneously at t=0.

Sequence timer circuit

Design requirements

A sequential timer application links together multiple monostable timers. The connecting elements are 33-kΩ resistors and 0.001-µF capacitors. An output high-to-low edge delivers a 10-µs start pulse to the next monostable.

Detailed design procedure

The selection formula of timing resistor and timing capacitor is: tw=1.1×R×C.

Apply Curve

Timing Timer Waveform

Power Recommendations

The TLC555 requires 2 V to 15 V. Sufficient power supply bypassing is required to protect associated circuits. The minimum recommended value is 0.1-µF ceramic in parallel with 1-µF electrolysis. Place bypass capacitors as close to the TLC555 as possible and minimize trace length.

Layout Guidelines

Standard PCB rules apply to the routing of the TLC555. The 0.1µF ceramic capacitor in parallel with the 1µF electrolytic capacitor must be as close to the TLC555 as possible. The capacitor used for the delay must also be placed as close as possible to the discharge pin. The ground plane of the bottom layer can provide better noise immunity and signal integrity.

Basic layout for various applications.

C1 is based on delay calculation

C2-0.01-µF Bypass Capacitor for Control Voltage Pin

C3-0.1-µF Bypass Ceramic Capacitor

C4-1-µF Electrolytic Bypass Capacitor

R1 based on delay calculation