The ISL6565A, ISL6565B control the microprocessor core to drive up to three synchronous rectified voltage-regulated parallel buck channels. The polyphase buck converter architecture uses interleaving timing to multiply the channel ripple frequency and reduce input and output ripple currents. The difference between the ISL6565A and the ISL6565B is that the ISL6565A utilizes Radio Data System (ON) current sensing, while the ISL6565B uses DCR current sensing for each phase. These cost- and space-saving methods of current sensing are used for adaptive voltage positioning (droop), channel current balancing, and overcurrent protection. To ensure droop accuracy, a programmable internal temperature compensation function is used to compensate for the effects of rDS(ON) and DCR temperature sensitivity. A unity gain differential amplifier is provided for remote voltage sensing. Any potential difference between the remotes is eliminated by the remotes with local interference amplifiers. Accuracy Threshold Sensitive Enable Input is available for precise coordination of the ISL6565A, ISL6565B with Intersil MOSFET driver chip. Dynamic Video 8482 ; technology allows seamless real-time video changes. Offset pins allow precise voltage offset settings independent of video settings

feature

Multiphase power conversion - 2 or 3 phase operation

Accurate Core Voltage Regulation - Differential Remote Sensing Voltage - 0.5% System Accuracy Over Temperature and Lifetime - Adjustable Reference Voltage Offset

Accurate rDS (on) or DCR current sensing - Integrated programmable temperature compensation - Accurate load line programming - Accurate channel current balancing - Low cost, lossless current sensing

Input Voltage: 12V or 5V Bias

Microprocessor Voltage Identification Input - Dynamic VID® Technology - 6 Bit Video Input - 0.8375V to 1.600V in 12.5mV steps

Threshold enablement for precise sorting

overcurrent protection

Over voltage protection

digital soft start

Operating frequency up to 1.5MHz per phase

QFN Package - JEDEC PUB95 MO-220QFN Compliant - Quad Planar Leadless - Package Outline - Near Chip Scale Package for Improved PCB Efficiency and Thinner Profile

Lead free available

Absolute Maximum Ratings

Supply voltage, VCC. +7V

Input, output or I/O voltage (except OVP). Ground -0.3V to VCC+0.3V

Overvoltage. +15V

mannequin. >4kV

ESD (machine model). > 300V

ESD (charging unit model). >2kV

operating conditions

Supply voltage, VCC (5V bias mode). +5V±5%

junction temperature. 0°C to 125°C

Hot information

Thermal resistance θJA (°C/W) θJC (°C/W)

SOIC package (Note 1). 62 Not applicable

QFN package (Note 2, 3). 33 3.5

TSSOP package (Note 1). 85 knives

maximum junction temperature. 150 degrees Celsius

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius (SOIC - lead only)

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

1. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air. See Technical Bulletin TB379 for details.

2. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct-attach" characteristics. See Technical Bulletin TB379.

3. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Electrical Specifications Operating Conditions: VCC=5V or ICC<25mA (Note 3), TJ=0°C to 105°C. unless otherwise specified.

Electrical Specifications Operating Conditions: VCC=5V or ICC<25mA (Note 3), TJ=0°C to 105°C. unless otherwise specified. (continued)

notes:

4. When using the internal shunt regulator, VCC is clamped to 6.02V (max). Current must be limited to 25mA or less.

5. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

6. During soft start, VDAC rises from 0 to VID. Overvoltage trip levels are 1.7V and VDAC+0.2V.

Function pin description

VCC - Provides all power needed to operate the chip. When the voltage on this pin exceeds the rising POR threshold, and the voltage on this pin falls below the falling POR threshold. Connect this pin directly to the +5V supply or through a series of 300Ω resistors to the +12V supply. GND—The bias and reference ground of the integrated circuit. EN - This pin is the controller. Provides a method for synchronizing the power-up of the controller and MOSFET driver chips through appropriate resistor dividers. When EN voltage is higher than 1.31V, ISL6565A, ISL6565B fault state according to ENLL, internal POR and pending. Driving below 1.14V will clear all fault fault states and start the ISL6565A, ISL6565B until soft start is re-enabled. ENLL - This pin is the controller. When asserted logic high, the ISL6565 is active input based on the state of EN, internal POR, VID and a pending fault state. Release all fault states of the balance and start the ISL6565A, ISL6565B as soft start when re-enabled. FS - A resistor, from FS to ground, will set the switching frequency. Refer to Equation 45 for the correct resistor calculation. Video 4, Video 3, Video 2, Video 1, Video 0, and Video 12.5 - These are the input and output adjustment voltages for the internal DACs that provide the reference. Connect these pins to open-drain outputs with or without external pull-up resistors or to activate pull-up outputs. VID4-VID12.5 have 20µA when the voltage is above logic high. VDIFF, VSEN, and RGND - VSEN and RGND are precision differential sense amplifiers. This amplifier converts the differential voltage output of the remote control to a single-ended voltage referenced to local ground. VDIFF is the output of the amplifier and the input of the regulator and protection circuit. Connect VSEN and RGND to the pins that sense remote loads. The input and output inversions of the FB and COMP-errors are amplified, respectively. FB goes through a resistor. Negative current, proportional to the output current, appears on the FB pin. Appropriately sized resistors VDIFF and FB set the load line (droop). The droop scale factor is set by the ratio of the ISEN resistance and the lower resistance MOSFET rDS(ON) or inductor DCR. COMP is tied to FB compensated by an external RC network

The REF-REF input pin is the wrong positive input amp. It goes through a 1kΩ resistor. Reference pin and ground to smooth voltage transitions during Dynamic Video™ operation. TCOMP - Temperature Compensated Scaling Input. A resistor from this pin to ground sets the internal temperature sensing circuit. Used by the controller to modify the droop current output to the FB pin for regulating MOSFET rDS(ON) and inductor DCR with temperature. PWM1, PWM2, PWM3—Pulse width modulation output. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3. Connect PWM3 to VCC to configure two-phase operation. ISEN1, ISEN2, ISEN3, ICOMON (ISL6565B only) - These pins are used to sense a single phase output ocean current. Induced current is used for channel balancing, protection and load line regulation. ISEN3 should be left open for 2-phase operation. For radio data system (ON) current sensing using the ISL6565A, connect resistors between ISEN1, ISEN2, and ISEN3 pins to their respective phase nodes. This resistor sets a conduction interval for a current proportional to the current in the lower MOSFET. For DCR sensing using the ISL6565B, connect a resistor from VCORE to the icomon pin. Then connect ISEN1, ISEN2 and ISEN3 to the components around each phase inductance at the node between RC sense. PGOOD-PGOOD is used to end soft-start. It is a sinking logic output with low impedance until soft-start is complete. It will be pulled once the undervoltage point is reached and lowered again. The OFS-OFS pin provides a way to program the dc current by drooping a resistor between FB and VDIFF that produces an offset voltage. The offset current is a voltage reference generated by external resistors and internal precision resistors. The polarity of the offset is determined by connecting a resistor to GND or VCC. If there is no offset the OFS pin should be left unconnected. Overvoltage protection pin. This is an open channel device that can be configured externally with a resistor controlled thyristor shutdown regulator

operate

Multiphase Power Conversion

The microprocessor load current profile has been changed to point out that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing single-phase converters are both cost-effective and thermally feasible forcing a shift to a multi-stage cost-saving approach. The ISL6565A, ISL6565B controllers help simplify the implementation of minimal output components by integrating important functions and requirements. The block diagrams on pages 2 and 3 provide top-level views of polyphase power conversion using the ISL6565A and ISL6565B controllers.

The switching of each channel in a polyphase converter is a symmetrical out-of-phase channel with respect to each other. In a three-phase converter, each channel switches 1/3 of the loop after the previous channel, while tracking the channel. Therefore, the combined ripple frequency of the three-phase converter is higher than the ripple frequency of any one phase. Furthermore, the peak-to-peak amplitude reduction of the combined inductor current is proportional to the number of phases (Equations 1 and 2). Ripple frequency increases and ripple amplitude decreases. Designers can use less inductance per channel and lower total output capacitance specifications for any performance. Figure 1 illustrates the frequency of the multiplication effect of the output ripple. The three channel currents (IL1, IL2 and IL3) are combined to form the AC ripple current and the DC load current. The ripple of the ripple component is the frequency of the current in each channel. Each PWM pulse in the previous stage. The peak-to-peak current per phase is about 7A, and the DC component of the inductor current combines to deliver the goods. To understand the ripple current amplitude in a polyphase circuit, examine the peak-to-peak inductor current representing a single channel.

In Equation 1, VIN and VOUT are the input and output voltages, L is the single-channel inductance value, and fS is the switching frequency. The output capacitor conducts the inductor current. In the case of multiphase converters the capacitive current is per individual channel. Combine Equation 1 with the expression for the peak-to-peak current after summing N symmetrically phase-shifted inductor current Equation 2. The peak-to-peak ripple current is reduced by an amount proportional to the number of channels. The output voltage ripple is a function of capacitance, equivalent series resistance (ESR) and inductor ripple current. Reducing inductor ripple current allows designers to use fewer or less expensive output capacitors.

Another benefit of interleaving is reducing input ripple current. The input capacitor section is determined by the maximum input ripple current. Multiphase topologies can increase overall system cost and scale by reducing input ripple, enabling designers to reduce the cost of input capacitors. The example in Figure 2 demonstrates the current total input ripple current into a three-phase converter. The converter shown in Figure 2 delivers 1.5V from a 12V input to a 36A load. The rms input capacitor current is 5.9A. Compare this to a single phase converter for the same buck = 12V to 1.5V at 36A. The single-phase converter has 11.9A rms input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current, and the capacity is equivalent to that of the three-phase converter.

Figures 19 and 20 in the section titled "Input Capacitors" can be used to determine the input capacitor RMS based on load current, duty cycle and channel selection. in determining the optimal input capacitance solution. The timing of the PWM operation of each converter branch is determined by the active channel. The default channel setting for ISL6565A, ISL6565B is 3. A switching cycle is defined as the time between PWM1 pulse termination signals. This pulse termination signal is the signal that the internally generated clock triggers the falling edge of PWM1. The cycle time pulse termination signal is the inverse of the switch frequency set by a resistor between the FS pin and ground. When commanded by the clock signal, PWM1 goes low at the beginning of each cycle. The PWM1 transition sends a signal to Channel 1 to turn off the MOSFET driver for the upper MOSFET of Channel 1 and to turn on the synchronous MOSFET of Channel 1. In the default channel configuration, the PWM2 pulse terminates 1/3 of the period after the PWM1 pulse. The PWM3 pulse terminates 1/3 of a period after PWM2. If PWM3 is connected to VCC, the PWM2 pulse is terminated 1/2 cycle after the dual-channel operation is selected and the PWM1 pulse is terminated. Once a PWM pulse transitions low, it will remain low for a minimum of 1/3 cycle. Forced off-time requirements ensure accurate current samples. Current sensing is described in the next section. When the forced off time expires, the PWM output will be enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the sawtooth ramp as shown in Figure 6. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output is highly transitioned. The MOSFET driver detects the state of the PWM signal and turns off the MOSFET above it synchronously. The PWM signal starts the next cycle by triggering a low PWM signal at the end of pulse signal mark.

Current sampling

During the forced off time, the current sense amplifier reproduces a signal proportional to the inductor current using the ISEN input after a low voltage pulse width modulation transition. Regardless of the current sensing method, the induced current (ISEN) is just the inductive current. The example window opens exactly for the switching period, tSW, after the PWM transitions low. The example window will then remain open for a fixed time, tsamples, equal to 1/6 of the switching period, tSW as shown in Figure 3.

The sampling current is proportional to the inductor current at the end of the sampling and is held until the next switching cycle sample. The sampled current is used for current balancing, load line regulation, and overcurrent protection.

Current sensing

The ISL6565A supports MOSFET rDS(ON) current sensing, while the ISL6565B supports inductive DCR current sensing. The internal circuits shown in Figures 4 and 5 represent the n-channels of the n-channel converter. This circuit is repeated for each channel in the converter, but cannot be activated based on the state of the PWM3 pin, as described in the "Pulse Width Modulation Operation" section. MOSFET rDS(ON) Sensing (ISL6565A only) The ISL6565A senses the voltage across the MOSFET rDS(ON) under the channel load current by sampling, as shown in Figure 4. A ground referenced op amp, internally to the ISL6565A, rises through a resistor. The rising voltage is equivalent to the voltage drop across the rDS(ON) of the lower MOSFET when it is conducting. The resulting current into the ISEN pin is proportional to the channel current. The Eisen Current is sampled as described in the Current Sampling and Hold section. As can be seen in Figure 4, the following formula for In is where IL is the channel current.

Inductor DCR sensing (ISL6565B only) The inductor winding has a distributed characteristic resistance or DCR (Direct Current Resistance). For simplicity, the inductive DCR is considered an independent lumped quantity, as shown in Figure 5. The channel current IL flows through the inductor, through the DCR. Equation 5 shows the s-domain equivalent voltage, VL, across the inductor.

A simple RC network extracting the DCR voltage across the inductors (R1 and C) is shown in Figure 5. The voltage across the sense capacitor, VC, can be shown to be proportional to the channel current IL as shown in Equation 6

In some cases it may be necessary to use a resistor divider RC network to sense current through the inductor. This can be done by placing a second resistor, R2, across the sensing capacitor. In these cases, the voltage across the sensing capacitor, VC, is related to the channel current IL and the resistor divider ratio K.

If the RC network component is selected, the RC time constant matches the inductor L/DCR time constant, and VC is equal to the ratio of DCR times the resistor divider, K. If the resistor divider is not used, the value of K is 1.

The capacitor voltage VC then rises across the sense resistor. The regulator should have only one connection from the VOUT plane to the ICimon pin. through the rising current and the inductor current. Equation 9 shows the resistor divider ratio between the channel current and the sense current (ISEN) driven by the value of the selected sense resistor, the DCR of the inductor.

Channel current balances the sampled current from each active channel, In sum divided by the number of active channels. The resulting circulating average current, IAVG, is supplied to the converter for each switching cycle. Channel currents are calculated by comparing the circulating average currents for each channel and making errors based on them. Intersil's patented current balancing method is shown in Figure 6 for error correction for channel 1. In the figure, the circulating average current is sampled with channel 1, I1, to create an error signal. The IER filtered error signal changes the pulse width by the VCOMP command to correct any imbalance and force closer to zero. The same method of correction of the error signal is applied to each active channel.

Channel current balance is a key advantage of multiphase operation to achieve thermal balance. The heat generated is transferred across multiple devices and over a large area. Designers avoided driving multiple parallel MOSFETs, as well as using heat sinks and non-standard magnetic materials. The voltage regulation integrated compensation network shown in Figure 7 ensures that the steady-state error of the output voltage is limited to the error of the reference voltage (offset error of the output and OFS current sources, telemetry and error amplifiers. Intersil specifies that the guaranteed tolerances for the ISL6565A, ISL6565B include these Combination tolerance of the elements. The output of the error amplifier VCOMP and a sawtooth wave that produces a pulse width modulated signal. The pulse width modulated signal controls the internal MOSFET driver and regulates the converter output to a specified reference voltage. Controls internal and external circuit voltage regulation such as Figure 7. The ISL6565 integrates an internal differential remote sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output with respect to the voltage at the controller ground reference to obtain a more accurate sensed output method voltage. Connect the microprocessor sense pin to the remote control amplifier. The remote sense output, VDIFF, is through an external resistor.

A digital-to-analog converter (DAC) generates a reference signal voltage based on the logic signal state on pin VID4 through Section 12.5. The DAC decodes the 6-bit logic signal (VID) into a discrete voltage as shown in Table 1. Each VID input provides a 20µA pull-up to an internal 2.5V supply for open-drain outputs. The pull-up current is decremented to zero above the logic threshold to protect voltage-sensitive output devices. External pull-up resistors can increase the current of the pull-up current source into the drive device greater than 20 microamps during leakage.