The ISL6414 is an ultra-low noise triple output LDO regulator with a microprocessor reset circuit and is designed to power wireless chipsets. The IC accepts input voltages ranging from 3.0V to 3.6V and provides three regulated output voltages: 1.8V (LDO1), 2.84V (LDO2) and another ultra-high voltage clean 2.84V (LDO3). On-chip logic provides sequencing of voltage outputs between LDO1 and LDO2 for BBP/MAC and I/O power supplies. The LDO3's ultra-low noise typically exceeds 30µV RMS to help the VCO stabilize. The high level of integration and thin quad-flat-lead-free (QFN) package makes the ISL6414 the ideal choice for many of today's small industry standard wireless network cards such as PCMCIA, mini-PCI and Cardbus-32. The ISL6414 uses internal PMOS transistors as channel devices. The SHDN pin controls the LDO1 and LDO2 outputs and SHDN3 controls the LDO3 output. Internal voltage sequencing ensures that the LDO1 output (1.8V supply) is always stable until LDO2 is turned on. When powered off, the power to LDO2 is disconnected before the output of LDO1 is turned off. The ISL6414 also integrates a reset function, which does not require an additional reset IC which is required in WLAN applications. The IC requires a reset to signal when the VIN supply voltage falls below a preset threshold, and remains above the reset threshold for at least 25 ms after the VIN (VIN). The output fault detection circuit indicates that LDO1 is out of regulation. Other features include overcurrent protection, thermal shutdown and reverse battery protection

feature

Small DC/DC Converter - Three LDOs and Low Profile Reset Circuit in 4x4mm QFN Package

High Output Current - LDO1, 1.8V. 500mA - LDO2, 2.84V. 300mA - LDO3, 2.84V . 200 mA

Ultra Low Voltage Drop - LDO2, 2.84 volts. 125mV (typ) at 300mA - LDO3, 2.84V. 100 mV at 200 mA (typ)

Ultra-low output voltage noise - <30μVRMS (typ) for LDO3 (VCO supply)

Small ceramic output capacitor, stable performance

Voltage Sequencing for BBP/MAC and Analog Power Supplies

Extensive protection and monitoring functions - overcurrent and short circuit protection - thermal shutdown - reverse battery protection - fault indicator

Logic Control Dual Shutdown Pins

Integrated microprocessor reset circuit - programmable reset delay - free reset output

Proven reference design solution for the entire WLAN system

QFN Package Option - Compliant with JEDEC PUB95 MO-220 QFN - Four Level Apartment

No Potential Customers - Product Overview - Near Chip Scale Package Size Improves PCB Performance Efficiency and Thinner Profile

Lead-free plus annealed (RoHS compliant) available

application

PRISM®3, PRISM Gas Turbine™, and PRISM WWR Chipsets

WLAN Card - PCMCIA, Cardbus32, Micro PCI Card - Small Flash Card

hand-held musical instrument

Absolute Maximum Ratings (Note 1) Thermal Information

VIN, SHDN/SHDN3 to GND/GND3. -7.0V to 7.0V

Set, CC, Fault to GND/GND3. -0.3V to 7.0V

Output current (continuous)

LDO1. 500 mA

LDO2. 300 mA

LDO3. 200 mA

Electrostatic discharge classification. Level 1

Thermal Resistance (Typical Notes 2, 3) θJA (°C/W) θJC (°C/W)

QFN package. 46 8.0

Maximum connection temperature (plastic packaging). -55°C to 150°C

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius

range of working temperature. -40°C to 85°C

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

1. All voltages are related to ground.

2. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct-attach" characteristics.

3. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Electrical Specifications VIN=+3.3V, Compensation Capacitor=33nF, TA=25°C unless otherwise stated.

Electrical Specifications VIN=+3.3V Unless otherwise stated Electrical Specifications VIN=+3.3V, Compensation Capacitor=33nF, TA=25°C. (continued), compensation capacitor = 33nF, TA = 25°C.

notes:

4. Specifications at -40°C are guaranteed by design/characterization, not production testing.

5. When VOUT is 50mV below the VOUT value of VIN=VOUT+0.5V, the voltage drop is defined as VIN-VOUT.

6. The reset time has a linear relationship with CT with a slope of 2.5ms/nF. Therefore, at 10nF (0.01μF), the reset time is 25ms; at 100nF (0.1μF), the reset time of 25ms is 250ms.

7. Guaranteed by design, not production tested.

8. The design of LDO1 is guaranteed to be within the regulation range of the minimum input voltage of 2.7V.

Pin Description

OUT1—This pin is the output of LDO1. Bypass to 2.2µF minimum, low ESR capacitor to ground stable operation. VIN - Power input pin. Connect input power. Bypass to ground with a 2.2µF capacitor. The two VINs must be tied to the PC board, close to the IC. GND—The ground pin for LDO1 and LDO2. CC1—compensation capacitor for LDO1. Connect a 0.033µF capacitor from CC1 to GND. SHDN - Shutdown input for LDO1 and LDO2. connected to for normal operation. Drive the SHDN pin low to turn off LDO1 and LDO2. Output 2 - This pin is the output of LDO2. Bypass to 2.2µF minimum, low ESR capacitor to ground stable operation. CT - Timing pin to reset the pulse width of the circuit. CC2—LDO2 compensation capacitor. Connect a 0.033µF capacitor from CC2 to GND. OUT3—This pin outputs LDO3. Bypass minimum 2.2μF, low ESR capacitor to GND3, stable operation. GND3 - Ground pin for LDO3. CC3—LDO3 compensation capacitor. Connect a 0.033µF capacitor from CC3 to GND3. Shutdown input for SHDN3-LDO3. The connected VIN operates normally. Driving the SHDN3 pin low turns off LDO3. Fault - This is the power good indicator for LDO1. when? The 1.8V output is out of regulation (>?5%, typ), this pin goes low. During heating, this pin also goes low for shutdown and any overcurrent events on LDO1. Connect this pin to ground if not used. This pin is in shutdown mode and is controlled by the SHDN pin (see Figure 19)

RESET - This pin is a push-pull active low output stage of the integrated reset supervisory circuit. This reset circuit monitors the VIN and here asserts the reset output pin if the VIN falls below the reset threshold. Reset When the VIN pin voltage falls below the reset threshold, at least 25 ms after the VIN rises above the reset threshold. RESET - This pin is a push-pull active high output stage of the integrated reset supervisory circuit. This reset circuit monitors the VIN and here asserts the reset output pin if the VIN falls below the reset threshold. Reset When the VIN pin voltage is below the reset threshold, at least 25ms after the VIN rises above the reset threshold.

Function description

The ISL6414 is a 3-in-1 multi-output, low-dropout regulator designed for wireless chipset power applications. It offers three fixed output voltages 1.8V, 2.84V and 2.84V. The 1.8V output from LDO1 remains active (minimum) at VIN=2.7V, ensuring proper BBP/MAC operation. Each LDO includes 1.2V reference voltage, error amplifier, MOSFET driver, P-Channel pass transistor, dual-mode comparator and internal feedback divider. The 1.2V bandgap reference is connected to the inverting input of the error amplifier. The error amplifier compares this against the selected feedback voltage and amplifies the difference. The MOSFET driver reads the error signal and applies the appropriate driver to the P-channel channel transistor. If the feedback voltage is lower, the reference voltage, the pass transistor gate is pulled low, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage through the transistor gate drive, less current is allowed to pass to the output. The output voltage is connected to the output 1/2/3 pins through an internal resistor divider. Additional blocks include output overcurrent protection, reverse battery protection, thermal sensor, fault detector, reset function and shutdown logic. Internal P-Channel Pass Transistor The ISL6414 has a typical 0.5Ω rDS(on) P-Channel MOSFET pass transistor. This provides several advantages over similar designs using PNP bipolar transistors. This P-channel MOSFET does not require base drive, which reduces quiescent current considerably. PNP-based regulators waste when the pass transistor saturates. They also use high base drive current for bulk cargo. Island 6414 is not affected by these

Internal P-channel pass transistor

The ISL6414 has a typical 0.5ΩrDS(on) P-channel MOSFET pass transistor. This provides several advantages over similar designs using PNP bipolar transistors. This P-channel MOSFET does not require base drive, which reduces quiescent current considerably. PNP-based regulators waste when the pass transistor saturates. They also use high base drive current for bulk cargo. Island 6414 is not affected by these issues. Integrated Reset for MAC/Baseband Processor The ISL6414 includes a microprocessor supervisory block. This block eliminates additional reset ICs and components required for external wireless chipset applications. This block performs a single function; it asserts the reset signal when the VIN supply voltage falls below a preset threshold, keeping it asserted for a programmable time (set via an external capacitor CT) when the VIN pin voltage rises above the reset threshold. The push-pull output stage of the reset circuit provides low and high outputs. This function is guaranteed to be in the correct state when the VIN drops to 1V. The reset comparator is designed to ignore transients on the VIN pin. The reset threshold of the ISL6414 is typically 2.63V. Except during power-up, power-down, and power-down conditions, this block is relatively immune to short duration negative VIN transients/faults.

The output voltage

The ISL6414 provides a fixed output voltage for wireless chipset applications. An internal trim resistor network sets the typical output voltage as follows: VOUT1=1.8V; VOUT2=2.84V; VOUT3=2.84V. Shutdown driving the SHDN input low puts both LDO1 and LDO2 into shutdown mode. Drive SHDN3 input low and output LDO3 in shutdown mode. Pulling the SHDN and SHDN3 pins low at the same time puts the entire chip into shutdown mode and the supply current typically drops to 5µA. The SHDN and SHDN3 inputs have internal pull-up resistors, so the output is always enabled for normal operation; no external pull-up resistors are required. Using the SHDN pin in shutdown mode, the fault output will remain high (see Figure 19). Current Limit The ISL6414 monitors and controls the gate voltage through the transistor to limit the output current. The current limit is 550mA for LDO1, 330mA for LDO2, and 250mA for LDO3. The output can be shorted to ground without damaging the part due to current limiting and thermal protection features. Thermal Overload Protection Thermal overload protection limits total power consumption to 6414 islands. When the junction temperature (TJ) exceeds +150°C, the thermal sensor sends a signal to shutdown logic, turning off the transistor and allowing the IC to be cool. When the IC is powered up, the transistor is turned on again and the junction temperature is typically cooled by 20°C, resulting in a pulsed output condition during continuous thermal overload. Thermal overload protection protects the ISL6414 from fault conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of +150°C. Operating Area and Power Dissipation The maximum power dissipation of the ISL6414 depends on the thermal resistance of the IC package and the board, the thermal resistance of the die joints and the ambient temperature difference between the air and the air flow rate. The energy in the device is: The maximum power dissipation is: Pmax=(TJMAX–TA)/θJA In the formula, TJMAX=150°C, TA=ambient temperature, θJA is the thermal resistance from the connector to the surrounding environment The ISL6414 package is characterized by its underside. This pad lowers the package die by providing a direct thermal conduction path to the computer board. In addition, the ground (GND/GND3) of island 6414 performs the electrical connection that provides system grounding and heat dissipation away. Connect the exposed backside pads and ground to using a large pad or ground plane, or through multiple vias to the ground plane layer.

reverse input protection

The ISL6414 has a unique protection scheme that limits the reverse supply current to less than 1 mA below ground when the VIN drops. The circuit monitors the polarity of these two pins, disconnecting the internal circuit and parasitic diodes when the applied voltage is reversed. This feature prevents the device from overheating or damaging the installed input power supply. The integrator circuit ISL6414 uses an external 33nF compensation capacitor to minimize load and line regulation errors, as well as reduce output noise. When the output voltage changes due to load current or input voltage, the integrator capacitor voltage is raised or lowered to compensate for the system offset of the error amplifier. Compensation is when the device loses power, current limit, or thermal shutdown. Fault Detection Circuit The fault pin monitors LDO1 output regulation, as well as current limiting, thermal shutdown, and other fault conditions. If the LDO1 output is out of regulation ±5.5% (typ). During shutdown mode, using the SHDN pin, the fault output will remain high (see Figure 19).

application information

Capacitor Selection and Regulator Stability Capacitors are required at the input and output of the ISL6414 for stable operation over the entire load range. Use a capacitor larger than 1µF on the input 6414 island. The input capacitor reduces the source impedance to the input power supply. Larger capacitor values provide better PSRR and line transient response with lower ESR. The input capacitor must be located no more than 0.5 inches away from the IC's VIN pin and return to a clean analog ground. Any high quality ceramic or tantalum can be used as the input capacitor. The output capacitors must meet the capacitances of all three LDOs and the ESRISL6414 is specifically designed for small ceramic output capacitors. The ESR of the output capacitor affects the stability of the output noise. Use output capacitors with an ESR of ISL6414 size 11 50mΩ or lower to ensure stability and best transient response. For stable operation, a ceramic capacitor is recommended for VOUT1 with a minimum of 3.3µF 300mA output current and 2.2µF is recommended for VOUT2 at 200mA load current for each output 3. There is no upper limit to the output capacitor value. Larger capacitor tank reduces noise, improves load transient response and stability and PSRR. The output capacitor should be very close to supplying the pin to the PC board inductance and should return to a clean analog ground. The minimum input to output voltage difference (or voltage drop) of the input to output voltage regulator determines the minimum usable supply voltage. In battery-operated systems, this determines the battery's useful end-of-life voltage. Because the ISL6414 uses a P-channel MOSFET pass transistor, its leakage voltage is rDS(on) (typically 0.5) times the load current. Noise, PSSR, and Transient Response The ISL6414 is designed for good noise, transient response, and AC rejection with low dropout operation maintaining voltage and low quiescent current. Running from a noise source, improving power supply noise rejection and transient response can be achieved by increasing the value of input and output bypass capacitors and through passive filtering techniques. The load transient response diagram of ISL6414 is shown in application description AN1080. Overshoot can be reduced by increasing the output capacitor value and decreasing the ESR.