feature

• Complete front end for bridge sensors

• Internal amplifier, gain 128

• Internal oscillator

• Bridge sensor low side power switch

• Low Noise: 35nVrms

• Selectable data rate: 10SPS or 80SPS

• Simultaneous suppression of 50 Hz and 60 Hz 10SPS

• Input EMI filter

• External voltage reference up to 5V for ratiometric measurements

• Simple pin-driven control

• Two-wire serial digital interface

• Power supply range: 3V to 5.3V

•Package: SOIC-16

• Temperature range: –40°C to +85°C

application

•scale

• Strain gauges

• Load cell

• Industrial process control

illustrate

The ADS1231 is a precision 24-bit analog-to-digital converter (ADC). The ADS1231 features an on-board low noise amplifier, on-board oscillator, precision third-order 24-bit delta-sigma (Δ-sigma) modulator, and bridge power switch for bridge sensor applications (including scales, strain gauges, and load cells) A complete front-end solution is provided.

The LNA has a gain of 128 and supports a full-scale differential input of ±19.5mV. The ΔΣ ADC has 24-bit resolution and consists of a third-order modulator and a fourth-order digital filter. Two data rates are supported: 10SPS (simultaneous rejection of 50 Hz and 60 Hz) and 80SPS. The ADS1231 can be in a low-power standby mode or completely shut down in shutdown mode.

The ADS1231 is controlled by dedicated pins; there are no programmable digital registers. Data is output through an easily isolated serial interface that connects directly to the MSP430 and other microcontrollers.

The ADS1231 is available in an SO-16 package and has a temperature range of -40°C to +85°C.

Absolute Maximum Ratings

Outside operating free air temperature range unless otherwise specified.

(1) Stresses exceeding the absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and do not imply functional operation of the device under these or any other conditions. Long-term exposure to absolute maximum rating conditions may affect device reliability.

(2) Note: ESD sensitive devices. Precautions should be taken when handling equipment to prevent permanent damage.

Noise performance

The ADS1231 has excellent noise performance. Table 1 summarizes the typical noise performance when the input is externally shorted for different data rates and voltage references.

RMS and peak-to-peak noise refer to the input. The effective number of bits (ENOB) is defined as: ENOB=ln(FSR/RMS noise)/ln(2)

Noise-free bits are defined as: Noise-free bits = ln(FSR/peak-to-peak noise)/ln(2)

Where: FSR (full-scale range) = VREF/gain.

Typical features

At TA=+25°C, AVDD=DVDD=REFP=5V, REFN=GND, VCM=2.5V, unless otherwise noted.

Overview

The ADS1231 is a precision 24-bit ADC that includes a low noise PGA, internal oscillator, third-order deltasigma (ΔΣ) modulator, and fourth-order digital filter. The ADS1231 provides a complete front-end solution for bridge sensor applications such as load cells, strain gauges, and pressure sensors.

Data can be output at 10SPS for superior 50Hz and 60Hz rejection, or at 80SPS when higher speeds are required. The ADS1231 is easy to configure, and all digital control is done through dedicated pins; no registers are programmable. A simple two-wire serial interface retrieves data.

Analog Inputs (AINP, AINN)

Apply the input signal to be measured to input pins AINP and AINN. The ADS1231 accepts differential input signals, but can also measure unipolar signals.

low noise amplifier

The ADS1231 uses a low drift, low noise amplifier to provide a complete front-end solution for bridged sensors. A simplified diagram of the amplifier is shown in Figure 13. It consists of two chopper-stabilized amplifiers (A1 and A2) and three precisely matched resistors (R1, RF1, and RF2) that form a differential front-end stage with a gain of 128, followed by gain stage A3 (gain = 1 ). The input is equipped with an EMI filter, as shown in Figure 13. The cutoff frequency of the EMI filter is 20MHz. With AVDD as the reference input, the bipolar input range is -19.5mV to +19.5mV. The inputs of the ADS1231 are protected by internal diodes connected to the supply rails. These diodes clamp the applied signal to prevent it from damaging the input circuit.

external capacitor

The external capacitors (CEXT) on the two ADS1231 cap pins combine with the internal resistor RINT (onchip) to form a low pass filter. The recommended value for CEXT is 0.1µF and the corner frequency is 720Hz. This low pass filter serves two purposes. First, the input signal is band-limited to prevent aliasing from the ADC and to filter out high-frequency noise. Second, it attenuates the chopping residue of the amplifier to improve temperature drift performance. NPO or C0G capacitors are recommended. For best performance, place external capacitors very close to the cover feet.

Voltage Reference Inputs (VREFP, VREFN)

The voltage reference used by the modulator is generated by the voltage difference between VREFP and VREFN: VREF=VREFP–VREFN. This reference input has a structure similar to that of an analog input. In order to improve the reference input impedance, a switch buffer circuit is used to reduce the input equivalent capacitance. Reference drift and noise affect ADC performance. For best results, pay close attention to the reference noise and drift specifications. A simplified diagram of the circuit on the reference input is shown in Figure 14. Switches and capacitors can be approximately modeled with effective impedance ZEFF=500MW.

ESD diode protection reference input. To prevent these diodes from energizing, make sure the voltage on the reference pin is no more than 100mV below GND, and likewise, not more than 100mV from AVDD:

GND – 100mV < (VREFP or VREFN) < AVDD +100mV

Low Voltage Power Switch (SW)

The ADS1231 contains an internal switch for bridging the sensor externally, as shown in Figure 15. This switch can be used for the return path of a bridge power supply. By opening the switch, the power dissipation in the bridge is eliminated. The switches are controlled by the ADS1231 conversion state. During normal conversion, the switch is closed (switch pin is grounded). In standby or power-down mode, the switch is open (switch pins are high impedance). When using a switch, it is recommended to connect the negative reference input (VREFN) directly to the bridge ground terminal, as shown in Figure 15, for best performance.

clock source

The ADS1231 can use the internal oscillator or an external clock source to suit a variety of applications. Figure 16 shows the equivalent circuit of the clock module. The CLK_Detect block determines whether to apply an external clock signal to the CLKIN pin in order to bypass or activate the internal oscillator. When the CLKIN pin frequency is higher than ~200kHz, the CLK_detect circuit turns off the internal oscillator and passes the external clock signal to the ADC. The CLK_detection block activates the internal oscillator when the CLKIN pin frequency falls below ~200kHz. When selecting the internal oscillator, make sure to connect the CLKIN pin to GND.

The allowable frequency range of the external clock signal fCLKIN is specified in the electrical characteristics table.

Frequency response

The ADS1231 uses a sinc4 digital filter, and the frequency response is shown in Figure 17, fCLKIN=4.9152MHz. The frequency response repeats at multiples of the 76.8kHz modulator sampling frequency. The overall response is a low pass filter with a -3dB cutoff frequency of 3.32Hz, speed pin bind low (10SPS data rate), 11.64Hz, speed pin bind high (80SPS data rate).

To help observe the response at low frequencies, Figure 17(a) illustrates the nominal response at 100 Hz when the data rate is 10 SPS. Note that the signal at the 10Hz magnification is rejected, so simultaneous rejection of 50Hz and 60Hz is achieved.

The benefit of using a sinc4 filter is that each frequency notch has four zeros in the same location, providing excellent normal mode rejection of line cycle disturbances.

Figure 17(b) Zoom in on the 50 Hz and 60 Hz notches with the speed pins bound low (10SPS data rate).

The data rate and frequency response scale of the ADS1231 are directly related to the clock frequency. For example, if fCLKIN increases from 4.9152MHz to 5.5296MHz with the speed pin high, the data rate increases from 80SPS to 90SPS and the notch also increases from 80Hz to 90Hz. Note that these changes are only possible when an external clock source is applied.

Settling time

Rapid changes in the input signal take time to resolve. For example, an external multiplexer in front of the ADS1231 can generate abrupt changes in the input voltage by simply switching the multiplexer input channel. These changes in the input require four data conversion cycles to resolve. When converting continuously, five readings may be required to determine the data. If the input change occurs in the middle of the first conversion, then four full conversions of the fully settled input are required to obtain fully settled data. The first four reads were discarded as they contained only partially fixed data. Figure 18 shows the settling time for the ADS1231.

data rate

The ADS1231 data rate is set by the speed pins, as shown in Table 2. At lower speeds, the data rate is nominally 10SPS. This data rate provides the lowest noise and excellent rejection of both 50 Hz and 60 Hz line cycle disturbances. For applications that require fast data rates, set High Speed to select a nominally 80SPS data rate.

Data Format

The ADS1231 outputs 24-bit data in binary two's complement format. The least significant bit (LSB) has a weight of (0.5VREF/128)(223–1). A positive full-scale input yields an output code of 7FFFFFh, a negative full-scale input yields an output code of 800000h, and the output is stuck at these codes for signals exceeding full scale. Table 3 summarizes the ideal output codes for different input signals.

Data Ready/Data Out (DRDY/DOUT)

This digital output pin serves two purposes. First, it indicates when new data is ready. Then on the first rising edge of SCLK, the DRDY/DOUT pin changes function and starts outputting conversion data, the most significant bit (MSB) first. Data is present on each subsequent SCLK rising edge. After all 24 bits have been retrieved, additional SCLK can be used. Then it stays high until new data is ready. This configuration polls the DRDY/DOUT state to determine when to start.

Serial Clock Input (SCLK)

This digital input shifts serial data out with each rising edge. This input has built-in hysteresis, but care should still be taken to ensure a clean signal. A faulty or slowly rising signal can cause unnecessary extra shifts. Therefore, it is best to ensure that both the rise and fall times of SCLK are less than 50ns.

data retrieval

The ADS1231 continuously converts analog input signals. To retrieve data, wait until DRDY/DOUT is low, as shown in Figure 19. After DR goes low, start shifting out data by applying SCLK. Data is shifted out MSB first. The 24-bit data does not need to be shifted out all, but the data must be retrieved (within tCONV) before updating the new data or the data will be overwritten. Avoid retrieval during data update (tUPDATE). If only 24 SCLKs have been applied, DRDY/DOUT is still shifted high with the state of the last bit (see tUPDATE), indicating that new data is being updated. To avoid DRDY/DOUT being left in the last bit state, a 25th SCLK can be applied to force DRDY/DOUT high, as shown in Figure 20. This technique is useful when the host controlling the device is polling DRDY/DOUT to determine when data is ready.

Standby mode

Standby mode significantly reduces power consumption by shutting down most of the circuitry. To enter standby mode, simply hold SCLK high after DRDY/DOUT goes low; see Figure 21. Standby mode can be initiated at any time during the backup process; all 24-bit data does not have to be retrieved beforehand.

Standby mode is active when tSTANDBY passes with SCLK held high. When standby mode begins, DRDY/DOUT is held high. SCLK must be held high to remain in standby mode. To exit standby mode (wake up), set SCLK low. The first data after exiting standby mode is valid.

Power down mode

Power-down mode shuts down the entire ADC circuit and reduces total power consumption to near zero. To enter power-down mode, simply hold the PDWN pin low. Power-down mode also resets the entire circuit. During readback, shutdown mode can be initiated at any time; it is not necessary to retrieve all 24-bit data beforehand. Figure 22. Power-Up Timing Sequence Figure 23 shows the wake-up timing in power-down mode.

Applications

weighing system

Figure 24 shows a typical ADS1231 application as part of a weighing system.

Tape and Reel Information