1. Features

Input voltage range: 2.7 V to 10 V

output voltage range: 1.25 V to 9 v

2.5%adjustment pin voltage accuracy ( 25 ° C)

Low pressure difference: 1 A is 450 mv (typical value is 5 VVOUT)

Precision (fine-tuning) band gap benchmark

to ensure -40 ° C The specifications of+125 ° C

1-μA disconnected static current

Heat overload protection

can be foldable and restricted

Enable (EN) Spinning (LP38692-ADJ)

5-pin SOT-223 and 6-pin WSON packaging

2, Application

hard disk drive

Notebook computer

]

Battery power supply equipment

Portable instrument

3. Explanation

LP38690-ADJ and LP38692-ADJ low pressure difference CMOS linear voltage voltage voltage voltage regulator provides 2.5%accuracy reference reference Voltage, extremely low voltage drop (450 MV under 1-A load current, VOUT u003d 5 V), and excellent AC performance series connected resistor (ESR) ceramic output capacitors using ultra-low equivalent. The low thermal resistance of WSON and SOT-allows 223 complete packages to use the environment even at high environmental temperatures. The use of PMOS power transistors means that the DC base drive current needs to keep its offset ground pins currents below 100 μA regardless of the load current, input voltage, or operating temperature.

Falling voltage: 450 MV (typical value) is 1 A (typical value output 5 volts)

Ground pins current: 55 μA (typical value)

adjustment Pinper voltage: 2.5%(25 ° C) accuracy

Electric characteristics

Unless otherwise stipulated: typical limit is tj u003d 25 ° C, minimum and maximum limit is suitable for the entire operation Temperature range; vin u003d Vout+1 V, CIN u003d COUT u003d 10 μF, ILOAD u003d 10 mAh. The minimum and maximum values u200bu200bare tested, statistical correlation or design.

(1) Typical numbers represent the most likely parameter specifications for operation of 25 ° C.

(2) The output voltage line adjustment refers to changes in the output voltage and nominal value caused by changes in the input voltage.

(3) The output voltage load adjustment refers to the increase in load current from 1MA to full load.

(4) pressure dropThe minimum input output gauge required to keep the output in the range of the nominal value of 100 MV.

Typical features

Unless there are other regulations: TJ u003d 25 ° C, CIN u003d COUT u003d 10 μF, EN pins are connected to VIN (only LP38692-ADJ), vout u003d 1.25 V, Vin u003d 2.7 Five, ILOAD u003d 10 MA.

Detailed description Overview

lp3869x adjustment The design of the device meets the requirements of portable and battery power systems to provide accurate output voltage and rapid startup. By enabling the low-logical signal of the pin (EN), the power consumption is almost reduced to zero (only LP38692-Adj). LP3869X has a good performance with a 1 μF input capacitor and a 1 μF ceramic output capacitor.

Function description

Folding restrictions

Folding current is limited in LP3869X ADJ, which can reduce the output current of the component Output when the output voltage is reduced. The size of the load current depends on the pressure difference between VIN and VOUT. Generally, when the voltage difference exceeds 5V, the load current will be limited to 450 mAh. When the VIN -VOUT difference drops below 4 V, the load current is limited to about 1500 mA.

Equipment function mode

Enable pin (only LP38692-ADJ)

LP38692-ADJ has a enable pin (EN), allowing external control signals to open the regulator Output and then leave. The opening/turn -off threshold is not lagging. The voltage signal must be clearly risen and decreased, and the voltage threshold is quickly through the switching voltage. The EN pin does not have an internal pull -down or drop -down to establish the default conditions, so it is necessary to actively or passively terminate this pin. If the EN pin is driven from a high -voltage and low -voltage power supply, the driving voltage cannot be lower than the ground potential or VIN. If the application does not need to be enabled, the pipe foot must be connected directly to the IN pin.

Application information

Reverse voltage

When the voltage on the OUT pin is higher than the voltage on the IN pin, there is a reverse voltage. Under normal circumstances, when IN is suddenly lowered and cannot continue to keep enough charge, the voltage input into the output of the output will occur. One of the uncommon cases is to connect the backup voltage source to the output end. During the reverse voltage, the current has two possible path conditions from the output pins.

1. When the vehicle recognition number (VIN) is high,It is enough to keep the control circuit working, and the EN pin (only LP38692-ADJ) is higher than that of the (open) threshold. The control circuit will try to adjust the output voltage. If the input voltage is low, the grille of the output voltage of the programming is completely connected to the output voltage drive channel component. In this case, the reverse current flows from the OUT pin to the IN pin, and the only RDS (on) restrictions are limited to the voltage difference between the components and output to the input. The output capacitor discharge up to 1000 μF When the current is rapidly attenuated, this method will not damage the device. However, continuous reversal must avoid current. When EN pins are low, this can prevent this.

2. The internal PFET channel element has a inherent parasitic diode. During the normal operation, the input voltage is higher than the output voltage and the parasitic diode reverse bias. However, when the vehicle identification number (VIN) is lower than the control circuit band or EN pin (only LP38692-ADJ) and the output voltage is higher than the input voltage 500 millivolttrasion (typical value), the parasite diode will produce a positive bias The pressure and current pass through the diode from the OUT pin to the IN pin. The current in the parasitic diode must be limited to less than 1-a consecutive and 5-a peak. If it is used for the dual power system, the regulator output load returns the negative power supply, the output pin must be tied to the ground to limit the negative voltage conversion. It is recommended to use the protective clip of the Schottky diode.

Detailed design program

Set output voltage

Use the external resistor R1 and R2 settings The output voltage (see Figure 29 and Figure 30). The output voltage is given by 1: VOUT u003d VADJ × (1+ (1+ (R1/R2))) (1) Because the minimum load current requirements of the parts are 100 μA, TI recommends that R2 is always 12 kΩ or less to provide enough loads to provide enough loads Essence Even if the minimum load is always provided in other ways, it is not recommended to use very high resistance values u200bu200bfor R1 and R2, because it can make ADJ nodes easily affected by noise. The maximum value of R2 is recommended to prevent this to prevent this.

External capacitors

Like any low -voltage difference, external capacitors need to ensure stability. These capacitors must be correctly selected to obtain appropriate performance.

Input a capacitor

requires at least 1 μF to input capacitors (it is recommended to use ceramics). The position of the capacitor shall not exceed 1 cm from the IN pin, and return to the clean simulation ground.

Output capacitor

requires an output capacitor to ensure the stability of the circuit. It must be located where the distance is less than 1 cm, and is directly connected to the OUT and GND pins to use traces without other current flowing. The minimum output that can be used for stable operationThe capacity is 1 μF. Ceramic capacitors are recommended (LP3869X ADJ design for ultra -low ESR capacitors). The LP3869X regulator is stable between 0Ω and 100Ω output capacitance ESR.

Select a capacitor

It must be noted that the capacitor tolerance and temperature change must be considered. When the capacitor is selected, the minimum power capacity is greater than the working temperature range.

Ceramics

For capacitor values u200bu200bin the range of 10-100 μF, ceramics usually have high noise than the capacitor, so there is a high noise ESR (usually less than 10 m u0026# 8486;). However, some media types do not have good capacitance characteristics as functions of voltage and temperature. The capacitance of Z5U and Y5V dielectric ceramics decreased sharply with the increase of voltage. Typical Z5U or Y5V capacitors will lose 60%of the rated capacitors when applying half of the rated voltage. Z5U and Y5V also show serious temperature effects, in the temperature range. If you use ceramics, it is strongly recommended to use X7R and X5R medium ceramic capacitors, because they are usually kept the capacitor range within the range of ± 20%of the full -working rated value of temperature and voltage. For the given voltage and capacitors, they are usually larger and higher than the Z5U/Y5U model.

12

Solid 钽 capacitors have good temperature stability: high-quality 钽 usually manifested as the entire temperature range of capacitors from -40 ° C to+125 ° C by less than 10- 15%value. ESR only changes about 2 × from high temperature to low temperature limit. When using marginal mass capacitors, an increase in ESR at lower temperatures will cause oscillation (if the ESR of the capacitor is close to the upper limit of a stable range at room temperature).

RF interference/electromagnetic interference sensitivity

RF interference (RFI) and electromagnetic interference (EMI) will reduce the performance of any integrated circuit due to the small geometric size inside the device, so the performance is good. In the circuit application, there is a signal source of a large amount of high -frequency energy content (u0026 gt; 1MHz) that generates a large amount of high -frequency energy content (u0026 gt; 1MHz). You must carefully ensure that this will not affect the device regulator. If the input side of the regulator has RFI/EMI noise (for example, the application of an input source appears from the output of the switching regulator), it must be in the device. If the load is connected to the device output (such as clock) to the high -speed switch, the current pulse required by the high -frequency load must be provided by the capacitor output on the device. Because if the bandwidth is less than 100 kHz, the control circuit cannot respond frequency to load changes above the value. This means that the effective output impedance of the device is determined at the frequency of 100 kHz or above only the output capacitor. In the application of high -speed switching, the output of the device may require radio frequency isolation load. It is recommended to place some inductors between the output capacitor and the load, and the good RF crossing electric container directly placed directly inOn the load. PCB layout is also important in a high noise environment, because RFI/EMI can easily radiate directly into the PC trajectory. The noise circuit should be isolated from the clean circuit as much as possible and grounded through a separate path. At the frequency of MHz, the ground plane begins to look induced, and RFI/EMI may cause the ground to rebound the ground surface. In the application of multi -layer printing circuit boards, the layout should be paid attention to, so that the noise power and grounding aircraft should not be directly radiated to the adjacent layer of the portal of simulation power and the ground.

Output noise

There are two provisions of noise: spots noise or output noise density is the average root root of all noise sources. Hz bandwidth measurement). This is that this noise is usually drawn on the curve as a function of the frequency. Total output noise or broadband noise is equal to square roots and on specific bandwidth, usually spots noise in the frequency range of decades. Pay attention to the measurement unit. The measurement unit of the point noise is μV/√Hz or NV/√Hz, and the main noise source of the low voltage difference stabilizer in the measuring low voltage stabilizer is internal benchmark. Noise can be divided into two methods: by increasing the area of u200bu200bthe transistor or increasing internal benchmark current. Increasing this area reduces the possibility of assembling molds to smaller packaging. Internal reference to increase the total power current (GND pins current).

Power consumption

The correct size of the power consumption of the device and the thermal flat plane connected to the convex ears or pads is essential for ensuring reliability. The power consumption depends on the input voltage, output voltage and load conditions and available formulas 2 calculations. Vehicle recognition number (VIN) u003d Maximum value 2 By using the minimum power consumption available, the power consumption can be minimized, and the higher efficiency voltage reduction option will still be greater than the voltage voltage (VDO). However, please remember that the voltage drop will produce better dynamic performance (ie, PSRR and transients). In WSON (NGD) packaging, the main conductive path of the heat is to the printing circuit board through the exposed power. To ensure that the device is not overheated, the exposed pads are connected to the internal floor through the heat -pass hole to have an appropriate amount of copper PCB area. On SOT-223 (NDC) packaging, the main conductive path of the calorie is to PCB through pins. Power consumption and knot temperature are usually related to environmental thermal resistance. /Rθja

Unfortunately, this RθJA is highly dependent on the thermal diffusion capacity of specific PCB design, and therefore vary depending on the area and total area of u200bu200bcopper. RθJA records the heat information is determined by the specific EIA/JEDEC JESD51-7 PCB and copper spreading area standards, and only as a relative measurement of packaging thermal performance. For the well -designed heat layout, RθJA is actually the sum of packaging knot and shell (bottom) thermal resistance (RθJCBOT) plus thermal contribution as a hot PCB copper area.

Estimated knot temperature

EIA/JEDEC standards are recommended to use PSI (ψ) thermal characteristics to estimate the temperature of typical PCB board application surface installation equipment. These characteristics are not real thermal resistance values, but to pack specific thermal characteristics, providing practical and relatively estimated temperature -knot temperature. These PSI indicators are determined to be significantly independent of the copper diffusion area. The key thermal characteristics (和jt and ψJB) are given in the heat information and used according to the type 5 or type 6. TJ (maximum) u003d ttop+(ψjt × PD (MAX))

PD (MAX) explained u0026#8226 in Formula 4; TTOP is the temperature measured at the top of the center of the device. TJ (MAX) u003d T -board+(ψjb × PD (MAX))

PD (MAX) is explained in Formula 4. TBOARD is a PCB surface temperature measured from the device packaging 1 mm, and the edge of the packaging is packed.

Power suggestion

LP3869X ADJ device design is designed for working in the range of input power supply voltage between 2.7 V and 10 V, and the input power supply must be well adjusted and no murmur. To ensure that the output voltage of the LP3869X regulator is well adjusted, the input power supply must be at least VOUT+0.5V or 2.7V. The minimum capacitor value 1-μF requires that within the range of IN pin 1cm.

Layout

Layout Guide

It is necessary to use a good PC layout practice, otherwise it will be unstable due to the decline of ground circuit and voltage. The input and output capacitors must use the records that are directly connected to the input, output and ground pins of the regulator (Kelvin connection) without other current flow. The best way is to arrange CIN and COUT near the device, and track the input, output and GND short -distance tracking. The regulator ground needle must be connected to the external circuit ground so that the regulator and its capacitors have single -point grounding. The problem of stability has appeared in the grounding of the device and input and output capacitors in applications using internal ground flooring. This is caused by these nodes that are caused by current flowing across the ground plane. Using single -point grounding technology regulator and regulator capacitor to solve this problem. Because the high current flows through the input and output, Kelvin connects the capacitor lead to these pins, so that there will be no voltage reduction input and output capacitors.

WSON installation

NGG0006A (no back) 6-lead WSON packaging requires specific installation technology. These technologies are detailed in AN-1187 in detail. Lead -free lead frame encapsulation (LLP), SNOA401. The PAD style used with the WSON package is NSMD (non -welding -cover definition) type.In addition, the TI recommends that the PCB terminal pad is 0.2 mm than the packaging pad to form welding angles to improve reliability and testability.The input current is diverted between the two IN pin 1 and 6.Two IN sales must be connected together to ensure that the device can meet all specifications under the rated current.The cooling performance of WSON packaging is directly related to the additional copper area of the structure and structure of the printing circuit board to DAP.The DAP (exposed pad) at the bottom of the WSON packaging is adhesive to the mold substrate through the conductive material.DAP has no direct electrical (wire) connection with any pin.There is a connection between parasitic PN chip substrate and equipment ground.Therefore, it is strongly recommended that DAP directly ground at the device wire 2 (ie GND).Or, but it is not recommended, DAP can maintain a floating state (that is, there is no electrical connection).DAP must not be connected to the elimination ground.