feature

1.8V analog supply operation; 1.8 V to 3.3 V output supply; SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input; SFDR = 85 dBc to 70 MHz input; low power: 395 mW @ 125 ms/sec; 650mhz bandwidth differential input; on-chip voltage reference and sample-and-hold amplifier; DNL=±0.15 least significant bit; flexible analog input: 1 V pp to 2 V pp range; offset binary, gray code, or twos complement data format; Duty cycle stabilizer; data output clock; serial port control; built-in selectable digital test mode generates programmable clock and data alignment.

application

Ultrasonic equipment; CDMA One, IMT-2000 if the sampling in the communication receiver is -95; battery powered instruments; handheld oscilloscopes; low cost digital oscilloscopes.

General Instructions

The AD9233 is a monolithic, single 1.8V supply, 12-bit, 80MSPS/105MSPS/125MSPS analog-to-digital converter (ADC) with a high performance sample and hold amplifier (SHA) and an onboard voltage reference. The product uses a multi-stage differential pipeline structure with output error correction logic, provides 12-bit accuracy at a data rate of 125 MSPS, and guarantees no code loss over the entire operating temperature range.

The wide bandwidth, true differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in continuous channels, as well as sampling single-channel inputs at frequencies well beyond the Nyquist rate. Compared to previously available ADCs, the AD9233 not only saves power and cost, but is also suitable for communications, imaging, and medical ultrasound.

The differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) can compensate for large variations in the clock duty cycle while maintaining good overall ADC performance.

Digital output data is represented in offset binary, gray code, or two's complement format. A data output clock (DCO) is provided to ensure proper latch timing of the receive logic.

The AD9233 is available in a 48-lead LFCSP and is specified over the industrial temperature range (-40°C to +85°C).

Product Highlights

1. The AD9233 is powered by a 1.8V power supply and is equipped with a separate digital output driver power supply to accommodate 1.8V to 3.3V logic families.

2. The patented SHA input maintains excellent performance for input frequencies up to 225MHz.

3. The clock DCS maintains the overall performance of the ADC over a wide range of clock pulse widths.

4. The standard serial port interface supports various product features and functions, such as data formatting (offset binary, two's complement or gray coding), enabling clock DCS, power down and voltage reference modes.

5. The AD9233 is pin-compatible with the AD9246, allowing easy migration from 12-bit to 14-bit.

Pin Configuration and Function Description

Equivalent Circuit

Typical performance characteristics

AVDD=1.8 V; DRVDD=2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V pp differential input; AIN=-1.0 dBFS; 64k samples; T=25°C unless otherwise noted. All figures show typical performance for all speed grades.

theory of operation

The AD9233 architecture consists of a front-end SHA and a pipelined switched capacitor ADC. In the digital correction logic, the quantized outputs from each stage are combined into a final 12-bit result. The pipelined architecture allows the first stage to operate on new input samples, while the remaining stages operate on previous samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last stage, consists of a low-resolution flash ADC connected to a switched capacitor DAC and an interstage residual amplifier (MDAC). The residual amplifier amplifies the difference between the reconstructed DAC output and the flash input in the next stage of the pipeline. One bit redundancy is used per stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage contains a differential SHA, which can couple AC or DC in differential or single-ended mode. The outputtaging block aligns the data, performs error correction, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted. During power down, the output buffers go into a high impedance state.

Analog Input Considerations

The analog input to the AD9233 is a differential switched capacitor SHA, which is designed for optimum performance when dealing with differential input signals.

The clock signal alternates the SHA between sample mode and hold mode (see Figure 36). When the SHA switches to sampling mode, the signal source must be able to charge and stabilize the sampling capacitor within half a clock cycle. Small resistors in series with each input help reduce the peak transient current required to drive the source output stage.

A parallel capacitor can be placed at the input to provide dynamic charging current. This passive network creates a low-pass filter at the ADC input; therefore, the exact value depends on the application.

In undersampling applications, any parallel capacitors should be reduced. Combined with the drive source impedance, these capacitors limit the input bandwidth. See application notes AN-742, Frequency Domain Response of Switches - Capacitor ADCs, and AN-827, A Resonant Approach to Interfacing Switched Capacitor ADCs to Amplifiers, and the Analog Dialogue article "Transformer-Coupled Front Ends for Wideband A/D Converters" ” for more information.

For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched so that the common-mode regulation errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

An internal differential reference buffer generates two reference voltages that define the input range of the ADC core. The span of the ADC core is set by the buffer to be 2×VREF. The user cannot use the reference voltage. Two bypass points, REFT and REFB, are proposed for decoupling to reduce the noise of the internal reference buffer. A 0.1µF capacitor is recommended to separate REFT from REFB, as described in the Layout Considerations section.

Input common mode

The analog inputs of the AD9233 have no internal dc bias. In AC-coupled applications, the user must provide this bias externally. For best performance, it is recommended to set the device to V=0.55×AVDD; however, the device has a wider range of functions and reasonable performance (see Figure 32). An on-board common-mode voltage reference is included in the design, available from the CML pin. Best performance is obtained when the common-mode voltage of the analog inputs is set by the CML pin voltage (typically 0.55 × AVDD). The CML pin must be separated from ground by a 0.1µF capacitor, as described in the Layout Considerations section. centimeter

Differential Input Configuration

The best performance is obtained by driving the AD9233 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and flexible interface to ADCs. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9233 (see Figure 37), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

For baseband applications where signal-to-noise ratio is a critical parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 38. The CML voltage can be connected to the center tap of the transformer secondary winding to bias the analog input.

Signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz, and excessive signal power can cause the core to saturate, resulting in distortion.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is insufficient to achieve the true SNR performance of the AD9233. For applications where signal-to-noise ratio is a critical parameter, input transformer coupling is recommended. For applications where SFDR is a critical parameter, a differential dual balun coupled input configuration is recommended. An example is shown in Figure 39.

As an alternative to using a transformer-coupled input at the second Nyquist zone frequency, the AD8352 differential driver can be used. An example is shown in Figure 40.

In any configuration, the value of the shunt capacitor C depends on the input frequency and source impedance and may need to be reduced or removed. Table 8 shows suggested values for setting up the RC network. However, these values depend on the input signal and should only be used as a starting guide.

Single-ended input configuration

Although not recommended, the AD9233 can be operated in a single-ended input configuration as long as the input voltage swings within the AVDD supply. Single-ended operation can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to excessive input common-mode oscillation. If the source impedances at each input are matched, there should be little impact on the SNR performance. Figure 41 details a typical single-ended input configuration.

voltage reference

A stable and accurate voltage reference is built into the AD9233. The input range can be adjusted by changing the reference voltage applied to the AD9233 (either using the internal reference voltage or an externally applied reference voltage). The input range of the ADC tracks linear changes in the reference voltage. The following sections summarize the various reference modes. The Reference Decoupling section describes the referenced PCB layout best practices and requirements.

Internal reference connection

The comparator in the AD9233 senses the potential at the sense pin and configures the reference into four possible states, as shown in Table 9. If the sensor is grounded, the reference amplifier switch is connected to an internal resistor divider (see Figure 42), setting VREF to 1V.

Connecting the sense pin to VREF switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 V reference output. As shown in Figure 43, if the resistor divider is connected outside the chip, the switch is again set to the sense pin.

This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

If the sense pin is connected to the AVDD pin, the reference amplifier is disabled and an external reference voltage can be applied to the VREF pin (see the External Reference Operation section).

The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

If the AD9233's internal reference is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 44 depicts the effect of the load on the internal reference voltage.

Xref Operations

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 45 shows the typical drift characteristics of the internal reference in 1V and 0.5V modes.

When the sense pin is tied to the AVDD pin, the internal reference is disabled, allowing the use of an external reference. The internal resistor divider loads the external reference with an equivalent 6 kΩ load (see Figure 11). In addition, internal buffers generate positive and negative full-scale references to the ADC core. Therefore, the external reference voltage must be limited to a maximum of 1V.

Clock Input Considerations

For best performance, the AD9233 sample clock inputs (CLK+ and CLK-) should be clocked with differential signals. Signals are typically AC coupled to the CLK+ and CLK- pins through transformers or capacitors. These pins are internally biased (see Figure 5) and do not require external biasing.

Clock input options

The AD9233 has a very flexible clock input structure. The clock input can be CMOS, LVDS, LVPECL, or a sine wave signal. Regardless of the type of signal used, the jitter of the clock source is of greatest concern, as described in the Jitter Considerations section.

Figure 46 shows a preferred method of timing the AD9233. The low-jitter clock source is converted from a single-ended to a differential signal by an RF transformer. Back-to-back Schottky diodes on the secondary side of the transformer limit the clock skew of the AD9233 to approximately 0.8V pp differential. This helps prevent large voltage fluctuations of the clock from being fed through the rest of the AD9233, while maintaining the fast rise and fall times of the signal, which are critical for low jitter performance.

If a low-jitter clock source is not available, another option is to AC-couple the differential PECL signal to the sampling clock input pins, as shown in Figure 47. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers have excellent jitter performance.

A third option is to AC couple the differential LVDS signal to the sample clock input pins, as shown in Figure 48. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers have excellent jitter performance.

In some applications, a single-ended CMOS signal can be used to drive the sample clock input. In this application, drive CLK+ directly from the CMOS gate while bypassing the CLK- pin to ground with a 0.1µF capacitor. Although the CLK+ input circuit power supply is AVDD (1.8v), this input is designed to tolerate input voltages up to 3.6v, making the choice of drive logic voltage very flexible. When driving CLK+ with a 1.8V CMOS signal, the CLK pin needs to be biased in parallel with a 0.1µF capacitor and a 39 kΩ resistor (see Figure 49). When driving CLK+ with a 3.3V CMOS signal, a 39 kΩ resistor is not required (see Figure 50).

clock duty cycle

A typical high-speed ADC uses two clock edges to generate various internal timing signals. Therefore, these ADCs may be sensitive to the clock duty cycle. Typically, a ±5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics.

The AD9233 includes a DCS that retimes non-sampling or falling edges, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9233. As shown in Figure 31, when the DCS is on, the noise and distortion performance is nearly flat over a wide range of duty cycles.

Jitter on the rising edge of the input is still the most important issue and is not reduced by the internal stabilization circuit. The duty cycle control loop is generally not suitable for clock frequencies less than 20 MHz. In applications where the clock rate can vary dynamically, the time constant associated with the loop needs to be considered, which requires a latency of 1.5µs to 5µs after the dynamic clock frequency is increased (or decreased) before the DCS loop relocks to the input signal . During the time the loop is unlocked, the DCS loop is bypassed and the internal device timing depends on the duty cycle of the input clock signal. In this application, the duty cycle stabilizer can be appropriately disabled. In all other applications, it is recommended to enable the DCS circuit to maximize AC performance.

When operating in external pin mode (see Table 10), DCS can be enabled or disabled by setting the SDIO/DCS pin or through the SPI (as described in Table 15).

Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given input frequency (F), the SNR drop due to jitter (t) is calculated as:

In the equation, the rms aperture jitter (t) represents the root mean square of all jitter sources, including clock input, analog input signal, and ADC aperture jitter specifications. If the undersampling application is particularly sensitive to jitter, as shown in Figure 51.

Treat the clock input as an analog signal if aperture jitter may affect the dynamic range of the AD9233. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. The power supply should also not be shared with analog input circuits such as buffers to avoid clock modulation onto the input signal and vice versa. Low jitter, crystal controlled oscillators are the best clock sources. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

See application notes AN-501, Aperture Uncertainty and ADC System Performance, and AN-756, Sampling System and Effects of Clock Phase Noise and Jitter for more in-depth information on ADC jitter performance.

Power Consumption and Standby Modes

As shown in Figures 52 and 53, the power consumed by the AD9233 is proportional to its sampling rate. Digital power consumption depends primarily on the strength of the digital driver and the load on each output bit. The maximum DRVDD current (I) can be calculated as:

where N is the number of output bits (12 in the case of the AD9233).

This maximum current occurs when each output bit switches on every clock cycle, i.e. a full-scale square wave at the Nyquist frequency f/2. In practical applications, the DRVDD current is determined by the switching quantity of the average output bits, which is determined by the sampling rate and the characteristics of the analog input signal. Reducing the capacitive loading of the output driver can minimize digital power consumption.

The data used in Figure 52 and Figure 53 is based on the same operating conditions used in the graphs in the Typical Performance Characteristics section, with a 5 pF load on each output driver.

Power down mode

By asserting the PDWN pin high, the AD9233 is placed in power down mode. In this state, the ADC typically dissipates 1.8mW. When powered down, the output drivers are in a high impedance state. Reasserting the PDWN pin low will return the AD9233 to its normal operating mode. The voltage tolerance of this pin is 1.8V and 3.3V.

Low power consumption in shutdown mode is achieved by turning off the reference, reference buffer, bias network and clock. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must then be recharged when normal operation resumes. Therefore, the wake-up time is related to the time spent in power-down mode; the shorter the power-down period, the shorter the wake-up time. With the recommended 0.1µF decoupling capacitors on REFT and REFB, it takes approximately 0.25 ms to fully discharge the reference buffer decoupling capacitor and 0.35 ms to resume full operation.

Standby mode

When using the SPI port interface, the user can place the ADC in power-down or standby mode. Standby mode allows the user to keep the internal reference circuit powered up when a faster wake-up time is required. See the memory mapping section for more details.

digital output

The AD9233 output driver can be configured to interface with a 1.8 V to 3.3 V logic family by matching DRVDD to the digital supply of the interface logic. The output drivers are sized to provide enough output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the power supply, affecting converter performance. Applications that require the ADC to drive large capacitive loads or large sectorized outputs may require external buffers or latches.

When operating in external pin mode, the output data format can be selected for offset binary or two's complement by setting the SCLK/DFS pin (see Table 10). When using SPI control, the data format can be selected for offset binary, two's complement, or gray code, as described in Interfacing with High Speed ADCs through the SPI User Manual.

out of range (or) condition

An out-of-range condition exists when the analog input voltage exceeds the input range of the ADC. Or a digital output that is updated with the data output corresponding to a particular sampled input voltage. So, or have the same pipeline latency as digital data.

Or low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in Figure 55. Or stay high until the analog input returns to the input range and another conversion is complete. An upper or lower overrange condition can be detected by logical operation and adding the OR bit to the MSB and its complement. Table 11 is the truth table for the overrange/overrange circuit in Figure 56 using a NAND gate.

Digital output enable function (OEB)

The AD9233 is tri-state capable. If the OEB pin is low, the output data driver is enabled. If the OEB pin is high, the output data driver is in a high impedance state. This is not for fast access to the data bus. Note that OEB is the reference digital supply (DRVDD) and should not exceed the supply voltage.

opportunity

The minimum typical conversion rate of the AD9233 is 10 MSPS. Dynamic performance degrades when the clock rate is lower than 10ms/sec.

The AD9233 provides a latched data output with a pipeline delay of 12 clock cycles. The data output is available one propagation delay (t) after the rising edge of the clock signal.

The length and loading of the output data lines should be minimized to reduce transients within the AD9233. These transients degrade the dynamic performance of the converter.

Data Clock Out (DCO)

The AD9233 provides a data clock output (DCO) for capturing data in external registers. The data output is valid on the rising edge of the DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 for a graphical timing description.

Serial Port Interface (SPI)

The AD9233 SPI allows the user to configure the converter for a specific function or operation through the structured register space provided inside the ADC. This provides the user with increased flexibility and customization based on the application. The address is accessed through the serial port and can be written or read through the port. Memory is organized into bytes, which are further divided into fields, as described in the memory mapping section. Refer to the Interfacing to High Speed ADCs via SPI user manual for detailed operational information.

Configuration using SPI

As shown in Table 13, three pins define the SPI of this ADC. The SCLK/DFS pin synchronizes the read and write data presented to the ADC. The SDIO/DCS dual-purpose pins allow data to be sent and read from the internal ADC memory-mapped registers. The CSB pin is an active low control that enables or disables read and write cycles.

The falling edge of CSB and the rising edge of SCLK together determine the start of the frame. Figure 57 and Table 14 provide examples of serial timing and its definitions.

Other modes involving CSB are also available. CSB can stay low indefinitely, enabling the device permanently (this is called streaming). CSB can be suspended high between bytes to allow for additional external timing. When CSB is tied high during power-up, the SPI function is put into high-impedance mode. This mode enables any SPI pin auxiliary functions. If CSB is high at power up and then brought low to activate the SPI, the SPI pin assist function will no longer be available unless the device is power cycled.

In the command phase, a 16-bit command is sent. The data follows the instruction phase and the length is determined by the W0 and W1 bits. All data consists of 8-bit words. The first bit of each byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pins to change the input direction to the output direction.

In addition to word length, the instruction stage determines whether the serial frame is a read or write operation, allowing the serial port to be used to program the chip and read the contents of on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pins to change from input to output at the appropriate point in the serial frame.

Data can be sent in MSB first or LSB first mode. MSB first is the default value at power-on and can be changed through configuration registers. For more information, see the Interfacing to High Speed ADCs via SPI user manual.

hardware interface

The pins described in Table 13 comprise the physical interface between the user programming device and the AD9233 serial port. When using the SPI interface, the SCLK and CSB pins are used as inputs. The SDIO pins are bidirectional and act as inputs during the write phase and as outputs during readback.

The SPI interface is flexible enough to be controlled by a PROM or PIC microcontroller. This provides the user with the ability to program the ADC using alternative methods. One method is described in detail in Application Note AN-812.

Some pins have dual functions when the SPI interface is not used. During device power-up, when connected to AVDD or ground, pins are associated with specific functions.

Configuration without SPI

In applications that do not interface with the SPI control registers, the SDIO/DCS and SCLK/DFS pins are used as independent CMOScompatible control pins. When the device is powered up, the CSB chip select is connected to AVDD and the serial port interface is disabled. In this mode, it is assumed that the user intends to use the pins as static control lines for the output data format and duty cycle stabilizer (see Table 10). For more information, see the Interfacing to High Speed ADCs via SPI user manual.

memory map

read memory map

Each row in the memory map has eight address locations. The memory map is roughly divided into three parts: the chip configuration register map (address 0x00 to address 0x02), the device index and transfer register map (address 0xFF), and the ADC function map (address 0x08 to address 0x18).

The memory-mapped registers in Table 15 show the register address number in hexadecimal in the first column. The last column shows the default value for each hex address. Bit 7 (MSB) column is the beginning of the given default hex value. For example, hex address 0x14, the hex default value of the output phase is 0x00. This means that bit 3=0, bit 2=0, bit 1=1, bit 0=1 or 0011. This setting is the default output clock or DCO phase adjustment option. The default values adjust the DCO stage by 90° relative to the nominal DCO edge and 180° relative to the data edge. For more information on this feature, see Interfacing to High Speed ADCs via SPI User Manual.

open location

Locations marked as open are not currently supported on this device. These locations should be written with 0 when needed. These locations only need to be written if part of the address location is open (eg, address 0x14). If the entire address location is open (address 0x13), the address location does not need to be written.

Defaults

From reset, key registers are loaded with default values. The default values of the registers are shown in Table 15.

logic level

The interpretation of the two registers is as follows:

• Bit set is synonymous with bit set to logic 1 or bit written to logic 1.

• Clear a bit is equivalent to setting the bit to a logic 0 or writing a logic 0 to the bit.

SPI accessible functions

Below is a list of features accessible through the SPI and a brief description of what the user can do with these features. These features are described in detail in Interfacing to High Speed ADCs via the SPI User Manual.

• Mode: Set the shutdown or standby mode.

• Clock: DCS is accessed via SPI.

• Offset: Digitally adjust the converter offset.

• Test I/O: Set the test mode to have known data on the output bits.

• Output Mode: Set the output, change the intensity of the output driver.

• Output Phase: Set the output clock polarity.

• Reference Voltage: Set the reference voltage.

Layout Considerations

Power and Grounding Recommendations

When connecting power supplies to the AD9233, it is recommended to use two separate power supplies: one for analog (AVDD, 1.8 V nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal). If only one 1.8V supply is available, it should be connected to AVDD first, then tapped and isolated with a ferrite bead or filter choke with decoupling capacitors before connecting it to DRVDD. Users can use several different decoupling capacitors to cover high and low frequencies. They should be close to the entry point at the PC board level and close to the part with the smallest trace length.

When using the AD9233, a single PC board ground plane should be sufficient. Optimum performance is easily achieved with proper decoupling and intelligent partitioning of the analog, digital, and clock sections of the board.

Exposed Blade Hot Slug Recommendations

The exposed blade on the bottom of the ADC is required to be connected to analog ground (AGND) for optimum electrical and thermal performance of the AD9233. The exposed continuous copper plane on the PCB should mate with the AD9233 exposed paddle (pin 0). The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation through the bottom of the PCB. These vias should be filled or plugged with solder.

To maximize the coverage and adhesion between the ADC and the PCB, the continuous plane is divided into several uniform sections by overlaying a silk screen on the PCB. This provides two connection points during reflow. Using a continuous plane with no partitions only guarantees one connection point between the ADC and the PCB. See Figure 58 for an example of a PCB layout. For detailed information on packaging and PCB layout for chip scale packages, please refer to Application Note AN-772, Design and Manufacturing Guidelines for Lead Frame Chip Scale Packages (LFCSP).

CML

The CML pin should be separated from ground using a 0.1µF capacitor, as shown in Figure 38.

RBIAS

The AD9233 requires the user to place a 10 kΩ resistor from the RBIAS pin to ground. This resistor sets the primary current reference for the ADC core and should have at least a 1% tolerance.

Reference decoupling

The VREF pin should be connected in parallel with a low ESR 1.0µF capacitor and a 0.1µF ceramic low ESR capacitor, disconnected from ground externally. In all reference configurations, REFT and REFB are bypass points provided to reduce noise caused by the internal reference buffer. It is recommended to place an external 0.1µF ceramic capacitor on REFT/REFB. While there is no need to place such a 0.1µF capacitor, without it the SNR performance will degrade by about 0.1db. All reference decoupling capacitors should be placed as close as possible to the ADC with minimal trace length.

Evaluation Committee

The AD9233 evaluation board provides all the support circuitry required to operate the ADC in various modes and configurations. The converter can be driven differentially with a dual balun configuration (default) or with an AD8352 differential driver. ADCs can also be driven single-ended. A separate power supply pin is provided to isolate the DUT from the AD8352 driver circuitry. Each input configuration can be selected by the correct connection of various components. Figure 59 shows a typical bench characterization setup used to evaluate the ac performance of the AD9233.

Signal sources for analog inputs and clocks with very low phase noise (<1ps rms jitter) are key to achieving optimum converter performance. To achieve the specified noise performance, the analog input signal also needs to be properly filtered to remove harmonics and reduce integrated or broadband noise at the input.

See Figure 60 through Figure 70 for complete schematics and layouts demonstrating routing and grounding techniques that should be applied at the system level.

power supply

The evaluation board comes with a wall-mounted switching power supply that provides a maximum output of 6 volts, 2 amps. Simply connect the power source to a wall outlet rated for 100 VAC to 240 VAC at 47 Hz to 63 Hz. On the other end is a 2.1mm inner diameter jack that connects to the PCB on the P500. Once on the PC board, the 6 V power supply is fused and regulated before being connected to five low-dropout linear regulators that provide the proper bias for various parts of the board. The L501, L503, L504, L508, and L509 can be removed to disconnect the switching power supply when operating the evaluation board in a non-fault state. This enables the user to bias each section of the board independently. Use the P501 to connect a different power source for each section.

Although AVDD-DUT and DRVDD-DUT require at least a 1.8v power supply with a current capacity of 1A, separate power supplies are recommended for analog and digital power supplies.

To operate the evaluation board with the AD8352 option, a separate 5.0V analog supply is required. The 5.0 V supply or AMP_VDD should have 1 A current capability. To operate the evaluation board with the alternate SPI option, a separate 3.3V analog power supply is required in addition to the other power supplies. The 3.3V supply (AVDD_3.3V) should also have 1A current capability. Solder jumpers J501, J502 and J505 allow the user to combine these power supplies. See Figure 64 for more details.

input signal

When connecting clock and analog sources, use a clean signal generator with low phase noise, such as a Rohde & Schwarz SMHU or Agilent HP8644 signal generator or equivalent. Connect the evaluation board using a one-meter, shielded, RG-58, 50Ω coaxial cable. Enter the desired frequency and amplitude of the ADC. Typically, most ADI evaluation boards can accept ~2.8V pp or 13dBm sine wave input. When connecting an analog input source, a multipole narrowband bandpass filter with 50Ω termination is recommended. Emulate devices using TTE? , Allen Avionics and K&L? type bandpass filter. If possible, connect the filter directly to the evaluation board.

output signal

Parallel CMOS outputs interface directly with analog

The device's standard single-channel FIFO data acquisition board (HSC-ADC-EVALB-SC). For more information on the FIFO board and its optional settings, visit /FIFO.

Default Action and Jumper Selection Settings

Below is a list of default and optional settings or modes allowed by the AD9233 version. Evaluation Committee.

POWER

Connect the switching power supply provided in the evaluation kit between 47 Hz to 63 Hz and a rated 100 V ac to 240 V ac wall outlet at the P500.

vehicle identification number

The evaluation board is set up for a dual balun configuration analog input with an optimum impedance of 50Ω and a matching frequency of 70MHz. For more bandwidth response, the differential capacitors on the analog inputs can be changed or removed (see Table 8). The common mode of the analog input is developed from the center tap of the transformer through the CML pin of the ADC. See the Analog Input Considerations section for more information.

VREF

VREF by passing the sense pins through the JP507 (pin 1 and pin 2). This results in the ADC operating at 2.0 V pp full scale. The evaluation committee also includes a separate external reference option. Just connect JP507 between pin 2 and pin 3, connect JP501, and provide an external reference at E500. The Voltage Reference section details the proper use of the VREF option.

Indian Rupee

RBIA requires 10 kΩ (R503) to ground and is used to set the ADC core bias current.

clock

The default clock input circuit is derived from a simple transformer coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T503) which adds a very low amount of jitter to the clock path. The clock input is terminated in 50Ω and AC coupled to handle single-ended sine wave inputs. The transformer converts the single-ended input to a differential signal, which is truncated before entering the ADC clock input.

PDWN

To enable the power down function, connect JP506 and short the PDWN pin to AVDD.

CSB

The CSB pin is pulled up internally, setting the chip to external pin mode to ignore SDIO and SCLK information. To connect the CSB pin control to the SPI circuit on the evaluation board, connect JP1 pin 1 and pin 2. To set the chip to serial pin mode and enable SPI information on SDIO and SCLK pins, connect JP1 low (connect pins 2 and 3) to always-enabled mode.

SCLK/DFS system

If the SPI port is in external pin mode, the SCLK/DFS pin sets the output data format. If the pin is left floating, the pin is pulled down internally, setting the default condition to binary. Connect JP2 pin 2 and pin 3 to set the format to two's complement. If the SPI port is in serial pin mode, connect JP2 pin 1 and pin 2 to connect the SCLK pin to the on-board SPI circuit. See the Serial Port Interface (SPI) section for details.

SDIO/DCS system

If the SPI port is in external pin mode, the SDIO/DCS pin action sets the duty cycle stabilizer. If the pin is left floating, the pin is pulled up internally, setting the default condition to "enable DCS". To disable DCS, connect JP3 pin 2 and pin 3. If the SPI port is in serial pin mode, connecting JP3 pin 1 and pin 2 will connect the SDIO pin to the onboard SPI circuit. See the Serial Port Interface (SPI) section for details.

Alternate Clock Configuration

A differential LVPECL clock can also be used to clock the ADC inputs using the AD9515 (U500). The components listed in Table 16 need to be populated when using this drive option. See the AD9515 data sheet for more information.

To configure the analog input to drive the AD9515 instead of the default converter option, the following components need to be added, removed, and/or changed.

• Remove R507, R508, C532, and C533 in the default clock path.

• Fill R505 with a 0Ω resistor and C531 in the default clock path.

• Populate R511, R512, R513, R515 to R524, U500, R580, R582, R583, R584, C536, C537 and R586.

If an oscillator is used, two oscillator package options (OSC500) can also be used to check the performance of the ADC. The JP508 offers the user the flexibility to use the enable pin, which is common on most oscillators. Populate OSC500, R575, R587 and R588 to use this option.

Alternative analog input driver configuration

This section provides a brief description of an alternative analog input driver configuration using the AD8352. When using this particular drive option, some components need to be populated as listed in Table 16. For more details on the AD8352 differential driver, including its operation and optional pin settings, see the AD8352 data sheet.

To configure the analog input to drive the AD8352 instead of the default transformer option, the following components need to be added, removed, and/or changed:

• Removed C1 and C2 from the default analog input path.

• Fill R3 and R4 with 200Ω resistors in the analog input path.

• Populate the optional amplifier input path with all components except R594, R595 and C502. Note that to terminate the input path, only one of the components (R9, R592 or R590 and R591) should be populated.

• Fill C529 with a 5 pF capacitor in the analog input path.

Currently, R561 and R562 are fitted with 0Ω resistors to allow signal connections. This area allows the user to design filters if other requirements are required.

Evaluation Board Layout

Dimensions