feature

2-channel, 256 -bit OTP (One Time Programmable) setting and forget resistance setting, low cost alternative to EEMEM; infinite adjustment before starting OTP; OTP override allows user to adjust dynamically; defined presets; end-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ; compact MSOP-10 (3 mm x 4.9 mm) package; fast settling time: tS=5 microseconds at power-up; full read/write of wiper registers; open preset to midscale Power supply; additional packet address decode pins AD0 and AD1 ( AD5173 ); single supply 2.7 V to 5.5 V; low temperature coefficient: 35ppm/°C; low power consumption, IDD=6µA (max); wide operating temperature: –40 °C to +125°C; evaluation board and software available; software replaces µC in factory programmed applications.

application

System Calibration; Electronic Level Setup; Mechanical Trimmers® Replacement in New Designs; Permanent Factory PCB Setup; Sensor Trimming for Pressure, Temperature, Position, Chemical and Optical Sensors; RF Amplifier Biasing; Automotive Electronics Trimming; Gain Control and Offset Adjustment.

Overview

The AD5172/AD5173 are dual-channel, 256-bit, one-time programmable (OTP) digital potentiometers that use fuse linking technology to achieve memory retention of resistance settings. For users who do not need to program digital potentiometer settings, OTP is a cost-effective alternative to EEMEM memory more than once. This device performs the same electronic adjustment function as a mechanical potentiometer, or a variable resistor with high resolution, solid state reliability, and excellent low temperature coefficient performance.

The AD5172/AD5173 are programmed using a 2-wire I2C compatible digital interface. Allows infinite adjustment before permanently setting the resistance value. A permanent fuse command freezes wiper positioning (similar to putting epoxy on a mechanical trimmer) when activated during OTP.

Unlike traditional OTP digital potentiometers, the AD5172/AD5173 have a unique temporary OTP override feature that allows new adjustments to be made even after the fuse has blown. However, on subsequent power-up conditions, the OTP settings are restored. This feature allows the user to process these digital volatile potentiometers with programmable presets.

For in-plant simulation devices, device programming software is provided to run on Windows® NT® 2000 and XP® operating systems. This software effectively replaces any external I2C controller, improving time-to-market for the user's system.

Typical performance characteristics

test circuit

Figures 27 to 34 illustrate the test conditions used in defining the product specification sheet.

operate

The AD5172/AD5173 is a 256-bit digitally controlled variable resistor (VR) that uses fuse link technology to achieve memory retention of resistance settings.

The internal power on preset will set the wipers to mid-scale during power-up. If the OTP function is activated, the device will power up at a user-defined permanent setting.

One Time Programming (OTP)

Before OTP activation, the AD5172/AD5173 are preset to midscale during initial power-up. After setting the wipers in the desired position, the resistance can be permanently set by setting the T bit high and the appropriate coding (see Table 5 and Table 6). Note that the fuse connection technique requires 6 volts to blow the internal fuse for a given setting. The user can only try the fuse once. After programming, the supply voltage must drop to the normal operating range of 2.7 V to 5.5 V.

The device control circuit has two verify bits, E1 and E0, that can be read back to check the programming status (see Table 7). The user should always read the verification bit to ensure the fuse is blown properly. After a fuse blows, all fuse locks are enabled on subsequent power-up; therefore, the output corresponds to the stored setting. Figure 35 shows a detailed functional block diagram.

Variable Resistor and Voltage Programming

Rheostat operation

The nominal resistance of the RDAC between terminals A and B is 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance (R) of VR has 256 points of contact through the wiper terminal and the B terminal. The 8-bit data in the RDAC latch is decoded to select one of 256 possible settings.

Assuming a 10 kΩ part is used, the first connection to the wiper starts at the B terminal of data 0x00. Since there is a wiper contact resistance of 50Ω, such a connection creates a minimum resistance of 100Ω (2 x 50Ω) between terminals W and B. The second connection is the first tap, corresponding to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for 0x01. The third connection is the next tap point, representing 178Ω for data 0x02 (2×39Ω+2×50Ω), and so on. For each additional LSB data value, the wipers move up the resistor ladder until the last tap point reaches 10,100 Ω (RAB + 2 × RW).

The general equation for determining the digitally programmed output resistance between W and B is:

where D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register, R is the end-to-end resistance, and R is the wiper resistance resulting from the on-resistance of the internal switch.

In summary, if R = 10 kΩ and the A terminal is open, set the output resistance R for the RDAC latch code, as shown in Table 5.

Note that there is a finite wiper resistance of 100Ω at zero-scale conditions. In this state, care should be taken to limit the current between W and B to a maximum pulsed current of no more than 20 mA. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to the mechanical potentiometer, the RDAC resistor between wiper W and terminal A also produces a digitally controlled complementary resistor R. When using these terminals, the B terminal can be opened. The resistance value for setting R starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general equation for this operation is:

If R=10 kΩ and the B terminal is open, set the following output resistance R for the RDAC latch code, as shown in Table 6.

Typical equipment-to-equipment matching is process batch dependent and can vary by as much as ±30%. Since the resistive element is processed using thin film technology, R has a very low temperature coefficient of 35 ppm/°C as a function of temperature. AB Company

Program the Potentiometer Divider

Voltage output operation

A digital potentiometer easily generates a voltage divider proportional to the input voltage from a to B at the wiper-to-B and wiper-to-a positions. Unlike the polarity of V to GND, which must be positive, the voltage between aB, Wa, and WB can be of any polarity.

If you ignore the effect of the wiper resistance on the approximation, connecting the A terminal to 5 V and the B terminal to ground will produce an output voltage with the wiper connected to B, starting at 0 V and ending at 1 LSB less than 5 V. The voltage of each LSB is equal to the voltage applied on the AB terminal divided by the 256 positions of the potentiometer divider. The general equation that defines the V output voltage relative to ground for any effective input voltage applied across terminals A and B is:

For a more precise calculation, including the effect of wiper resistance, V can be found as:

Operation of the digital potentiometer in voltage divider mode results in more accurate overtemperature operation. Unlike the rheostat mode, the output voltage is mainly determined by the ratio of the internal resistances R and R, not the absolute value. Therefore, the temperature drift was reduced to 15ppm/°C.

ESD protection

All digital inputs SDA, SCL, AD0, and AD1- are protected with series input resistors and parallel Zener ESD structures, as shown in Figure 39 and Figure 40.

Terminal voltage operating range

The AD5172/AD5173 V to GND supply defines the boundary conditions for proper operation of the 3-terminal digital potentiometer. Supply signals that appear on terminals A, B, and W above V or GND are clamped by internal forward-biased diodes (see Figure 41).

power-on sequence

Since the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 41), it is important to power V/GND before applying any voltage to terminals A, B, and W. Otherwise, the diode will be forward biased, energizing V inadvertently and potentially affecting the rest of the user's circuit. The ideal power-up sequence is ground first, then digital input, then V/V/V. The relative order of V, V, and digital inputs doesn't matter as long as power is applied after V/GND.

Power Considerations

To reduce package pin count, both one-time programming and normal operating voltage supplies are applied to the same V terminal of the AD5172/AD5173. The AD5172/AD5173 use a fuse link technique that requires 6 volts to blow the internal fuse for a given setting. The user can only try the fuse once. After programming, the supply voltage must drop to the normal 2.7 V to 5.5 V operating range. This dual voltage requirement requires isolation between the power supplies. The fuse programming power supply (on-board voltage regulator or rack mount power supply) must be rated at 6 V and must be able to deliver a 100 mA transient for 400 ms for one-time programming to succeed. After programming, the 6 V supply must be removed for proper operation at normal operating current levels of 2.7 V to 5.5 V. Figure 42 shows the simplest implementation using jumpers. This method saves a voltage source, but requires additional current and manual configuration.

In a 3.5 V to 5.5 V system, an alternative is to add a signal diode for isolation between the system power supply and the OTP power supply, as shown in Figure 43.

For users operating at 2.7 V, it is recommended to use a bidirectional low-threshold P-Ch mosfet for power isolation, as shown in Figure 44, assuming that the 2.7 V system voltage is applied first, then the P1 and P2 gates are pulled to ground, thus Turn on P1 and therefore, the VDD of the AD5172/AD5173 is close to 2.7V. When the AD5172/AD5173 settings were found, the factory tester applied 6 volts to VDD; also applied 6 volts to close the gates of P1 and P2. The OTP command is executed at this time to program the AD5172/AD5173. The 2.7V supply is therefore protected. Once the OTP is complete, the tester deactivates 6 V and the AD5172/AD5173 settings are permanently fixed.

AD5172/AD5173 realize OTP function internal fuse by blowing air. The user should always use the 6V one-time program voltage requirement for the first program command. Failure to comply with this requirement may result in changes to the fuse structure, rendering programming inoperable.

Poor printed circuit board layout can introduce parasitics that can affect fuse programming. Therefore, it is recommended to add a 1µF tantalum capacitor in parallel with a 1nF ceramic capacitor as close to the VDD pin as possible. These capacitors help ensure that OTP programming is successful by providing the proper current density. The combination of capacitor values provides high frequency transient response and greater extended peak current. Generally, C1 minimizes any transient disturbances and low frequency fluctuations, while C2 reduces high frequency noise.

Layout Considerations

It is a good practice layout design to use a tight minimum lead length. The incoming wire should match the minimum conductor length. The ground path should have low resistance and low inductance.

Note that the digital ground should also be remotely connected to a point on the analog ground to minimize ground bounce.

Evaluation software/hardware

There are two ways to control the AD5172/AD5173. Users can program the device using computer software or an external IC controller.

software programming

Due to the advantages of the one-time programmable feature, users may consider programming the device at the factory before shipping the final product to the end user. ADI provides a device programming software that can be implemented on PCs running Windows 95 or later in the factory. Therefore, no external controller is required, which greatly reduces development time. A program is an executable file that does not require any programming language or user programming skills. It's easy to install and use. Figure 46 shows the software interface. The software can be downloaded from .

The AD5172/AD5173 start from midscale after power-up before OTP programming. To increase or decrease resistance, the user can simply move the scroll bar on the left. To write any specific value, the user should use the bit pattern in the upper screen and press the run button. The format of writing data to the device is shown in Table 7. Once the desired setting is found, the user can press the programmed permanent button to blow the internal fuse.

To read the verification bits and data from the device, the user simply presses the read button. The format of the read bits is shown in Table 8.

To apply device programming software in the factory, the user must modify the parallel port cable and configure pins 2, 3, 15, and 25 of SDA Write, SCL, SDA Read, and DGND for the control signals, respectively (Figure 47). The user should also place the AD5172/AD5173 printed circuit board with the SCL and SDA pads, as shown in Figure 48, so that the pogo pins can be inserted for factory programming.

I2C interface

S=Start condition P=Stop condition

A=Confirm

AD0, AD1 = Package pin programmable address bits

X = don't care

W=Write

R=read

A0=RDAC subaddress select bit

SD = Shutdown Connect the wiper to the B terminal and disconnect the A terminal. It does not change the contents of the wiper register.

T = OTP programming bit. Logic 1 permanently programs the wipers.

OW = Override fuse settings and program digital potentiometers to different settings. Note that upon power up, the digital potentiometer will be preset to the midscale or fuse setting, depending on whether the fuse is blown or not.

D7, D6, D5, D4, D3, D2, D1, D0 = data bits.

E1, E0=OTP verification bit.

0, 0 = ready to program.

1, 0 = fatal error. Some fuses did not blow. Do not try again. Abandon this unit.

1, 1 = programming is successful. No further adjustments are possible.

IC compatible with 2-wire serial bus 2

The 2-wire IC serial bus protocol operates as follows:

1. The host initiates a data transfer by establishing a start condition, a high-to-low transition on the SDA line when SCL is high (see Figure 50 and Figure 51). The following byte is the slave address byte, which consists of the slave address and the R/W bit (this bit determines whether data is read from or written to the slave device). The AD5172 has a fixed slave address byte, while the AD5173 has two configurable address bits, AD0 and AD1 (see Figure 50 and Figure 51).

The slave whose address corresponds to the transmit address responds by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial registers. If the R/W bit is high, the master device reads from the slave device. If the R/W bit is low, the master device writes to the slave device.

2. In write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is the RDAC subaddress select bit. A logic low selects channel 1; a logic high selects channel 2.

The second MSB, SD, is an off bit. When the wiper is shorted to terminal B, a logic high causes terminal A to open. This operation produces almost 0Ω in rheostat mode and 0 V in potentiometer mode. It should be noted that the shutdown operation does not interfere with the contents of the registers. When resuming from a shutdown state, the previous settings will be applied to the RDAC. Additionally, new settings can be programmed during shutdown. When the part returns from the closed state, the corresponding VR settings are applied to the RDAC.

The third MSB T is the OTP programming bit. A logic high will blow the multifunction fuse and permanently program the resistance setting.

The fourth MSB must always be at logic 0.

The fifth MSB, OW, is an overlay bit. When raised to logic high, OW allows the RDAC setting to be changed even if the internal fuse is blown. However, once OW returns to logic zero, the position of RDAC will return to overwriting the previous setting. Because OW is not static, if the device is powered off and on, the RDAC will preset to a midscale or blown fuse setting, depending on whether the fuse is permanently set. The remaining bits in the instruction byte are not significant (see Figure 50 and Figure 51). After acknowledging the command byte, the last byte in the write mode is the data byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (8 data bits followed by an acknowledge bit). Transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 49).

3. In read mode, the data byte follows the acknowledgment of the slave address byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (slightly different from write mode, which has 8 data bits followed by an acknowledge bit). Likewise, transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 52 and Figure 53).

Note that the channel of interest is the channel previously selected in write mode. If the user needs to read the RDAC value of both channels, the first channel must be programmed in write mode and then switched to read mode to read the first channel value. After that, the user must switch back to write mode with the second channel selected, and read the second channel value in read mode. The user does not need to issue frame 3 data bytes in write mode for subsequent readback operations. See Figure 52 and Figure 53 for the programming format.

After the data byte, the verify byte contains two verify bits E0 and E1. These bits indicate the status of one-time programming (see Figure 52 and Figure 53).

4. After reading or writing all data bits, the master will establish a stop condition. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during 10 clock pulses to establish a stop condition (see Figure 50 and Figure 51). In read mode, the master issues a No response to the ninth clock pulse (ie, the SDA line is held high). The master then drives the SDA line low before 10 clock pulses, which will go high to establish a stop condition (see Figure 52 and Figure 53).

The Repeat Write feature gives the user the flexibility to update the RDAC output multiple times after only addressing and indicating the part once. For example, after the RDAC acknowledges its slave address and instruction byte in write mode, the RDAC output will be updated on every consecutive byte. If a different instruction is required, the write/read mode must start over with a new slave address, instruction and data bytes. Likewise, the repeated read function of the RDAC is also allowed.

Multiple devices on one bus (AD5173 only)

Figure 54 shows four AD5173s on the same serial bus. Each has a different slave address because their AD0 and AD1 pins are different. This allows each device on the bus to be written or read independently. The master output bus driver is an open-drain pull-down in a fully I2C-compatible interface.

Pin Configuration and Function Description

Dimensions