The ISL65426 is a high-efficiency dual-output monolithic synchronous buck converter operating at the input from 2.375V to 5.5V. This microcontroller power supply solution offers two output voltages, selectable or externally adjustable, from 1V to 80% of the voltage at a total output current of up to 6A. The two PWMs are synchronized 180 ° out of phase to step down the rms input current and ripple voltage. The ISL65426 switches at a fixed frequency of 1MHz using current mode control with integrated compensation to minimize the size and number of external components and provide good transient response. Internal synchronous power switches are thermally optimized for high efficiency, eliminating the need for an external Schottky diode. A unique power block architecture allows 6 partitions to support 1A function block options in one of four configurations. A master power block is associated with each master power block to synchronize the converter channels. Four floating slave power blocks allow the user to assign them to either channel. Verify the correct external configuration of the power block Internal initialization before soft-start initialization. Independent enable inputs allow simultaneous or soft-start interval sequencing of both drives. A third enable input allows additional sequencing for multiple input bias supply designs. Individual power is good indicator (PG1, PG2) signal conditioning window when output voltage is within range. The ISL65426 integrates two synchronous buck regulator channels. Fault conditions include overcurrent, undervoltage, and IC thermal monitors. The high level of integration contained in a lead-free thin quad plane (QFN) software package makes the ISL65426 ideal for powering many of today's small form factor applications. A single-chip solution for a large-scale digital integrated circuit, a programmable gate array (FPGA), requires separate core and I/O voltages.

feature

Efficient: up to 95%

Fixed frequency: 1MHz

Operates ±1% reference from 2.375V to 5.5V supply

Flexible output voltage options - programmable 2-bit video input - adjustable output 0.6V to 4.0V

User Partition Power Block

Ultra-Compact DC/DC Converter Design

PWMs synchronized 180° out of phase

Independent enable input and system enable

Stable all-ceramic solution

Excellent dynamic response

Independent output digital soft start

Power Good Output Voltage Monitor

Short circuit and thermal overload protection

Overcurrent and Undervoltage Protection

Lead-free plus annealed (RoHS compliant) available

application

FPGA, CPLD, DSP, CPU Core and I/O Voltages - Cyclone Spartan IIITM, Virtex IITM, Virtex II ProTM, Virtex 4mm - Altera StratixTM, Stratix IITM, Cyclone, Cyclone IITM - Latisectum , Latti Sectam, Latti Sectam

Low-voltage, high-density distributed power system

load regulation point

Distributed Power System

set top box

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Absolute Maximum Ratings Thermal Information

VCC, PVINx, LXx. Ground -0.3V to +6V

FBx, ENx, VxSETx, ISETx, PGOODx. -0.3V to VCC+0.3V

Electrostatic discharge classification

mannequin. 2 kV

machine type. 200 volts

Recommended working input range

VCC, PVINx. 2.375V to +5.5V

Thermal resistance θJA (°C/W) θJC (°C/W)

QFN package (Note 1, 2). 23 2.5

Maximum Junction Temperature (Plastic Packaging). +150 degrees Celsius

Maximum storage temperature range. -65°C to +150°C

Maximum lead temperature (10s for soldering). +260 degrees Celsius

Ambient temperature range. -10°C to +100°C

Operating Junction Temperature Range. -10°C to +125°C

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

The maximum junction temperature of 150°C is used for short periods of time to prevent shortened life. Operation near the 150°C junction may trigger

The unit was even before 150°C because that number was specified as a typical value.

notes:

1. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct connect" characteristics.

2. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Operating conditions recommended by electrical codes unless otherwise stated. VCC=PVIN=5.0V, TA=-10°C to +100°C (Note 2)

Operating conditions recommended by electrical codes unless otherwise stated. VCC=PVIN=5.0V, TA=-10°C to +100°C (Note 2) (continued)

Note: 3. Not production tested.

Typical performance curve circuit of Figure 2. VIN = 5V, Input Voltage 1 = 4A, Input Voltage 2 = 2A, Temperature TA = -10°C to +100°C, unless otherwise noted. Typical value is TA=+25°C (continued)

Typical performance curve circuit of Figure 2. VIN = 5V, Input Voltage 1 = 4A, Input Voltage 2 = 2A, Temperature TA = -10°C to +100°C, unless otherwise noted. Typical value is TA=+25°C (continued)

Typical performance curve circuit of Figure 2. VIN = 5V, Input Voltage 1 = 4A, Input Voltage 2 = 2A, Temperature TA = -10°C to +100°C, unless otherwise noted. Typical value is TA=+25°C (continued)

Pin Description

Bias supply input for small signal circuits. Connect this pin to the highest supply voltage available if two or more options are available. Locally screen this pin using a quality 0.1µF ceramic capacitor and 5Ω resistor (optional). PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, PVIN6 these pins are the corresponding power supply pins PWM power block. The associated power blocks must all be connected to the same power source. The power supply must be in the range of 2.375V to 5.5V. Ground signal ground. All small signal components are connected to this ground, which in turn is connected to PGND at one point. Power ground for PWM power block and thermal release for wrapping. The exposed pad must be connected to PGND and soldered to the PCB. Connect these pins tightly to the negative terminal of the input and output capacitors. FB1, FB2 voltage feedback input. Depending on the voltage select pin setting, connect an optional resistor divider between VOUT and GND for selecting the variable output voltage. LX1, LX2, LX3, LX4, LX5, LX6 switch the node connection to the inductor. This pin is connected to the internal synchronous power MOSFET switch. The average voltage at this node is equal to the regulator output voltage.

Programmable voltage monitoring system enables hysteresis. The POR rise threshold for this pin is 0.6Venable for applications with two or more inputs where power and bias rise time is an issue. EN1, EN2 Standard These pins are threshold-sensitive individual PWM converters. The current on these pins is small (10µA) internally pulled up to VCC. This pin disables the respective converter until pulled above the 1V rising threshold. ISET1, ISET2 power block configuration input. Select the appropriate state for each pin according to Table 1. V1SET1, V1SET2, V2SET1, V2SET2 output voltage configuration input. Select the appropriate state for each pin in accordance with the Electrical Specifications table. Page 1, Page 2 Good power delivery. The open-drain logic output is grounded when the output voltage is out of regulation. Functional Description The ISL65426 is a monolithic constant frequency current mode dual output buck converter controller configurable power block. Designed to provide use in FPGAs, cpld, core processors and ASICS.

power block

A unique power block architecture allows 6 partitions to support one configuration option of four power blocks. The block diagram in Figure 3 provides a top-level view of the power block layout. A main power block is assigned to each converter output channel. Power block 2 is assigned to converter channel 1 and power block 5 to channel 2. The main power modules must not be bundled together or the controller will not be able to soft start. The remaining four floating power blocks can be partitioned into one of the four valid states listed in Table 1. The controller detects logic signals at programming configuration pins ISET1 and ISET2 based on the following states. The controller checks the power block configuration and programs the configuration before both converters can be soft-started. Each power block has separate power connection pins, PVINx and common channels that must be connected to an input power supply. The connection points of each channel of a normal synchronous power switch must be connected together as well as an external inductor. See Typical Application Pin Connection Guidelines Schematic

Each power block has a scaled pilot device feedback that provides current. The settings of the configuration pins determine how the controller handles the individual split and summed current feedback signals. The main control loop ISL65426 is a monolithic constant frequency current mode step-down DC/DC converter. During normal operation, the internal top power switch is on every clock cycle. The output inductor current rises until the current comparator trips and turns off the highest power MOSFET. The bottom power MOSFET turns on and the inductor current gradually decreases for the remainder of the cycle. The current comparator compares the ripple current peak to the current pilot. The error amplifier monitors VOUT and compares it to the internal voltage reference. The output voltage of the error amplifier drives a current proportional to the pilot. If you are low pilot current level increases, trip current level output increases. The increased current brings the output level in line with the reference voltage. The output voltage programming is applied to the reference voltages V1SET1, V1SET2, V2SET1 and V2SET2 inside the error amplifier with respect to 0.6V which is internally scaled based on the logic signal state of the pins. The output voltage configuration logic decodes the 2-bit voltage and converts the identification code into a discrete voltage as shown in Table 2. This default condition programs the output voltage to a minimum level when each pin is pulled down internally by 10µA. Pulling down prevents situations where a pin can float, for example (cold solder connections) to raise the output voltage to the programmed level and damage sensitive load devices.

For output voltage levels required as shown in Table 2, the ISL65426 allows the user to use an external resistor divider (see Figure 4). First, both channels must be connected to the select pin associated with that output channel to set the internal reference to 0.6V. Next, the output voltage is divided by an external resistor divider according to Equation 1. R2 is arbitrarily chosen, but 5kΩ or 10kΩ is usually a good starting point. The designer can configure the output voltage of the 5V supply from 1V to 4V. Reducing the input supply voltage reduces the maximum programmable voltage output voltage to 80% of the input voltage level.

On-off level

The controller features an internal oscillator at a fixed frequency of 1MHz. The oscillator tolerance is +10% input deviation and the load range is too large. Operation Initialization The ISL65426 is based on three enable state initialization inputs (EN, EN1, EN2) and a power-on reset (POR) monitor on the VCC and PVINx inputs. Successful initialization of the controller prompts a one-time power block configuration check. Verification of soft-start interval for correct phase connection. The controller starts slowly ramping the output voltage based on the state of the enable input. Once the commanded output voltage is running, the power good signal changes from low to high corresponding to the active channel state, indicating the initialization of normal operation. A power-on-reset POR circuit prevents the controller from attempting to soft-start the supplied input pins before the critical power is sufficiently skewed. These include the VCC and PVINx pins. The VCC pin has a pin configuration based on the output voltage configuration VOUT2. If the configuration pin is set to 2.5V, the VCC POR rising threshold is typically 2.9V. The 3.3V configuration increases the VCC-POR level to 4.3V. This variable rise threshold ensures that the controller can properly switch the internal power block at the specified output voltage level. The PVINx pins have a programmed POR rising threshold output voltage configuration. While these upper voltage pins are below this threshold, as in the electrical specification section, the controller disables the internal power mosfet. Built-in hysteresis between the rising and falling thresholds ensures that once enabled, the controller will not inadvertently turn off the switch unless the bias voltage drops substantially. When these pins are below the rising POR threshold, the LX pin of the synchronous power switch remains in a high impedance state. If additional POR control is required, the system enable input can be used to control initialization, as described in the following sections.

ENABLE AND DISABLE If the POR input requirements are met, the ISL65426 remains off until the voltage at the enable input is above its enable threshold. Independent enable inputs EN1 and EN2 allow initialization of any one of the buck's individual, sequential or simultaneous converter channels. Both pins have a 10µA pull-up, which will initialize both when the voltage on their respective pins exceeds the rise-enable threshold, as defined in the Electrical System Specifications section. Both converters are controlled and enabled by the presence of the system, EN (see Figure 5). When two independent input power supplies are used for each channel of the power block or an external signal is required to control the power-on sequence system is enabled to provide a start-up sequence mechanism. The system enable has an internal 10µA pull-down menu only when the voltage on the EN pin is below the enable threshold. The current sink pulls the EN pin low. When VCC2 rises, the enable level is not determined by the resistor divider for VCC2. The enable level is defined in Equation 2 when the current receiver is active. R1 is the resistor VCC2 and R2 is the resistor from EN to GND.

Once the voltage on the EN pin reaches the enable threshold, the 10µA current sink turns off. When the part is enabled and the current receiver is off, the disable level is set by the resistor divider. The disable level is defined in Equation 3.

The difference between enabled and disabled levels provides users with configurable lag to prevent annoying tripping. To enable the controller, system enable must be high and one or both channel enable must be high. This must meet the POR circuit requirements for VCC and PVINx inputs. Once these conditions are met, the controller immediately initiates a power block configuration check.