feature

Wideband upconverter/downconverter; power conversion gain 1.8db; wideband RF, LF, and IF ports; SSB noise figure (NF) of 9.75 dB; input IP3: 28.5 dBm; input P1dB: 13.3dbm; typical low drive: 0 dBm; Single Supply Operation: 5V at 130mA ; Adjustable Bias for Low Power Operation; Open Paddle, 4 mm x 4 mm, 24-lead LFCSP package.

application

Cellular base station receivers; wireless link downconverters; wideband block conversion; instrumentation.

General Instructions

The ADL5801 uses a highly linear, double-balanced, active mixer core and integrated LO buffer amplifier to provide high dynamic range frequency translation from 10mhz to 6ghz. The mixer benefits from a proprietary linearization architecture that provides enhanced input IP3 performance when subjected to high input levels. A bias adjustment feature allows the use of a single control pin to optimize input linearity, SSB noise figure, and DC current. An optional input power detector is provided for adaptive bias control. High input linearity allows the device to be used in demanding cellular applications where in-band blocking signals can cause degraded dynamic performance. The adaptive biasing feature allows the part to provide high input IP3 performance in the presence of large blocking signals. When the blocker is removed, the ADL5801 can be automatically down-biased to provide low noise figure and low power consumption.

The balanced active mixer configuration provides excellent LO-toRF and LO-to-IF leakage, typically better than -40 dBm. The IF output is designed to provide a typical voltage conversion gain of 7.8 dB when loaded into a 200 Ω load. The wide frequency range of the open collector IF output allows the ADL5801 to be used as an upconverter for a variety of transmit applications.

The ADL5801 is fabricated using SiGe high-performance integrated circuit technology. The device is housed in a compact 4 mm × 4 mm 24-lead LFCSP package and operates over the -40°C to +85°C temperature range. There is also an evaluation committee.

Typical performance characteristics

Broadband Balun Downconversion Mode

VS=5 V, TA=25°C, VSET=3.8 V, IF=153 MHz, unless otherwise noted, measured using a typical circuit schematic with a low-side local oscillator (LO). The insertion loss of the input and output baluns ( TC1-1 -13M+, TC4-1W+) was extracted from the gain measurements.

Downconverter Mode with MINI-CIRCUITS® TC1-1-43M+ Input Balun

VS=5 V, TA=25°C, VSET=3.8 V, IF=211 MHz, measured using typical circuit diagram with low-side local oscillator (LO) unless otherwise noted. Gain measurements include insertion loss for input and output baluns (TC1-1-43M+, TC4-1W+).

Downconverter mode with JOHANSON 3.5ghz input balun

VS=5 V, TA=25°C, VSET=3.6 V, IF=153 MHz, measured using typical circuit diagram with low-side local oscillator (LO) unless otherwise noted. Gain measurements include insertion loss for input and output baluns (3600BL14M050, TC4-1W+).

JOHANSON 5.7ghz down conversion mode

VS=5 V, TA=25°C, VSET=3.6 V, IF=153 MHz, measured using typical circuit diagram with low-side local oscillator (LO) unless otherwise noted. Gain measurements include insertion loss of input and output baluns (5400BL14B050, TC4-1W+).

900 MHz output matching upconverter mode

VS=5 V, TA=25°C, VSET=3.6 V, RF=153 MHz, measured using typical circuit diagram with low-side local oscillator (LO) unless otherwise noted. The insertion loss of the input and output baluns (TC1-1-13M+, TC4-14) is included in the gain measurement.

Incentive performance

All spur tables are (N x fRF) - (M x fLO) and are measured using a standard evaluation committee (see Evaluation Committee section). Mixer spurious products are measured in decibels and are related to the carrier (dBc) of the IF output power level. Data is only measured for frequencies less than 6GHz. The typical noise floor for the measurement system is -100 dBm.

900 MHz downconversion performance

VS=5 V, VSET=3.8 V, TA=25°C, RF power=0 dBm, low power=0 dBm, fRF=900 MHz, fLO=703 MHz, Z0=50Ω.

1900 MHz downconversion performance

VS=5 V, VSET=3.8 V, TA=25°C, RF power=0 dBm, low power=0 dBm, frequency=1900 MHz, frequency=1703 MHz, Z0=50Ω.

2600 MHz downconversion performance

VS=5 V, VSET=3.8 V, TA=25°C, RF power=0 dBm, low power=0 dBm, fRF=2600 MHz, fLO=2350 MHz, Z0=50Ω.

3800 MHz downconversion performance

VS=5 V, VSET=3.8 V, TA=25°C, RF power=0 dBm, low power=0 dBm, fRF=3800 MHz, fLO=3500 MHz, Z0=50Ω.

5800 MHz downconversion performance

VS=5 V, VSET=3.8 V, TA=25°C, RF power=0 dBm, low power=0 dBm, fRF=5800 MHz, fLO=5600 MHz, Z0=50Ω.

806MHz upconversion performance

VS=5 V, VSET=3.8 V, TA=25°C, RF power=0 dBm, low power=0 dBm, fRF=140 MHz, fLO=946 MHz, Z0=50Ω.

2210 MHz up-conversion performance

VS=5 V, VSET=4.0 V, TA=25°C, RF power=0 dBm, low power=0 dBm, frequency=140 MHz, frequency=2350 MHz, Z0=50Ω.

Circuit Description

The ADL5801 includes a double-balanced active mixer with 50Ω input impedance and 250Ω output impedance. In addition, the ADL5801 integrates a local oscillator (LO) amplifier and an RF power detector, which can be used to optimize the dynamic range of the mixer. RF and LO are differential, providing the maximum available bandwidth at the input and output ports. The LO can also operate with a 50Ω input impedance, with a choice of differential or single-ended operation. Input, output and LO ports can operate over a very wide frequency range. The ADL5801 can be configured as a downconversion mixer or an upconversion mixer.

The ADL5801 can be divided into the following parts: LO amplifier and divider, RF voltage-to-current (V-to-I) converter, mixer core, output load, RF detector, and bias circuit. A simplified block diagram of the device is shown in Figure 87. The LO block generates a pair of differential LO signals to drive the two mixer cores. The RF input power is converted into RF current by a V-to-I converter, which is then fed into two mixer cores. The mixer's internal differential load provides a broadband 250Ω output impedance from the mixer. The reference current for each section is generated by the bias circuit and can be enabled or disabled using the ENBL pin. Each part of the ADL5801 will be described in detail below.

LO Amplifiers and Splitters

The LO input is conditioned by a series of amplifiers to provide good control and limited LO swing to the mixer core, resulting in an excellent input IP3. Amplify the LO input with a broadband low noise amplifier (LNA) followed by an LO limiting amplifier. The LNA input impedance is nominally 50Ω. The local oscillator circuit has low additive noise and good mixer noise figure and output noise under RF blocking. For best performance, the LO input should be driven differentially, but at a lower frequency; single-ended drive is acceptable.

RF Voltage to Current (V-TO-I) Converter

The differential RF input signal is applied to a V-to-I converter that converts the differential input voltage to output current. The V-to-I converter provides 50Ω input impedance. The V-to-I segment bias current can be adjusted up or down using the VSET pin. Turning up the current improves the input at IP3 and P1dB, but reduces the noise figure of the SSB. Lowering the current improves the noise figure of the SSB, but reduces the input to IP3 and P1dB. Conversion gain remains nearly constant over a wide range of VSET pin settings, allowing dynamic tuning of the part without affecting conversion gain.

mixer core

The ADL5801 has a double balanced mixer using high performance SiGe NPN transistors. The mixer is based on a Gilbert cell design of four cross-connected transistors.

Mixer output load

The mixer load is connected to the positive supply using a pair of 125Ω resistors. This provides a differential output resistance of 250Ω. The mixer output should be pulled externally to the positive supply through a pair of RF chokes or an output transformer using a center tap connected to the positive supply. These components can be eliminated when the mixer core current is low, but then both the P1dB input and the IP3 input are reduced.

Mixer load outputs can range from direct current (dc) to approximately 600 MHz to 200Ω loads. For upconversion applications, the mixer load can be matched using off-chip matching components. The transfer operation can be up to 3ghz. See the Application Information section for more information on matching circuits.

RF detector

The RF power detector is partially buffered from the V-to-I converter. The detector has a power response range of approximately -25 dBm to 0 dBm and provides a current output. When a large RF signal is present at the mixer input, the output current is designed to be connected to the VSET pin to increase the mixer core current. An external capacitor can be used to adjust the response time of this function. If not used, the DETO pin can be left open or grounded.

The detector was characterized under broadband balun section conditions in downconverter mode. Pin 11 (DETO) is connected to pin 10 (VSET) and the voltage on these pins is plotted against RF input power levels, temperature and many devices.

Under these conditions, input IP3, gain and supply current were also recorded. The results are shown in Figures 89 to 91.

Bias circuit

The bandgap reference circuit generates the reference current used by the mixer. Bias circuits and internal detectors can be enabled and disabled using the ENBL pin. Pulling the ENBL pin high turns off the bias circuit and internal detector. However, the ENBL pin does not change the current in the LO segment and, therefore, does not provide a true power-down feature. When the ENBL pin is pulled high, the device can be operated by applying an external voltage to the VSET pin or by connecting a resistor from the VSET pin to the positive supply. Internally, the VSET pin has a series resistor and diode to ground; therefore, driving the pin with a simple voltage divider is not enough. Table 4 lists some typical values for this resistor along with the resulting VSET value and supply current when the ENBL pin is set high. Use Table 4 to select the appropriate value of R10 (see Figure 110) to achieve the desired mixer bias level. In this mode of operation, the VSET pin cannot be left floating, and placeholders R7 and R9 must remain open.

If the ENBL pin is pulled low, the device's bias circuits and internal detectors will be enabled. In this mode, the device can be operated by applying an external voltage to the VSET pin or connecting a resistor from the VSET pin to the positive supply. Table 5 lists some typical values for this resistor along with the resulting VSET value and supply current when the ENBL pin is set low. Use Table 5 to select the appropriate value of R10 (see Figure 110) to achieve the desired mixer bias level. In this mode of operation, R7 and R9 must remain open.

Optionally, the VSET pin can be connected to the DETO pin to provide dynamic mixer bias control using an internal detector. Figure 92 is a comparison of input IP3 performance versus RF input power level at 2GHz when the ENBL pin is pulled high and low. Pulling ENBL high improves linearity between input power levels, while pulling ENBL low improves IP3 performance at higher power levels. The device also exhibits better excitation performance when the ENBL pin is pulled high. Figure 95 is a comparison of 4LO-5RF and 6LO-7RF spurs with RF input power levels at ENBL high and low at 900 MHz.

Figure 93 is a graph of input IP3 and RF input power levels for different VSET levels at 2ghz when the ENBL pin is pulled high. In this mode of operation, the device exhibits the best linearity at a VSET level of 4.0v. As mentioned earlier, the VSET level can be set using an external voltage or by placing a resistor from the VSET pin to the positive supply. Figure 94 is a graph of input IP3 versus RF input power level for a VSET level of 4.0v when ENBL is pulled high under different temperature and frequency conditions. The device performs well in different frequency ranges and exhibits excellent temperature sensitivity.

application information

basic connection

The ADL5801 is designed to convert between radio frequency (RF) and intermediate frequency (IF). For up-conversion and down-conversion applications, RFIP (Pin 16) and RFIN (Pin 15) must be configured as input interfaces. IFOP (pin 20) and IFON (pin 21) must be configured as output interfaces. A separate bypass is required near each power supply pin (pin 7, pin 13, pin 18, and pin 24), VSET control pin (pin 10), and DETO detector output pin (pin 11) capacitor. When the on-chip detector is selected to form a closed loop, automatically controlling the VSET pin, R7 can be filled with a 0Ω resistor. Alternatively, just use a jumper between the VSET and DETO test points for evaluation. Figure 96 illustrates the basic connections for the operation of the ADL5801.

RF and low port

The RF and low input ports are designed for differential input impedance of approximately 50Ω. Figure 97 and Figure 98 illustrate the RF and LO interfaces, respectively. It is recommended to drive each RF and low differential port through a balun for best performance. AC coupling for RF and low ports is also required. Using appropriately sized capacitors can help improve input return loss at the desired frequency. Table 6 and Table 9 list the recommended components for various RF and LF bands in up-conversion and down-conversion modes. Characterization data is available in the Typical Performance Characteristics section.

IF port

The IF port has an open collector, differential output interface. The open collector output must be biased using one of the schemes shown in Figure 99 and Figure 100.

Figure 99 shows the use of a center-tapped impedance transformer. The turns ratio of the transformer should be chosen to provide the desired impedance transformation. In the case of a 50Ω load impedance, a 4:1 impedance ratio transformer should be used to convert the 50Ω load to a 200Ω differential load at the IF output pins.

Figure 100 shows a differential IF interface using a pull-up choke inductor to bias the open collector output. The shunt impedance of the choke inductor used to couple the DC current to the mixer core should be large enough so that it does not drop the output current until it reaches the intended load. In addition, the DC current handling capability of the selected choke inductor must be at least 45 mA.

The self-resonant frequency of the selected choke inductor must be higher than the expected IF frequency. A variety of suitable choke inductors are available from manufacturers such as Coilcraft® and Murata. On the IF output, an impedance conversion network may be required to convert the final load impedance to 200Ω. Table 8 lists the recommended components for the IF port in up-conversion and down-conversion modes.

Downconvert to low frequency ZL

For downconversion to lower frequencies, the device should be biased with a resistor at the output. The IF output common mode voltage of the unit should be 3.75v to ensure optimum performance. Figure 101 provides an example setup for downconverting a 900 MHz input signal to 100 kHz. In the setup shown in Figure 101, the output of the device is biased by a 50Ω resistor. In this mode of operation, the device exhibits a conversion gain of 2.0 dB when a 500 MHz signal is downconverted to 100 kHz, 10 kHz, or 1 kHz.

broadband service

The ADL5801 can support input frequencies from 10 MHz to 6 MHz. For applications requiring broadband frequency coverage, the device can be operated using a broadband balun, such as the small circuit TCM1-63AX+. Figure 102 shows an example setup configuration for populating the microcircuit TCM1-63AX+balun on the RF and LO ports. This single setup solution provides the option to utilize the full input frequency range of the device.

Figures 103 to 105 show the performance of a mixer populated with a small circuit TCM1-63AX+ on the RF and LO ports.

The device maintains 20 dBm or higher input IP3 and -2 dB or higher conversion gain over the 10 MHz to 6 GHz frequency band.

Single-ended driver for RF and low input

The RF and LO ports of the active mixer can be driven single-ended without the need for a balun for single-ended operation. In this configuration, the unused RF and LO ports should be AC grounded with 1nf capacitors. Figure 106 depicts a recommended setup configuration for operating the device in single-ended mode.

Figure 107 to Figure 109 show the performance of the mixer in single-ended mode.

Evaluation Committee

There is an evaluation board for the ADL5801. The standard evaluation board is fabricated from Rogers® RO3003 material. Each RF, LO, and IF port is configured for single-ended signaling through a balun transformer. A schematic of the evaluation board is shown in Figure 110. Table 9 describes the various configuration options for the evaluation board. The layout of the board is shown in Figure 111 and Figure 112.

Dimensions