Features and Benefits

▪ Low Rds (on) output

▪ Automatic current decay mode detection/selection

▪ Mixed and slow current decay modes

▪ Low power synchronous rectification

▪ Internal UV exposure

▪ Cross current protection

▪ 3.3 and 5V compatible logic supply

▪ Thermal shutdown circuit

▪ Short-circuit protection to ground

▪ Short-circuit load protection

▪ Five selectable step modes: full step, 1/2 step, 1/4 step, 1/8 step and 1/16 step

illustrate

The A4988 is a complete microstepping motor driver with built-in translation for easy operation. It is designed to operate bipolar stepper motors in full, half, four, eight and sixteen order modes with output drive capacities up to 35V and ±2A. The A4988 includes a fixed off-time current regulator with the ability to operate in slow decay or mixed decay modes.

Translation is the key to A4988's ease of implementation. Just a single pulse at the step input can drive the motor one microstep. There are no phase sequence tables, high frequency control lines or complex programming interfaces. The A4988 interface is ideal for applications where complex microprocessors are unavailable or overburdened.

During step operation, the chopper control in the A4988 automatically selects the current decay mode: slow or mixed. In mixed decay mode, the device is set to decay fast for a portion of the fixed off time and then to slow decay for the remainder of the off time. Hybrid decay current control reduces motor noise, improves step accuracy, and reduces power consumption.

Internal synchronous rectification control circuitry is provided to improve power consumption during PWM operation. Internal circuit protections include: hysteretic thermal shutdown, undervoltage lockout (UVLO), and cross-current protection. No special power-up sequence is required.

The A4988 is available in a 5 mm x 5 mm surface mount QFN package (ET) with a nominal total package height of 0.90 mm and an exposed pad for enhanced thermal dissipation. It is lead (Pb) free (suffix -T), with a 100 % matte tin leadframe.

Functional block diagram

Function description

device operation. The A4988 is a complete microstepper motor driver with a built-in converter for simple operation and minimal control lines. It is designed to operate bipolar stepper motors in full, half, fourth, eighth and sixteenth order modes. The two output full bridges and all N-channel DMOS field effect transistors are regulated using a fixed off-time PWM (pulse width modulated) control circuit. In each step, the current of each full bridge is set by the value of its external current sense resistors (RS1 and RS2), the reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the converter) ).

At power-up or reset, the converter sets the digital-to-analog converter and phase current polarity to the initial initial state (as shown in Figures 9 to 13), and sets the current regulator to a mixed decay mode for both phases. When a step command signal appears on the step input, the converter automatically sequences the DAC to the next stage and current polarity. (See Table 2 for the current level sequence.) The microstep resolution is set by the combined effects of the MSx inputs, as shown in Table 1.

When stepping, if the new output level of the DAC is lower than its previous output level, the attenuation mode of the active full bridge is set to mixed. If the new output level of the DAC is higher or equal to its previous level, the decay mode of the active full bridge is set to slow. This automatic current decay selection improves microstepping performance by reducing current waveform distortion caused by motor back EMF.

Microstep selection (MSx). The microstep resolution is set by the voltage on the logic input MSx, as shown in Table 1. The MS1 and MS3 pins have 100 kΩ pull-down resistors, and the MS2 pin has a 50 kΩ pull-down resistor. When changing the step mode, the change does not take effect until the next rising edge.

If the step mode is changed without a converter reset, and the absolute position must be maintained, the step mode must be changed at a step position common to both step modes in order to avoid missing steps. When the device is powered down or reset due to a TSD or overcurrent event, the converter is set to the initial position, which by default is the same as for all step modes.

Mixed decay operations. The bridge operates in mixed decay mode, at power up and reset, during normal operation, according to the ROSC configuration and sequence of steps, as shown in Figures 9 to 13. In mixed decay mode, when the trigger point is reached, the A4988 initially enters a fast decay interval for 31.25% of the off time tOFF. After that, it switches to slow decay for the remainder of the time. The next page will show the timing diagram for this function.

Typically, mixed decay is only necessary when the current in the winding changes from a higher value to a lower value (determined by the state of the converter). For most loads, the automatic selection of mixed decay is convenient because it minimizes ripple when the current is rising and prevents slipping when the current is falling. For some applications that require microstepping at very low speeds, the lack of back EMF in the windings can cause the current to rapidly increase in the load, resulting in missed steps. as shown in picture 2. By pulling the ROSC pin to ground, the mixed decay is set to 100% of the active time, for both rising and falling currents, and prevents missing steps, as shown in Figure 3. If this is not an issue, it is recommended to use the auto-selected mixed decay as it will produce reduced ripple current. For more information, see the Fixed Off Hours section.

Small current microstepping. Ideal for applications where the minimum on-time prevents the output current from regulating to the programmed current level on low current steps. To prevent this, the device can be set to operate in a mixed decay mode on the rising and falling portions of the current waveform. This function is achieved by shorting the ROSC pin to ground.

In this state, the shutdown time is internally set to 30 microseconds.

Reset input ("R" or "E" or "S" or "E" or "T"). The "R", "E", "S", "E", "T" inputs set the converter to a predefined initial state (as shown in Figures 9 to 13) and turn off all FET outputs. All step inputs are ignored until the "R" "E" "S" "E" "T" inputs are set to "High".

Step input (step). A low-to-high transition on the step input puts the translator in sequence and advances the motor one increment. The converter controls the input of the DACs and direc - the variation of the current in each winding. The size of the increment is determined by the combined state of the MSx input.

Direction Input (DIR). This determines the direction of rotation of the motor. Changes to this input will not take effect until the next rising edge.

Internal PWM current control. Each bridge is con-controlled by a fixed off-time PWM current control circuit, which limits the load current to a desired value ITRIP. Initially, a pair of diagonal source and sink FET outputs are enabled and current flows through the motor windings and current sense resistor RSx. When the voltage across RSx equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off the corresponding source driver and initiates a fixed off-time decay mode that sets the maximum current limit by selecting the voltages on the RSx and VREF pins. The transconductance function is approximated by the current-limited maximum value itrimax(A), which is given by:

where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the reference pin (V).

The DAC output reduces the VREF output to the current sense comparator in precise steps such that:

(See Table 2 for %itrimpax for each step.)

It is critical that the maximum rating (0.5 V) of the SENSE1 and SENSE2 pins is not exceeded.

fixed rest periods. The internal PWM current control circuit uses a one-shot circuit to control the duration that the DMOS FET remains off. The off time tOFF is determined by the ROSC terminal. The ROSC terminal has three settings:

▪ ROSC-off time relative to VDD is internally set to 30µs; decay modes are automatically mixed unless decay mode is set to slow in a full step.

▪ ROSC is directly related to ground time and is internally set to 30 microseconds; current decay is set to mixed and all step modes are increasing and decreasing current.

▪ The time for ROSC to pass through a resistor to ground is determined by the following formula; decay mode is automatically mixed for all step modes except full step mode which is set to slow.

blank. This function will blank the output of the current sense comparator when the internal current control circuit switches the output. The comparator output is shielded to prevent false overcurrent detection due to reverse recovery current of the clamp diode and switching transients associated with load capacitance. The blank time tBLANK (microseconds) is approximately:

Short-circuit load and short-to-ground protection.

If the motor wires are shorted together, or if one of the wires is shorted to ground, the driver will protect itself by sensing an overcurrent event and disabling the shorted driver, thus protecting the unit from harm. In the event of a short to ground, the device will remain disabled (locked) until the S''L''E''E''P' input goes high or the VDD supply is disconnected. Figure 4 shows a short-to-ground overcurrent event.

When the two outputs are shorted together, the current path is through the sense resistor. After the blanking time (≈1 μs) expires, the sense resistor voltage exceeds its trip value due to an overcurrent condition. This causes the driver to enter a fixed period of rest time. After the fixed shutdown time expires, the driver will be turned on again and the process will be repeated. In this case, the driver is completely immune to overcurrent events, but the short circuit is repeated for a period equal to the driver's fixed off-time. This situation is shown in Figure 5.

During a short-circuit load event, the positive and negative current spikes shown in Figure 3 are typically observed due to the directional change achieved by the mixed decay characteristics. As shown in Figure 6. In both cases, an overcurrent circuit protects the driver and prevents damage to the device.

Charge Pumps (CP1 and CP2).

A charge pump is used to generate a gate supply greater than VBB to drive the source side FET gate. A 0.1µF ceramic capacitor should be connected between CP1 and CP2. Additionally, a 0.1µF ceramic capacitor is required between VCP and VBB as a reservoir for operating the gate of the high-side FET.

According to EIA (Electronic Industries Alliance) specifications, the capacitor value should be ±15% of the maximum value of the Class 2 dielectric, or a tolerance of R.

This internally generated voltage is used to operate the slot side FET output. The nominal output voltage of the VREG terminal is 7 V. The VREG pin must be separated from ground with a 0.22µF ceramic capacitor. VREG is monitored internally. Under fault conditions, the FET outputs of the A4988 are disabled.

According to EIA (Electronic Industries Alliance) specifications, the capacitor value should be ±15% of the maximum value of the Class 2 dielectric, or a tolerance of R.

Enable input (. "E" "N" "A" "B" "L" "E" This input turns all FET outputs on or off. When set to logic high, the output is disabled. When set to logic low , the internal control enables the outputs as needed. The converter inputs STEP, DIR, and MSx, as well as the internal sequencing logic, remain active, independent of the "E" "N" "A" "B" "L" "E" input states.

closure. In the event of a fault, overtemperature (too high TJ), or undervoltage (on VCP), the A4988's FET outputs will be disabled until the fault condition is removed. On power-up, the UVLO (under-voltage lockout) circuit disables the FET output and resets the converter to its initial state.

Sleep mode (“S” “L” “E” “E” “P”. To minimize power consumption when the motor is not in use, this input disables large Part of the internal circuit. The S''L''E''E''P'' pin is logic low, and the A4988 enters sleep mode. The logic high allows normal operation and startup (at this time the A4988 drives the motor to the initial microstep position). When When emerging from sleep mode, a 1 ms delay is provided before issuing a step command in order for the charge pump to stabilize.

Mixed decay operations. The bridge operates in mixed decay mode, depending on the step sequence, as shown in Figures 9 to 13. When the trigger point is reached, the A4988 initially enters a fast decay interval of 31.25% off time (tOFF). After that, it switches to slow decay for the remainder of the time. The timing diagram for this function is shown in Figure 7.

Synchronous rectification. When a PWM off cycle

Triggered by an internal fixed off-time period, the load current cycles according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FET during current decay and effectively shorts the body diode of the low FET Rds(on). This greatly reduces power dissipation and can eliminate the need for external Schottky diodes in many applications. When the load current is close to zero (0A), the synchronous rectification is turned off, preventing the load current from reversing.

application layout

Layout. Printed circuit boards should use heavy duty ground planes. For optimum electrical and thermal performance, the A4988 must be soldered directly to the board. Pins 3 and 18 are internally fused, which provides a way to enhance heat dissipation. These pins should be soldered directly to an exposed surface on the PCB that is connected to thermal vias used to transfer heat to other layers of the PCB.

To minimize the effects of ground bounce and offset issues, it is important to have a low impedance single point ground, called a star ground, very close to the device. By connecting the pad to the ground plane directly below the A4988, this area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage at the input terminals remains stable.

The two input capacitors should be placed in parallel and as close as possible to the device power pins. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor (CIN2). This is necessary because the ceramic capacitor will be responsible for carrying the high frequency current to the element. The ground impedance of the sense resistors RSx should be very low as they must carry large currents while enabling very accurate voltage measurements through the current sense comparators. A long ground trace will cause an additional voltage drop, adversely affecting the comparator's ability to accurately measure the winding current. The distance between the SENSEx pin and the RSx resistor is very short, and the distance to the star ground below the device is very large and the impedance is very low. If possible, no other components should be present on the detection circuit.

ET package, 28-pin QFN with exposed thermal pad