feature

Single chip CCD analog front end

10-Bit, 13-MSPS, Single 3-V Supply

Operating the A/D Converter

Very low power: 150 MW typical, 2 MW

Power down mode

Differential nonlinear error:

Typical values are less than ±0.5 LSB

Integral nonlinear error:

Typical values are less than ±0.9 LSB

Programmable Gain Amplifier

0-dB to 36 dB gain range (0.045 dB/step)

Automatic or programmable optical black

Digital level and offset calibration

Filters and Bad Pixel Limits

Additional DAC for external analog

set up

Serial interface for register configuration

Internal reference voltage

48-pin TQFP package

application

digital camera

PC camera

describe

The TLV990-13 is a complete CCD signal processor/digitizer camera and PC camera application designed for digital stills. The TLV990-13 performs all the analog processing needed to maximize dynamic range, correct for various errors associated with the CCD sensor, and then digitize the result with an on-chip high-speed analog-to-digital converter (ADC).

The key components of the TLV990-13 include: an input clamp circuit for the CCD signal, a correlated dual-channel sampler (CDS), a programmable gain amplifier (PGA) with a gain range of 0 to 36 dB, two internal digital-to-analog Converter (DAC) for automatic or programmable optical black level and offset calibration, 10-bit, 13-MSPS pipelined ADC, one parallel data port for simple microprocessor interface, one serial port for configuration internal control Port registers, two additional DACs for external system control, and an internal voltage reference.

Designed in an advanced CMOS process, the TLV990-13 consumes 150 mW at 13 MSPS from a common 3-V supply and 2 mW in power-down mode.

Its single 3-V operation, very low power consumption and fully integrated analog processing circuitry make the TLV990-13 an ideal CCD signal processing solution for digital camera and PC camera applications.

The device is housed in a 48-pin TQFP package and operates over a temperature range of -20°C to 75°C.

Functional block diagram

Absolute Maximum Ratings are above operating free air temperature (unless otherwise noted)

Supply Voltage, AVDD, DVDD, DIVDD – 0.3 V to 6.5 V.

Analog input voltage range –0.3 V to AV. DD+0.3V

Digital input voltage range –0.3 V to DV. DD+0.3V

Operating virtual junction temperature range, TJ–40. Celsius to 150 Celsius

Operating free air temperature range, TA–20. Celsius to 75 degrees Celsius

Storage temperature range, Tstg–65. Celsius to 150 Celsius

Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 . Stresses other than those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are just stress levels, and

Under these or any other conditions beyond those indicated in the Recommended Operating Conditions, the functional operation of the equipment

Alluded to. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Recommended Operating Conditions

Typical features

Model TLV990-13 3-V, 10-bit, 13-MSPS area array CCD analog front end

Typical features

application information

working principle

CDS and PGA

The output of the CCD sensor is first fed to the correlated double sampler (CDS) through the CCDIN pin. This samples and holds the CCD signal during the reset reference interval and the video signal interval. Subtracting the two voltage levels, CDS removes the low frequency noise from the CCD sensor output to obtain the voltage difference between the CCD reference level and the video level for each pixel. 2. Sample/hold control pulses (SR and SV) are required to perform the CDS function.

The CCD output is capacitively coupled to the TLV990-13. The AC coupling capacitor is clamped to establish the proper DC bias by the CLCCD input during the dummy pixel interval. The input bias of the TLV990-13 is set to 1.2 V. Typically, CLCCDs are applied at the line rate of the sensor. A capacitor, the value of which is larger than the input AC coupling capacitor, should be connected between the CLREF pin and AGND. When running the TLV990-13 at maximum speed, the CCD internal source resistance should be smaller than 50 ohms. Otherwise a CCD output buffer is required.

After the CDS function is complete, the signal is sent to the PGA. The PGA gain can be adjusted from 0 to 36 dB via serial port programming of the internal gain register. The PGA is digitally controlled on a linear decibel scale with 10-bit resolution, producing 0.045dB gain steps. The gain can be expressed by the following formula, gain = PGA code × 0.045dB where the range of the PGA code is 0 to 767 .

analog to digital converter

The ADC uses a pipelined structure to achieve high throughput and low power consumption. Fully differential implementation and digital error correction ensure 10-bit resolution. The delay of ADC data output is 6 ADCCLK cycles, as shown in Figure 1. Pulling the OE pin (pin 24) high sets the ADC output to high impedance.

User DAC

The TLV990-13 includes two user DACs that can be used for external analog settings. The output voltage can be set independently for each DAC, and its voltage range is from 0v to the supply voltage with 8-bit resolution. When the user DAC is not used in the camera system, it can be programmed into a control bit in the standby mode control register.

Internal timing

As mentioned earlier, the SR and SV signals are required to operate the CDS. The user needs to synchronize the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to an external circuit consisting of the ADCCLK signal, which is also used internally to control the ADC and PGA operations. This requires that the positive half cycle of the ADCCLK signal always falls between two adjacent SV pulses, and the user can then fine-tune the ADCCLK timing relative to the CDS timing for best performance.

The CLCCD signal is used to activate input clamping and the OBCLP signal is used to activate automatic optical black and offset correction.

working principle

Input blanking function

The input of the TLV990-13 may experience large input transients for a certain period of time during operation, which may saturate the input circuit and have a long recovery time. To prevent circuit saturation, the TLV990-13 includes an input blanking function that prevents the input signal by disabling the CDS operation each time the BLKG input is pulled low. After BLKG is pulled low, the TLV990-13 digital outputs will be set by the blanking data register.

Note:

If the BLKG pulse precedes the OBCLP pulse, the rising edge of the BLKG pulse and the falling edge of the OBCLP pulse. If the BLKG pulse is located after the OBCLP, the falling edge of the OBCLP and the falling edge of the BLKG pulse shall equal the number of optical black pixels per row + 4.

Three-wire serial interface

A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the TLV990-13. The serial clock SCLK can run at a maximum frequency of 40 MHz. Serial data SDIN of 16 is a bit long. Two leading zero bits followed by four address bits, the internal register is updated, and then 10 bits of data are written to the register. The CS pin must be held low to enable the serial port. After CS falls, the data transfer is initiated by the incoming SCLK.

SCLK polarity can be selected by pulling the SCKP pin high or low.

Device reset

When pin reset (pin 29) is pulled low, all internal registers are set to their default values. The device also resets when it first starts up. Additionally, the TLV990-13 has a software reset function that resets the device when control bits are written to the control registers.

See the Register Definitions section for register default values.

voltage reference

A nominal 1.5 V internal precision voltage reference is provided. The reference voltage is used to generate the ADC reference voltage of 1V, and the reference voltage + is 2V. It is also used to set the clamping voltage. All internally generated voltages are fixed values and cannot be adjusted.

Off mode (standby)

The TLV990-13 implements both hardware and software power down modes. Pulling pin STBY (pin 30) low puts the device into a low power standby mode. The total supply current drops to around 0.6mA. Power-down mode can also be activated by setting the power-down control bit in the a control register. The user can still program all internal registers in power down mode.

power supply

The TLV990-13 has several power pins. Each major internal analog block has a dedicated AVDD power pin. All internal digital circuits are driven by DVD. Both AVDD and DVDD are nominally 3 volts.

The DIVDD and DIGND pins power the output digital drivers (D9–D0). DIVDD operates from 1.8v to 4.4v independently of DVDD. This allows to output a different supply voltage than the required digital asic interface.

working principle

Grounding and Decoupling

All ground pins of the TLV990-13 are not connected internally and must be connected externally to PCB ground. General practices should be applied to PCB design to limit feedback of high frequency transients and noise into the supply and reference lines. This requires that the supply and reference pins be adequately bypassed.

In the case of power supply decoupling, a 0.1µF ceramic chip capacitor is sufficient to keep the impedance low over a wide frequency range. The recommended external decoupling of the three voltage reference pins is due to the fact that their effectiveness depends heavily on the proximity of the individual supply pins. Decoupling capacitors should be placed as close as possible to the supply pins.

To reduce high frequency and noise coupling, it is strongly recommended that the digital and analog grounds be shorted immediately outside the package. This can be done via the DGND and AGND under the package.

Automatic optical shading correction In the TLV990-13, light shading and system channel offset correction are performed by an automatic digital feedback loop. Two DACs are used to compensate for channel shift and optical black shift. The coarse correction DAC (CDAC) is located before the PGA gain stage, while the fine correction DAC (FDAC) is located after the PGA gain stage. The digital calibration system is capable of correcting light black and channel offset accurate to one ADC LSB.

Whenever the OBCLP input is pulled low, the TLV990-13 automatically starts auto-calibration. The OBCLP pulse width should be sufficient to cover one positive half cycle of ADCCLK.

For each row, pass through the ADC. Digital circuitry averages the data during optical black pixels. A digital comparison of the averaged results stores the desired output code in the Vb register (40H by default), then the control logic adjusts the FDAC to make the ADC output equal to Vb. If the offset is outside the range of FDAC (±255 ADC LSB), the error is corrected by CDAC and FDAC. The CDAC increments or decrements one CDAC LSB, depending on whether the offset is negative or positive, until the output is within the range of the FDAC. The remaining residue was corrected by FDAC.

The relationship between FDAC, CDAC, and ADC in terms of ADC lsb count is as follows:

1 FDAC LSB = 1 ADC LSB,

1 CDAC LSB = PGA linear gain × n ADC LSB.

where n is:

4:0=

3 for 64 = < gain code < 96

2:96=

1:128=

For example, if PGA gain=2 (6 dB), then 1 CDAC LSB=2 x 4 ADC LSB=8 ADC LSB.

After auto-calibration is complete, the digital output of the ADC during the CCD signal interval can be used

The following equation:

ADC output [D9–D0] = CCD U input × PGA gain + Vb, where Vb is the desired black level selected by the user. The total offset, including the optical black offset, is calibrated to be equal to Vb by adjusting the offset correction dac during the auto-calibration process.

working principle

Automatic Optical Black and Offset Correction (continued)

During averaging, a weighted rolling average of optical black pixels is performed. The weighting factor can be programmed in control register 2. The weighting factor determines the convergence speed of the digital signal and realizes filtering in the CCD signal processor. A weight factor close to 1 will speed up the convergence. When the weighting factor is reduced to the minimum value of 1/128, the convergence speed of digital filtering is reduced.

The algorithm also takes into account hot and cold pixels. Hot optically black pixels are defective pixels that generate excessive charge, while cool pixels are pixels that generate little or no charge. A digital comparator compares the digitized optical black pixels to user-selected limits for hot and cold pixels. If the black pixel value is out of range, the hot or cold pixel is replaced with the value of the previous pixel. Due to different exposure times, there may be a sudden optical black level shift at the beginning of each frame. Therefore, fast optical black level correction is required. The user can set an internal control bit (SOF bit in control register 2) to automatically disable the hot/cold pixel limit and set the digital filter weighting factor to 1 (equivalent to a row average). In this way, the first row of each frame can be processed very quickly. The number of black pixels in each row is programmable. The number of black pixels per row can be an average of 2N, where N can be any integer between 0 and 6.

The auto-calibration feature can be bypassed if the user wishes to program the offset DAC registers directly.

Switching from auto-calibration mode to direct programming mode requires two register writes. The offset DAC control bits in the control register must first be changed; then the register is loaded into the offset DAC register for proper error correction. If the total offset, including the optical black level, is less than ±255 ADC LSB, only the FDAC needs to be programmed. When switching from direct programming mode to auto-calibration mode, the previous DAC register value, not the default DAC register value, is used as the starting offset.