feature

●1.25 microsecond throughput time

●Standard ± 10V input range

●Minimum 69dB SINAD, input 250kHz

The maximum inlet is ±3/4 LSB, and the maximum DNL is ±1 LSB

●Internal reference

● Equipped with S/H, REF, clock, etc.

● Parallel data with latch

●28-pin SOIC

illustrate

The ADS7810 is a complete 12-bit sampling A/D using state-of-the-art CMOS architecture. It contains a complete 12-bit capacitive SAR A/D with input S/H, reference, clock, microprocessor interface and tri-state output drivers.

The ADS7810 has a sampling rate of 800kHz and is guaranteed over temperature. Laser-trimmed scaling resistors provide an industry-standard ±10V input range, while the innovative design allows operation from ±5V supplies.

The 28-pin ADS7810 is available in a plastic SOIC and is fully specified for operation over the industrial –40°C to +85°C range.

Typical performance curve

T=+25°C, fS=800kHz, +VDIG=+VANA=+5V, -VANA=-5V, using internal reference and input 50Ω resistors shown in Figure 4b unless otherwise specified.

Basic operation

Figure 1 shows the basic circuit for operating the ADS7810. Driving R/C (pin 23) low for at least 40ns will initiate a conversion. BUSY (pin 25) will go low and remain low until the conversion is complete and the output registers have been updated. Data will be output in binary 2's complement with the MSB on D11 (pin 6). Busy high can be used to lock data. When busy, all conversion commands will be ignored.

The ADS7810 will begin tracking the input signal at the end of the conversion. Allow 1.25 microseconds between transition commands to ensure accurate acquisition of new signals.

start conversion

The combination of CS (Pin 24) and R/C (Pin 23) lowers the sample/hold of the ADS7810 for at least 40ns to hold the state and start a conversion. Busy (pin 25) will disappear until the conversion is complete and the internal output registers have been updated. The new switch-on-busy-low command will be ignored.

The ADS7810 will start tracking the input signal transitions at the end. Allow 1.25 microseconds between transition commands to ensure accurate acquisition of new signals. Refer to Table 1 for a summary of CS, R/C, and BUSY states. Figures 2 and 3 are timing parameters.

CS and R/C are triggered internally or horizontally. There is no requirement to enter a low first to initiate the conversion. If CS or R/C starts a conversion, make sure the less critical input is low at least 10ns before the start input.

In order to reduce the number of control pins, the CS can be placed in a lower position to use R/C to control the read and transfer modes. Note that when R/C is high and no conversion is in progress. See the "Read" and "Convert" modes in the Reading Data section.

read data

The ADS7810 outputs fully parallel data in binary 2's complement data format. The parallel output will activate when R/C (pin 23) is high, CS (pin 24) is low, and no conversion will occur. Any other combination will tristate the parallel outputs. Valid conversion data can be read in fully parallel 12-bit words on D11-D0 (pins 6-13 and 1518). The ideal output codes are shown in Table 2.

After the conversion is complete and the output register has been updated, busy (pin 25) will go high. The latest converted valid data will be at D11-D0 (pins 6-13 and 15-18). Busy high can be used to lock data. See Table 3 and Figures 2 and 3.

Note: For best performance, the external data bus connected to D11-D0 should not be active during conversions. Switching noise from external asynchronous data signals can cause digital feedthrough and degrade converter performance.

The number of control lines can be reduced by layering CS using R/C to initiate conversions and activate the output mode of the converter when it is low. See Figure 2.

input range

The ADS7810 offers a standard ±10V input range. Figures 4a and 4b show the circuit connections required for the ADS7810 (with or without trim). Offset and full-scale error (1) specifications are tested and guaranteed with the 50Ω resistor shown in Figure 4b. This external resistor makes it possible to trim the offset by ±50mV using a trim pot or trim DAC. This resistor can be omitted if the offset and gain errors are to be corrected in software, or are negligible for a particular application. See the calibration section of the datasheet for details.

The nominal input impedance of 3.125kΩ is derived from the combination of the internal resistor network shown on the first page of the product data sheet and the external 50Ω resistor. The input resistor divider network provides inherent overvoltage protection, guaranteed to be at least ±25V. 50Ω, 1% resistance will not affect the accuracy or drift of the converter. It has little effect on internal resistance and does not require tighter tolerances.

Note: Internal resistance values shown are for reference only. The exact value can vary by ±30%. This is true for all resistors inside the ADS7810. Each resistor divider is trimmed for proper voltage division.

Notes: (1) Full-scale error includes offset and gain errors measured at +FS and -FS.

calibration

The ADS7810 can be tailored in hardware or software. Since offset directly affects gain, offset should be trimmed before gain.

hardware calibration

To calibrate the offset and gain of the ADS7810, install the appropriate resistors and potentiometers as shown in Figure 4a. The calibration range for bipolar zero is ±50mV and the calibration range for full scale is ±120mV.

Potentiometer P1 and resistor R1 constitute an offset adjustment circuit, and P2 and R2 constitute a gain adjustment circuit. The exact value is not important. R1 and R2 should not be greater than the values shown. They can easily be made smaller to provide a wider range of adjustment. Lowering these values below 15% of the indicated values may begin to adversely affect the operation of the converter.

P1 and P2 can also be made larger to reduce power consumption. However, larger resistors push the useful adjustment range to the edge of the potentiometer. To maintain reasonable sensitivity, P1 should probably not exceed 20kΩ and P2 100kΩ.

software calibration

To calibrate the offset and gain of the ADS7810, no external resistors are required. See the "No Calibration" section for details on the effects of external resistors.

No calibration

The circuit connection is shown in Figure 4b. Note that the actual voltage drop across the 50Ω resistor is nearly two orders of magnitude lower than the voltage across the internal resistor divider network. This should be taken into account when choosing the accuracy and drift specifications of the external resistors. In most applications, a 1% metal film resistor is sufficient.

In some applications, the external 50Ω resistor shown in Figure 4b may not be required. This resistor provides trimming capability for the offset and compensates for slight gain adjustments inside the ADS7810. Not using a 50Ω resistor will result in a small gain error, but will not affect the inherent offset error. Figure 5 shows the typical transfer function characteristics of the circuit with and without 50Ω resistors.

refer to

The ADS7810 can operate with its internal 2.5V reference or with an external reference. The internal reference can be bypassed by applying an external reference to pin 3. The reference voltage at REF is buffered internally and output on the lid (pin 4).

REF

REF (Pin 3) is the input for the external reference or the output for the internal 2.5V reference. The 0.1µF capacitor should be connected as close as possible to the reference pin. The capacitor and REF's output resistance create a low-pass filter to limit band noise on the reference. Using a smaller capacitor value will introduce more noise to the reference signal, thereby reducing the signal-to-noise ratio and the signal-to-noise ratio. The internal reference should not be used for sink or source currents greater than 100 µA. Also, all external loads should be static loads.

The external reference is in the range of 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage can increase the full-scale and LSB size of the converter, thereby improving the signal-to-noise ratio.

CAP

CAP (pin 4) is the output of the internal reference buffer. The 10µF tantalum capacitor should be placed as close as possible to the capacitor to provide the best switching current for the CDAC throughout the conversion cycle and to compensate for the output of the buffer. Using capacitors smaller than 1µF can cause the output buffer to oscillate and there may not be enough charge available for the CDAC. Capacitance values greater than 10µF have little effect on improving performance. When using the internal reference voltage or providing 80% of the reference voltage externally, the voltage on the cover pin is about 2V.

layout

that power

Most of the power of the ADS7810 is used in analog and static circuits, which should be considered analog components. For best performance, connect the analog and digital +5V supply pins to the same +5V supply, and connect the analog and digital grounds together.

For best performance, the ±5V supply can be generated from any analog supply used for the rest of the analog signal conditioning. Simple regulators can be used if a ±12V or ±15V supply is present. The +5V supply for the A/D should be separate from the +5V supply used for the system's digital logic. Connecting +VDIG (pin 27) directly to the digital supply can degrade converter performance due to switching noise from the digital logic.

While it is not recommended to use a digital power supply to power the converter, make sure the power supply is properly filtered. Whether using a filtered digital supply or a regulated analog supply, VDIG and VANA should be connected to the same +5V supply.

ground

There are three ground pins on the ADS7810. DGND (pin 22) is the digital power ground. AGND2 (pin 5) is the analog power ground. AGND1 (pin 2) is the ground reference for all analog signals inside the A/D. AGND1 is more susceptible to current induced voltage drops and must have a minimal resistive path back to the power supply.

All ground pins of the ADS should be tied to an analog ground plane, separate from the system's digital logic ground, for best performance. Both analog and digital ground planes should be connected to the "system" ground as close to the power supply as possible. This helps prevent dynamic digital ground currents from modulating analog ground to power ground through the common impedance.

signal conditioning

In many CMOS A/D converters, the FET switches used for sample and hold release a large amount of charge injection, which can cause the drive op amp to oscillate. The resistive front end of the ADS7810 attenuates this charge and reduces its size, significantly reducing the burden on external input amplifiers or buffers.

However, keep in mind that maintaining signal integrity with voltage fluctuations of ±10V and frequencies of several hundred kilohertz is very difficult. Additionally, the external input amplifier must primarily drive the ADS7810 within the sampling period of about 200ns. This will require a high speed, precise amplifier that can swing to greater than ±10V.

For signals clocked below 200kHz, the OPA671 op amp should be suitable for most applications. In some cases or at higher input frequencies, a composite configuration of the OPA671 and BUF634 (in its wideband mode) may be the best choice. See the BUF634 datasheet for more information.

The resistive front end of the ADS7810 also provides guaranteed ±25V overvoltage protection. In most cases, this eliminates the need for external input protection circuitry.

middle latch

The ADS7810 has tri-stated outputs for the parallel port, but if the bus is active during conversion, an intermediate latch should be used. The tri-state output can be used to isolate the A/D from other peripherals on the same bus if the bus is not active during the conversion process.

The intermediate latch is good for any monolithic A/D converter. The ADS7810 has an internal LSB size of 610µV. Transients from fast switching signals on the parallel port, even when the A/D is tri-stated, can couple through the substrate to the analog circuitry, resulting in degraded converter performance.