Description 9 10 11 12

The TLV990-13 is a complete CCD signal processor/digitizer designed for digital camera and PC camera applications. TLV990-13 performs all analog processing

The functions needed to maximize dynamic range, correct for various errors associated with the CCD sensor, and then digitize the results using an on-chip high-speed analog-to-digital converter (ADC).

Key components of the TLV990-13 include: input clamp circuit for CCD signal, correlated double sampler (CDS), programmable gain amplifier (PGA) with 0-36dB gain range, automatic or programmable optical black Two internal digital-to-analog converters (DACs) for flat and offset calibration, 10-bit 13-MSPS pipelined ADC, one parallel data port for simple microprocessor interface, one serial port for configuring internal control registers, two an additional DAC and internal voltage reference for external system control.

Designed in an advanced CMOS process, the TLV990-13 is powered by a 3-V power supply and has a normal power consumption of 150 MW at 13 ms/sec and 2 MW in power-down mode.

The single 3-V operation, extremely low power consumption, and fully integrated analog processing circuitry of the TLV990-13 make it an ideal CCD signal processing solution for digital still camera and PC camera applications.

The device is housed in a 48-pin TQFP package and has an operating temperature range of -20°C to 75°C.

Functional block diagram

CDS and PGA

The output of the CCD sensor is first fed to the correlated double sampler (CDS) through the CCDIN pin. The CCD signal is sampled and held during the reset reference interval and the video signal interval. By subtracting the two resulting voltage levels, CDS removes low-frequency noise from the output of the CCD sensor and obtains the voltage difference between the CCD reference level and the video level for each pixel. Two sample/hold control pulses (SR and SV) are required to perform the CDS function.

The CCD output is capacitively coupled to the TLV990-13. Via the CLCCD input, the AC-coupling capacitors are clamped within dummy pixel intervals to establish proper DC bias. The bias voltage at the input of the TLV990-13 is set to 1.2V. Typically, CLCCDs are applied at the line rate of the sensor. A capacitor, whose value should be greater than 10 times the input AC-coupling capacitor, should be connected between the CLREF pin and AGND.

When operating the TLV990-13 at maximum speed, the CCD internal source resistance should be less than 50Ω. Otherwise a CCD output buffer is required.

After the CDS function is complete, the signal is sent to the PGA. The PGA gain can be adjusted from 0 to 36 dB by programming the internal gain register through the serial port. The PGA is digitally controlled with 10-bit resolution on a linear dB scale, resulting in 0.045db gain steps. The gain can be expressed as,

Gain = PGA code × 0.045dB

The range of PGA codes is 0 to 767.

analog to digital converter

The ADC uses a pipelined structure to achieve high throughput and low power consumption. Fully differential implementation and digital error correction ensure 10-bit resolution.

The delay of ADC data output is 6 ADCCLK cycles, as shown in Figure 1. Pulling the OE pin (pin 24) high makes the ADC output high impedance.

User DAC

The TLV990-13 includes two user DACs that can be used for external analog settings. The output voltage of each DAC can be set independently from 0v to the supply voltage with 8-bit resolution. When the user DAC is not used in the camera system, it can be put into standby mode by programming control bits in the control register.

Internal timing

As mentioned earlier, the SR and SV signals are required to operate the CDS. The user needs to synchronize the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to the external circuit by the ADCCLK signal, which is also used to internally control the ADC and PGA operations. As shown in Figure 1, the positive half cycle of the ADCCLK signal must always fall between two adjacent SV pulses. The user can then fine-tune the ADCCLK timing relative to the CDS timing for optimum performance.

CLCCD signal is used to activate input clamping, OBCLP signal is used to activate automatic optical black and offset correction

working principle

Input blanking function

At the input of the TLV990-13, during a period of operation, there may be large input transients, which will saturate the input circuit and cause a long recovery time. To prevent circuit saturation, the TLV990-13 includes an input blanking function that blocks input signals by disabling CDS operation when the BLKG input is pulled low. After BLKG is pulled low, the TLV990-13 digital outputs will be set by the blanking data register.

Note:

If the BLKG pulse precedes the OBCLP pulse, there must be at least 4 pixels between the rising edge of the BLKG pulse and the falling edge of the OBCLP pulse. If the BLKG pulse follows OBCLP, the minimum number of pixels between the falling edge of OBCLP and the falling edge of the BLKG pulse should be equal to the number of optical black pixels per row + 4.

Three-wire serial interface

A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided, allowing writing to the TLV990-13's internal registers. The serial clock SCLK can run at a maximum frequency of 40 MHz. Serial data SDIN is 16 bits long. Two leading empty bits are followed by four address bits, the internal register will be updated, and then ten bits of data will be written to the register. The CS pin must be held low to enable the serial port. After CS falls, the data transfer is initiated by the incoming SCLK.

SCLK polarity can be selected by pulling the SCKP pin high or low.

Device reset

When pin reset (pin 29) is pulled low, all internal registers are set to their default values. The device also resets itself the first time it is powered on. Additionally, the TLV990-13 has a software reset function that resets the device when control bits are written to the control registers.

See the Register Definitions section for register default values.

voltage reference

A nominal 1.5 V internal precision voltage reference is provided. This reference voltage is used to generate the ADC reference voltage of 1V and the reference voltage of 2V. It is also used to set the clamping voltage. All internally generated voltages are fixed values and cannot be adjusted.

Off mode (standby)

The TLV990-13 implements both hardware and software power down modes. Pulling pin STBY (pin 30) low puts the device into a low power standby mode. The total supply current drops to about 0.6mA. Power-down mode can also be activated by setting the power-down control bit in the control register. In power-down mode, the user can still program all internal registers.

power supply

The TLV990-13 has several power pins. Each major internal analog block has a dedicated AV power pin. All internal digital circuits are powered by DV. AVDD and DV are both 3-V nominal. due diligence due diligence due diligence

The DIV and DIGND pins power the output digital drivers (D9–D0). DIV is independent of DV and works from 1.8v to 4.4v. This allows the output to interface with digital ASICs that require different supply voltages. due diligence due diligence due diligence

working principle

Grounding and Decoupling

All ground pins of the TLV990-13 are not connected internally and must be connected externally to PCB ground.

General conventions should apply to PCB design to limit high frequency transients and noise fed back to power and reference lines. This requires that the supply and reference pins be adequately bypassed. In the case of power supply decoupling, 0.1µF ceramic chip capacitors are sufficient to maintain low impedance over a wide frequency range. Recommended external decoupling for the three voltage reference pins is shown in Figure 4. All decoupling capacitors should be placed as close as possible to the supply pins, since their effectiveness depends heavily on the proximity to a single supply pin.

To reduce high frequency and noise coupling, it is strongly recommended to short the digital and analog grounds immediately outside the package. This can be achieved by running a low impedance line under the package between DGND and AGND.

Automatic optical shading correction

In the TLV990-13, light black and system channel offset correction is performed by an automatic digital feedback loop. Two DACs are used to compensate for channel shift and optical black shift. The coarse correction DAC (CDAC) is located before the PGA gain stage, and the fine correction DAC (FDAC) is located after the gain stage. A digital calibration system is able to correct optical blackness and channel offset to one ADC LSB accuracy.

Whenever the OBCLP input is pulled low, the TLV990-13 automatically starts auto-calibration. The OBCLP pulse width should be sufficient to cover one positive half cycle of ADCCLK, as shown in Figure 1.

For each row, the optical black pixels plus the channel offset are sampled and converted to digital data by the ADC. Digital circuitry averages the data during optical black pixels. The averaged result is digitally compared to the desired output code stored in the Vb register (40H by default), then the control logic adjusts the FDAC so that the ADC output equals Vb. If the offset is outside the range of FDAC (±255 ADC LSB), the error is corrected by CDAC and FDAC. The CDAC increments or decrements one CDAC LSB, depending on whether the offset is negative or positive, until the output is within the range of the FDAC. The remaining residue was corrected by FDAC.

The relationship between FDAC, CDAC, and ADC in terms of ADC lsb count is as follows:

1 FDAC LSB = 1 ADC LSB,

1 CDAC LSB = PGA linear gain × n ADC LSB.

where n is:

4:0=

2 For 96=

1:128=

For example, if PGA gain=2 (6 dB), then 1 CDAC LSB=2 x 4 ADC LSB=8 ADC LSB.

After the auto-calibration is completed, during the CCD signal interval, the digital output of the ADC can be expressed by the following formula:

ADC output[9–D0]=CCD Uinput×PGA gain+Vb,

where Vb is the desired black level selected by the user. The total offset (including optical black offset) is calibrated to be equal to Vb by adjusting the offset correction dac during auto-calibration.

working principle

Automatic Optical Black and Offset Correction (continued)

During averaging, a weighted rolling average of optical black pixels is performed. The weighting factor can be programmed in Control Register 2. The weighting factor determines the convergence speed of the digital filtering implemented in the CCD signal processor. The closer the weight factor is to 1, the faster the convergence. When the weighting factor is reduced to the minimum value of 1/128, the convergence speed of digital filtering decreases.

The algorithm also takes into account hot and cold pixels. Hot black pixels are defective pixels that generate excessive charge, while cool pixels are pixels that generate little or no charge. A digital comparator compares the digitized optical black pixels to user-selected limits for hot and cold pixels. If the optical black pixel value is out of range, the hot or cold pixel is replaced with the value of the previous pixel.

Due to different exposure times, there may be a sudden optical black level shift at the beginning of each frame. Therefore, fast optical black level correction is required. The user can set an internal control bit (SOF bit in Control Register 2) to automatically disable the hot/cold pixel limit and set the digital filter weighting factor to 1 (equivalent to one line averaging). In this way, optical black correction can be performed very quickly for the first line of each frame.

The number of black pixels in each row is programmable. The average number of black pixels per row is 2, where N can be any integer between 0 and 6.

The auto-calibration feature can be bypassed if the user wishes to program the offset DAC registers directly. Switching from auto-calibration mode to direct programming mode requires two register writes. First, the offset DAC control bits in the control register must be changed; then, the offset DAC register is loaded with the desired offset value for the register for proper error correction. If the total offset (including optical black level) is less than ±255 ADC LSB, only the FDAC needs to be programmed. When switching from direct programming mode to auto-calibration mode, the previous DAC register value (instead of the default DAC register value) is used as the starting offset.