The ISL6224 provides power control and protection for individual devices, chipsets and memory banks in high-performance laptops and PDAs. This output voltage is adjustable from 0.9-5.5V. A hysteresis or PWM controller regulates the output battery voltage from 4V to 24V . Synchronous rectification with optical hysteresis helps run loads over a wide range of input voltages and loads. Efficiency is further improved using the rDS(ON) of the MOSFET as the current sensing element. Feed-forward ramp modulation, average current mode control and internal feedback compensation provide fast and stringent handling of transients by the chipset when supply is advanced. Two-stage conversion using the system 5V voltage at a higher frequency (600kHz) to minimize the size of the output filter. The ISL6224 monitors the output voltage. Good power) Signals when the soft start is complete and the output is within ±10% of the set value. Built-in overvoltage protection prevents the output voltage from exceeding 120 % of the set value. Undervoltage protection locks the chip to 70% of its set value after the soft-start sequence is complete when the output falls below the full value. The overcurrent circuit of the PWM controller monitors the output current through the lower MOSFET by sensing the voltage drop. Optional external current sensors can use resistors if higher accuracy is required.

feature

Adjustable output voltage: 0.9-5.5V

Efficient over a wide load range - light load hysteretic mode is more efficient

Non-destructive current detection scheme - rDS(ON) using MOSFET - optional current detection method with higher accuracy

Powered Operating Modes - Wide VIN Range: 4V-24V-Single 5V System Rail

Input Undervoltage Lockout (UVLO) on VCC Pin

Excellent dynamic response - voltage feedforward and current combined mode control

good power indicator

300 /600kHz switching frequency

Thermal shutdown

Lead-free plus annealed (RoHS compliant) available

application

mobile PC

graphics card

Handheld Portable Instrument

Related Literature

Application Instructions AN9983

Absolute Maximum Ratings Thermal Information

Bias, VCC. -0.3V to +7V

Input voltage, vehicle identification number. +27.0V

Phase and Isen pins. Ground -0.3V to +29.0V

Dust boots and wear pins. +32.0V

About the start of the phase. +7.0V

all other pins. Ground -0.3V to 15V

Electrostatic discharge classification. level 2

Recommended Operating Conditions

Bias, VCC. +5.0V±5%

Input voltage, vehicle identification number. 4.0V to +24.0V

Ambient temperature range. -10°C to 85°C

junction temperature range. -10°C to 125°C

Thermal Resistance (Typical, Note 1) θJA (°C/Watt)

SSOP package. 112

Maximum Junction Temperature (Plastic Packaging). 150 degrees Celsius

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius (SSOP - lead only)

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation of the device under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

3. In free air, measure JA with components mounted on a high-efficiency thermal conductivity test board.

Electrical Specifications Operating Conditions: VCC=5V, TA=10°C to 85°C, unless otherwise noted.

Electrical Specifications Operating Conditions: VCC=5V, TA=10°C to 85°C, unless otherwise noted. (continued)

Function pin description

The VIN (pin 1) provides the battery voltage to the oscillator for feed-forward input voltage variation suppression. Also, this pin programs the internal clock frequency and gain ramp generator. When connected to a battery, the voltage is from 4V to 24V, the clock frequency is set to 300kHz, and the ramp gain is set accordingly to accommodate a wide input voltage range. For two-step conversion of the system 5V rail, the VIN pin is connected to ground through a 150k resistor. This arrangement changes the gain of the ramp generator to accommodate the lower input voltage without changing the clock frequency. When the VIN pin is grounded, the clock frequency is set to 600kHz. The gain of the ramp generator is also changed accordingly. This circuit arrangement enables the designer to select smaller output filter components.

PGOOD (Pin 2)

PGOOD is an open collector output that indicates the state of the output voltage. When the system output voltages are within ±10% of their respective nominal values.

EN (pin 3)

This pin provides the enable/disable function of the chip. This IC is enabled when this pin is pulled over 2V or left open. Note: A pull-down resistor of 100k or less is required to disable the controller.

catenary (pin 4)

A resistor from this pin to GND sets the overcurrent protection threshold.

VOUT (pin 5)

This pin is used to feed back the output voltage to the operating mode to correctly position the output voltage changes

VSEN (pin 6)

This pin is connected to the output through a resistor divider and provides a voltage feedback signal for the PWM controller. The PGOOD, UVP, and OVP circuits use this signal to report the output voltage status.

Soft (pin 7)

This pin provides a soft-start PWM controller. When the EN pin is pulled high, the voltage on the capacitor is connected due to the 5µA pull-up, and the soft-start pin rises linearly current. The output voltage follows the capacitor until it reaches a value of 0.9V. Rising the voltage on the soft-start capacitor further does not affect the output voltage.

Ground (Pin 8)

The signal of the IC is grounded.

PGND (pin 9)

This is the power ground connection for the PWM converter. This pin is connected to the lower MOSFET source terminal.

LGATE (pin 10)

This pin provides gate drive for the lower MOSFET.

VCC (pin 11)

This pin provides power to the chip.

ISEN (pin 12)

This pin is used to monitor the voltage drop of the lower MOSFET for current feedback and overcurrent protection. For accurate current sensing, this input can be connected to an optional current sense resistor with the source of the low MOSFET.

Phase (Pin 13)

Connect this pin to the phase node of the converter. This junction is the junction source of the upper MOSFET, the output filter inductor, and the drain of the lower MOSFET.

Wear (pin 14)

This pin provides gate drive for the upper MOSFET.

Sheath (pin 15)

This pin powers the upper MOSFET driver of the PWM converter. Connect this pin to the bootstrap capacitor with the bootstrap diode cathode. The anode steering diode is connected to the VCC pin.

FCCM (pin 16)

When pulled to VCC, this pin suppresses hysteretic operation under light load conditions.

General Instructions

Business Overview

The ISL6224 is a single-channel PWM controller for chipset, DRAM or other low voltage power supply requirements for modern notebook and sub-notebook ICs with single point control circuits and feedback compensated synchronous buck converters. The output voltage is set in the range 0.9-5.5V through an external resistor divider. Synchronous buck converters can be configured to switch at either 300kHz or 600kHz. when? Powered by batteries, a switching frequency of 300kHz is recommended. When operating from 5V, the switch selects a frequency of 300kHz or 600kHz. For 300kHz operation, pin 1 should be connected through a resistor (150K) to ground. For 600kHz operation, pin 1 should be ground. Table 1. Displays different configuration operating modes. Figure 1 below shows a graph of ramp speed compensation.

Improves the light-load efficiency of the synchronous converter through a hysteretic mode of operation when the inductor current becomes discontinuous. When the filter inductor resumes continuous current, the working mode is automatic recovery. The ISL6224 control IC uses an average current mode input voltage feed-forward ramp control scheme programmed for better rejection of input voltage variations. Current Sensing and Current Limit Protection The PWM converter uses the lower MOSFET on-state resistance, rDS(on), as the current sensing element. This technique does not require current sense resistors and associated power losses. A current sense resistor can be used in series with the lower MOSFET source if the current is more accurate for protection. The current proportional signal is used to provide average current mode control and overcurrent protection. The gain current sense circuit is set by a resistor connected to ISEN (pin 12) connected to the phase node of the buck converter. The value of this resistor can be estimated by the following expression:

where Iomax is the maximum inductor current. The value should be the expected maximum value to specify the elevated operating temperature. The overcurrent protection threshold is controlled by an external resistor from OCSET (pin 4) to ground. The expression for the value of this resistor:

where Ioc is the value of the overcurrent. The resulting current is taken out of the ISEN pin by rising for current feedback and current limit protection. This is related to the internal current limit threshold. When the sampled value of the output current is determined to be above the current limit threshold, the PWM driver is terminated and the counter is started. This limits the accumulation of inductor current and essentially switches the converter into current limiting mode. If an overcurrent is detected between 26ms and 53ms, an overcurrent shutdown is initiated. If no overcurrent is detected between 26 ms and 53 ms, the counter reset sampling continues as normal. This current limiting scheme is common in applications such as portable computers due to the wide variation in current accumulation between input and output voltages and inductors. Light Load (Hysteresis) Operation In Light Load (Hysteresis) mode, the output voltage is regulated by a hysteretic comparator to keep the output voltage ripple as shown in Figure 2. In hysteretic mode, the inductor current turns off only when the output voltage reaches the hysteretic comparator at the upper limit. Hysteretic mode by requiring it only at the output voltage. This mode works by reducing the power consumption associated with continuous switching. The upper and lower mosfets turn off during the time between inductor current pulses. This is referred to as "diode emulation mode" because the lower MOSFET performs the function of a diode. This diode emulation mode prevents the output capacitor from conducting through the upper MOSFET when the lower MOSFET does not conduct. Note: PWM-only operation can be enforced by tying a knot on pin 16, FCCM, connected to VCC.

Run Mode Control

The mode control circuit changes the mode of the converter based on the operation of the phase node voltage polarity when the lower MOSFET is turned on while the upper MOSFET is turned on. For continuous inductor current, when the lower MOSFET is conducting and the converter operates at a fixed frequency in the PWM mode shown in Figure 3. When the load current decreases to the point where the inductor current flows through the "reverse" direction of the lower MOSFET phase node becomes positive and the mode becomes hysterical. The phase comparator handles the timing voltage sensing of the phase nodes. The low level of the phase comparator output indicates the time of the MOSFET at the negative phase voltage during conduction. A high level comparator output indicates a positive voltage. When the phase node is positive (phase comparator high), at the end of the lower MOSFET conduction time, for 8 consecutive clock cycles, the pattern becomes hysteretic as shown in Figure 3. The dotted line indicates that the phase node goes positive and the phase comparator output is excited. The solid lines at 1, 2, ... 8 represent the sampling times of the phase comparators to determine the polarity (sign) of the phase nodes. The mosfet in PWM and hysteresis mode is turned off. The phase node will be based on the phase node with respect to the output inductance and parasitic capacitance and settle at the output voltage value.

The pattern change from hysteresis back to PWM can be caused by one of two events. One event is that the same mechanism turns PWM into a hysteretic transition. But instead of looking at eight consecutive occurrences of this stage node, it is looking for eight consecutive negative occurrences at the stage node. The operating mode is when these eight consecutive pulses appear. This switching technique prevents jitter in the operating mode at load levels close to the boundary. Another mechanism for changing from hysteresis to PWM is because of a sudden increase in output current. This step of loading causes the output voltage to drop instantaneously due to the voltage drop across the output capacitor ESR. If the reduction causes the output voltage to drop to the hysteretic regulation stage, the mode is changed to PWM on the next clock cycle. This ensures an increase in output current.

gate control logic

The gate control logic converts the generated PWM control into the MOSFET gate drive signal to provide the necessary amplification, level shifting and penetration protection. In addition, it has functions that help optimize the performance of the integrated circuit under various operating conditions. Because the switching time of the MOSFET can be determined from the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-source voltage of the upper and lower MOSFETs. This is between gate to source, the lower MOSFET turns on before the voltage on the upper MOSFET has dropped to less than about 1V. Similarly, the upper MOSFET does not turn until the gate-source voltage of the lower MOSFET drops below about 1V. This allows for a variety of upper and lower mosfets, without regard to simultaneous conduction, or shoot-through.

soft start operation

The soft start of the synchronous Buck converter is done by a capacitor connected from pin 7, soft to ground. The soft-start time can be obtained from the following equation:

Figure 4 shows the soft-start initiated by the enable pin with the VIN input pulled at 5.6V with the 3.3V output and the PGOOD signal pulled high. When the enable pin is held low, before t0, the output is turned off. When the EN-pin is at t0, the voltage on the capacitor is pulled high. Due to the internal 5µA current, the soft-start pin rises linearly and the power supply begins to charge the capacitor. The output voltage tracks the voltage across the capacitor until it reaches 0.9V at t1. At this point, t1, the output voltage starts to regulate. When the PGOOD pin is high at t2, the voltage rises further on the capacitor without affecting the output voltage during soft-start.

Power Good Status The ISL6224 monitors the output voltage. When the soft-start is complete, a power good signal PGOOD output is within 10% of the set value. After the soft-start sequence is complete, undervoltage protection locks the chip below 70% of the set value when any monitored output falls. Perform a "soft crowbar" function on the overvoltage at the output. If the output voltage is higher than the nominal output level, the upper MOSFET is turned off and the lower MOSFET is turned on. This "soft crowbar" will hold that state to the regulation window until the output voltage recovers, and then normal operation will continue. This "soft crowbar" and output monitor prevents the inductor current from negatively ringing the output voltage to flow in the "reverse" direction through the lower MOSFET and output capacitor. Component Selection Guidelines Output Capacitors Selecting output capacitors has unique requirements. In general, the selection of the output capacitor should meet dynamic regulation requirements, including ripple voltage and load transients. The selection of the output capacitor also depends on the output inductance, so an inductance analysis is required to select the output capacitor. One of the parameters limiting the converter's response to load transients is the time it takes for the inductor current to switch to a new level. Given a fast enough control loop design, the ISL6224 will provide a 0% or 94% duty cycle response to load transients. The response time is the initial current value of the load current level for the time interval required to switch the inductor current. During this interval inductor current and transient current levels must be provided by the output capacitor. Minimizing the response time minimizes the need for output capacitors. If the load transient rise time is slower than the inductor response time, as in a hard disk or CD drive, this reduces the requirement on the output capacitor. The maximum capacitor value required for the rising step, transient load current inductor response time is: where COUT is the desired output capacitor, LO is the output inductance, ITRAN is the transient load current step, VIN is the input voltage, VOUT is the output voltage, and DVOUT is the allowable output voltage drop during load transients. High frequency capacitors initially provide transient currents and slow down the rate of change of load seen by bulk capacitors. The bulk filter capacitor value is usually determined by ESR (equivalent series resistance) and rated voltage requirements and actual capacitance requirements. The output voltage ripple is the ripple current caused by the inductance of the output capacitor and the ESR is defined by: where it is calculated in the inductor selection section. High frequency decoupling capacitors should be placed as close as possible to the power pins of the load. become

Be careful not to add inductance to the board layout that may cancel out the effects of these low inductance components. Consult the load manufacturer for circuit specific decoupling requirements. Use only dedicated low ESR capacitor switching regulator applications, 300kHz, bulk capacitors. Small boxes are better capacitors than larger ones in most cases. Output selection stability requires capacitors to be 'ESR zero', fZ, at 1.2kHz and 30kHz. This range is set by an internal, single offset set to zero at 6kHz. The ESR zero can be one side of the internal zero and still contribute to the phase margin of the control loop. therefore:

In summary, the output capacitor must meet three criteria:

1. They must have sufficient bulk capacitance to maintain the output voltage during load transients and the inductor current turns into load value transients

2. The ESR must be low enough to meet the output voltage ripple caused by the required output inductor current, and

3. The ESR zero should be placed in a fairly wide range to provide additional phase margin. Output Inductor Selection Select the output inductance to meet the output voltage ripple requirements. The inductor value determines the converter's ripple current and ripple voltage as a function of the ripple current and the ESR of the output capacitor. The Ripple Capacitor Selection section gives the voltage expression for the ripple current approximation as follows:

where Fs is the switching frequency.

Input Capacitors The important parameters for selecting a bulk input capacitor are the voltage rating and the rms current rating. For reliable operation, choose a voltage and current rating higher than the maximum input voltage and maximum rms current required by the circuit. The capacitor voltage rating should be at least 1.5 times higher than the maximum input voltage and a conservative value guideline. AC RMS input current varies with load. depending on input power and impedance specifics (all) current is provided by the input capacitor. Use a hybrid input bypass capacitor to control the voltage ripple on the mosfet. Use ceramic capacitors for high frequency decoupling and bulk capacitors for rms current. Small ceramic capacitors can be placed close to the upper MOSFET to suppress impedance in voltage-induced parasitic circuits. For board designs that allow through-hole components, the Sanyo OS-CON® series offers low ESR and good temperature performance. For surface mount designs, solid tantalum capacitors can be used, but care must be taken with capacitor inrush current ratings. These capacitors must be able to handle inrush current when powered up. The series offered by TPSAVX is inrush current test.

MOSFET Considerations

Choosing a logic-level MOSFET for optimum efficiency takes into account the potentially wide input voltage range and output power requirements. A dual N-channel or two N-channel buck converters with mosfet outputs are used in each synchronous rectifier circuit. These mosfets should be selected based on the radio data system (on), door power requirements, and thermal management considerations. Power dissipation consists of two loss components; conduction losses and switching losses. These losses are distributed between the upper and lower mosfet according to the duty cycle (see equation below). This conduction loss is the main component of power loss in low mosfet. Only the upper MOSFET has significant switching losses as the lower device turns on and off near zero voltage.

The equation assumes a linear voltage-current transition and does not model the body diode due to deceleration of the MOSFET. The gate charge loss is caused by the ISL6224 and don't heat the mosfet. However, a huge gate charge increases switching time and tSW increases MOSFET switching losses. Ensure that both mosfets are within the maximum junction temperature range at high ambient temperature according to the package thermal resistance specification.

Layout Considerations

MOSFET switching is fast and efficient. Speed and current transitions from one device to another cause voltage spikes on interconnect impedance and parasitic circuit elements. Voltage spikes can reduce efficiency, radiate noise into circuits, and cause device overvoltage stress. Careful component layout and printed circuit design will convert the converter. For example, consider a PWM mosfet above. The upper MOSFET takes full load current before turning off. During shutdown, current stops flowing in the upper MOSFET and is picked up through the lower MOSFET. Any inductive current path in the switch creates a voltage spike interval during switching. Careful component selection, compact layout of critical components and short-circuit, wide circuit traces minimize the magnitude of voltage spikes. See Application Note AN9983 for evaluation board component placement and printed circuit board layout details.

There are two sets of key components in DC/DC

Converter using ISL6224 controller. Switching power components are the most critical because they switch large amounts of energy and, as a result, they tend to generate an equally large amount of noise. Critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. Power Component Layout Considerations Power components and controller ICs should come first. Place input capacitors, especially high-frequency ceramic decoupling capacitors, close to the power supply Mossfett. Locate the output inductor and output capacitor between the mosfet and the load. Position the PWM controller close to the mosfet. Make sure that the mosfet from the input capacitor to the output inductor and output capacitor is as short as possible, the maximum track width allowed. A multilayer printed circuit board is recommended. Dedication provides a solid layer for the ground plane and ground connections for all critical layer components with vias to that layer. Put another solid layer as the energy layer and break this plane to smaller islands of common voltage level. This power plane should support input power and output power nodes. Use copper-filled polygonal phase nodes on top of the bottom circuit layer, but don't unnecessarily oversize these special islands. Circuits in and around these islands will tend to couple switching noise since the phase nodes are exposed to very high dV/dt voltages. Use the remaining printed circuit layers for small signal routing. The routing trace power supply from the control IC to the gate of the MOSFET should be sized to handle a peak current of 2A. Widget Signal Layout Considerations The VIN pin 1 input capacitor should be bypassed with a 1.0µF capacitor. The VIN bypass capacitor and the soft-start capacitor should be close to the connecting pins on the control chip. For recommended component placement and interconnection. Figures 5, 6 and 7 show the three modes of application circuit operation. Mode 1 is from battery voltage and operates at 300kHz switching frequency. Mode 2 is running off 5V, operating at 300kHz switching frequency. Mode 3 is turning off 5V and running at 600kHz switching frequency.

ISL6224 DC-DC Converter Application Circuit Figure 5 shows the application circuit of the DC/DC converter For notebook computers, the power supply provides +4V–24VDC battery voltage or the system +5V bus. For circuit details, including bill of materials and board descriptions, see application note AN9983.