The Intersil ISL84051 , ISL84052 and ISL84053 devices are precision bidirectional analog switch channel multiplexers/demultiplexers (ISL84051) configured as 8, dual differential 4-channel multiplexers/demultiplexers (ISL84052) and three A single-pole, double-throw (SPDT) switch (ISL84053) is designed to supply power from a single +2V to + 12V operation or from ±2V to ±6V. All devices have an inhibit pin that opens all signal paths simultaneously. On-resistance is 60Ω (with ±5V supply) and 125Ω (with single supply +5V. Each switch can handle rail-to-rail analog signals. 5nA at +25oC or +85oC with ±5V supply. All digital inputs have 0.8V to 2.4V logic threshold ensures TTL/CMOS logic compatibility with a single +3.3V supply and +5V supply or dual ±5V supplies. The ISL84051 is an 8-to-1 multiplexer device. Island 84052 Dual 4 1-to-1 multiplexer device. The ISL84053 is a triple SPDT ideal for 2-to-1 multiplexer applications.

Related Literature

Technical Brief TB363 "Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"

Application Note AN557 "Recommended Test Procedures for Analog Switches"

feature

MAX4051 /A, MAX4052/A, and up to 4053/A

Compatible with the MAX4581, MAX4582, MAX4583, and industry-standard 74HC4051 , 74HC4052, and 74HC4053 models

Maximum on-resistance (RON), VS=±5V. 100 euros

Maximum on-resistance (RON), VS=+3V. 525 ohms

RON matching between channels. <6€

Low charge injection. 10 pieces (max)

Single power supply operation. +2V to +12V

Dual power supply operation. ±2V to ±6

Fast switching action (VS=+5V) - t. 90 nanoseconds - time of flight. Guaranteed maximum off-leakage at VS=V for 60 ns. 5mA

Guaranteed break-before-make

TTL, CMOS compatible

Lead free available

application

portable device

Communication systems - radios - telecommunications infrastructure - ADSL, VDSL modems

Test Equipment - Medical Ultrasound - Magnetic Resonance Imaging - CT and PET Scanners (MRI) - Electrocardiograph

Audio and video signal routing

Various circuits - +3V/+5V digital to analog converters and analog to digital converters - sample and hold circuits - op amp gain switching networks - high frequency analog switches - high speed multiplexing - integrator reset circuits

Absolute Maximum Ratings Thermal Information

V+ to V-. -0.3 to 15 volts

V+ is grounded. -0.3 to 15 volts

V-ground. -15 to 0.3V

Input voltage

INH, NO, NC, ADD (Note 2). ((V-)-0.3) to ((V+)+0.3V)

The output voltage

COM (Note 2). ((V-)-0.3) to ((V+)+0.3V)

Continuous current (any terminal). mA

Peak current NO, NC or COM (pulse 1 ms, 10% duty cycle, max). ±100mA

Electrostatic discharge rating

HBM (per MIL-STD-883, Method 3015.7). >2kV

Thermal Resistance (Typical, Note 3) θJA (oC/W)

16 Ld SOIC package. 115

16 Ld SSOP packs. 160

Maximum Junction Temperature (Plastic Packaging). 150 degrees Celsius

Maximum storage temperature range. -65 degrees Celsius to 150 degrees Celsius

Maximum lead temperature (10s for soldering). 300 degrees Celsius

(lead head only)

operating conditions

temperature range

ISL8405IX. -40 degrees Celsius to 85 degrees Celsius

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

2. Signals on NC, NO, COM, ADD or INH that exceed V+ or V- are clamped by internal diodes. Limit forward diode current to the maximum current rating.

3. θJA is measured in free air with components mounted on an inefficient thermal conductivity test board.

Electrical Specifications: 5V Power Test Condition: V Power = ? 4.5V to ? 5.5V, GND=0V, VINH=2.4V, VINL=0.8V (Note 4), unless otherwise specified

Electrical Specifications: 5V Power Test Condition: V Power = ? 4.5V to ? 5.5V, GND=0V, VINH=2.4V, VINL=0.8V (Note 4) unless otherwise specified (continued)

notes:

4. VIN = Input voltage to perform correct function.

5. The algebraic convention is used in this data sheet, where the most negative value is the minimum value and the most positive value is the maximum value.

6. RON=RON (maximum value) - RON (minimum value).

7. Flatness refers to the difference between the maximum value and the minimum value of the on-resistance within the specified analog signal range.

8. Leakage parameters are 100% tested at high temperature and pass relevant guarantees at 25°C.

9. Between any two switches

Electrical Specifications: 5V Power Supply Test Conditions: V+=+4.5V to +5.5V, V-=GND=0V, VINH=2.4V, VINL=0.8V (Note 4), unless otherwise specified

Electrical Specifications: 3.3V Power Supply Test Conditions: V+=+3.0V to +3.6V, V-=GND=0V, VINH=2.4V, VINL=0.8V (Note 4), unless otherwise specified

Detailed description

The ISL84051, ISL84052, ISL84053 analog switches provide from bipolar ±2V to ±6V or have low on-resistance (60Ω) and high-speed operation (tON=50ns, tOFF=40ns). The device is especially suitable for portable battery powered devices due to low operating supply voltage (2V), low power consumption (3 microwatts), and low leakage current (5nA max). High frequency applications also benefit from bandwidth, as well as very high isolation and crosstalk rejection. Power Supply Sequencing and Overvoltage Protection As with any CMOS device, proper power supply sequencing protects the device from excessive input current that can permanently damage the integrated circuit. All I/O pins contain ESD protection diodes from the pins to V+ and to V (see Figure 8). To prevent these diodes from being forward biased, V+ and V must be applied before any input signal and the V voltage must be kept between V+ and V-. If these conditions cannot be guaranteed, one of the following two methods of protection should be used. Logic inputs can be easily protected by adding 1kΩ resistors in series with the inputs (see Figure 8). The resistors limit the input current below the threshold resulting in permanent damage and sub-microampere input currents produce an insignificant voltage drop under normal operation. This method does not work for signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low Ron switch, so two small signal diodes can be placed in series with the power pins to provide overvoltage protection on all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. Low leakage current performance is not affected by this method, but switch resistance may increase, especially at low supply voltages.

Power Considerations

The ISL8405X structure is typical of most CMOS analog switches because they have three power pins: V+, V-, and ground. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there is no connection between the analog signal path and GND. Unlike the switch when the maximum power supply voltage is 13V, the ISL8405X 15V maximum power supply voltage is 10% tolerance of the 12V power supply (±6V or 12V single power supply), and there is room for overshoot and noise peaks. This series of switches performs quite well when operating with bipolar or single voltage supplies. The minimum recommended supply voltage is 2V or ±2V. It is important to note that at lower supply voltages, the input signal range, switching time, and on-resistance decrease. See the Electrical Specifications table and typical performance detail curves. V+ and GND power the internal logic (thus setting the digital switch points) and level shifters. Level translators convert the V+ and V- signals to drive the analog switch gate terminals. Logic Stage Thresholds V+ and GND power the internal logic stage, so V- has no effect on the logic thresholds. This switch series is TTL compatible over the V+ supply range of 2.7V (0.8V and 2.4V) to 10V. At 12 volts, the VIH level is about 3.5 volts. Still below the CMOS guaranteed high output minimum level of 4V, but with reduced noise margin. For best results with a 12V supply, use a logic family with a VOH greater than 4V. The digital input stage is where the digital input voltage is not on one of the supply rails. Driving V+ time from GND to fast transition minimizes power dissipation.

High frequency performance

In a 50Ω system, the signal response is fairly smooth, even exceeding 100MHz (see Figure 17). Figure 17 also illustrates that the frequency response is very consistent across analog signal levels of change. The off switch acts like a capacitor, attenuating lesser frequencies through higher, causing the signal to be fed from the switch's input to the output. Off isolation is the resistance to that feedthrough, while crosstalk represents the amount of feed from one switch to another. Figure 18 details the rejection of the high isolation and crosstalk provided by this family. At 10MHz, the disconnect isolation is about 55dB in a 50Ω system, decreasing by about 20dB with increasing frequency. Higher load impedance reduces isolation and crosstalk suppression of the off and load impedance of the divider action.

Spill Precautions

Reverse ESD protection diodes are internally connected between each analog signal pin and V+ and V-. A if any analog signal exceeds V+ or V-. Almost all analog leakage current comes from the ESD diode to V+ or V-. Although the pins on a given signal are the same and thus fairly balanced, they have different reverse biases. Everyone has biased V+ or V- and analog signals. This means that their leakage varies with the signal. The difference between the two diodes The leakage at the V+ and V- pins constitutes the analog signal path leakage current. All analog leakage currents are between each pin and one power terminal, not the other switch terminals. This is why a given switch can show the same or opposite leakage current polarity. There is no connection path and ground between analog signals.

Typical performance curve TA=25 oC unless otherwise specified

Typical performance curve TA=25oC unless otherwise specified (continued)