feature

Full 16-bit performance; 5V single supply operation; low power; short settling time; capable of driving 60kv unbuffered voltage output; direct loading; Soy Protein Isolate™/QSI™/Microfilament™-compatible interface standards; power-on reset Clears DAC output to 0 V (unipolar mode); direct optocoupler interface Schmitt trigger input.

application

Digital gain and offset adjustment; automatic test equipment; data acquisition systems; industrial process control.

General Instructions

The AD5541 and AD5542 are single 16-bit serial input, voltage output DACs that operate from a single 5 V ±10% supply.

The AD5541 and AD5542 feature a versatile 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.

These DACs provide 16-bit performance without any tuning. The DAC output is unbuffered, which reduces power dissipation and offset errors caused by output buffers.

The AD5542 can operate in bipolar mode, producing a ±VREF output swing. The AD5542 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity.

The AD5541 and AD5542 are available in SO packages.

Product Highlights

1. Single power supply operation.

The AD5541 and AD5542 are fully specified and guaranteed to be 5 V ±10% from a single supply.

2. Low power consumption.

These parts typically consume 1.5 megawatts from a 5 volt supply.

3. 3-wire serial interface.

4. The unbuffered output can drive a 60 kΩ load.

This reduces power consumption because there are no internal buffers to drive.

5. Power-on reset circuit.

the term

relative accuracy

For DACs, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation (lsb) of a straight line passing through the endpoints of the DAC transfer function. A typical INL and code diagram is shown in Figure 2.

Differential nonlinearity

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. Monotonicity is assured by differential nonlinearity specified to a maximum of ±1 LSB. Figure 3 shows a typical DNL and code diagram.

gain error

Gain error is the difference between the actual and ideal analog output range, expressed as a percentage of the full-scale range. This is the slope deviation of the DAC transfer characteristic from ideal.

Gain Error Temperature Coefficient

This is a measure of gain error as a function of temperature. Expressed in ppm/°C.

Zero code error

Zero code error is a measure of the output error when zero code is loaded into the DAC register.

Zero code temperature coefficient

This is a way to measure the zero code error as a function of temperature. The unit is mV/°C.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault region in nV-s and is measured when the digital input code is changed by 1lsb on a major carry transition. Figure 15 shows the fault pulse diagram.

digital feedthrough

Digital feedthrough is a measurement of the pulses injected into the DAC's analog output from the DAC's digital input, but when the DAC output is not being updated. CS remains high when the CLK and DIN signals toggle. It is specified in nV-s and is measured by a full-scale code change on the data bus, i.e. from 0 to 1 and vice versa. A typical diagram of digital feedthrough is shown in Figure 14.

power supply rejection ratio

This specification explains how the output of a DAC is affected by changes in the supply voltage. The power supply rejection rate is the output change per %VDD of the DAC full-scale output. VDD variation is ±10%.

reference feedthrough

This is from the VREF input to the DAC output when the DAC is loaded with all 0s. 100 kHz, 1 V pp applied to VREF. The reference feedthrough is expressed in mV pp.

Typical Performance Characteristics - AD5541/AD5542

General Instructions

The AD5541/AD5542 are single 16-bit serial input voltage output DACs. They operate from a single supply of 2.7V to 5V and typically consume 300mA at 5V. Data is written to these devices in 16-bit words via a 3-wire or 4-wire serial interface. To ensure a known power-on state, these parts are designed with a power-on reset function. In unipolar mode, the output is reset to 0 V, while in bipolar mode, the AD5542 output is set to –VREF. Kelvin sense connections for reference and analog ground are included on the AD5542.

Digital-to-analog conversion part

The DAC architecture consists of two matched DAC sections. Figure 18 shows a simplified circuit diagram. The DAC architecture of the AD5541/AD5542 is split. The four msbs of the 16-bit data word are decoded to drive the 15 switches, E1 to E15. Each switch connects one of 15 matched resistors to AGND or VREF. The remaining 12 bits driven by the data word switch S0 to S11 of the 12-bit voltage mode R-2R ladder network.

In this type of DAC configuration, the output impedance is code independent, while the input impedance seen by the reference is closely related to the code. The output voltage depends on the reference voltage as shown in the following equation.

where D is the decimal data word loaded into the DAC register and N is the resolution of the DAC. For a reference voltage of 2.5 V, the equation simplifies to the following.

Provide VOUT of 1.25 V (mid-scale load) and 2.5 V (full-scale load) to the DAC. The LSB size is VREF/65536.

serial interface

The AD5541 and AD5542 are controlled by a versatile 3-wire serial interface that operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram is shown in Figure 1. The input data is constituted by the chip selection input box CS. After the high-to-low transition on CS, the data is shifted synchronously and latched into the input register on the rising edge of the serial clock SCLK. Data is loaded first MSB in a 16-bit word. After loading the 16 data bits into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the AD5542 which has an LDAC function that allows the Asynchronously update the DAC latch. LDAC should be held high when data is written to the shift register. Alternatively, LDAC can be tied permanently low to update the DAC synchronously. When LDAC is held permanently low, the rising edge of CS loads data into the DAC.

Unipolar output operation

These DACs are capable of driving unbuffered loads of 60kΩ.

Unbuffered operation results in low supply current (typically 300µA) and low offset error. The AD5541 provides a unipolar output swing from 0V to VREF. The AD5542 can be configured to output unipolar and bipolar voltages simultaneously. Figure 19 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table I.

Assuming a perfect reference, the worst-case output voltage can be calculated from the equation below.

Unipolar Mode Worst Case Output

Where: VOUT–UNI=unipolar mode worst case output;

D = code loaded into DAC;

VREF = reference voltage applied to the part;

VGE = gain error (unit: volts);

VZSE = zero scale error (unit: volts);

INL=Integral Nonlinearity (unit: Volts).

Bipolar output operation

With an external op amp, the AD5542 can be configured to provide a bipolar voltage output. A typical circuit for this operation is shown in Figure 20. Matched bipolar bias resistors RFB and RINV are connected to an external op amp to achieve this bipolar output swing, typically RFB=RINV=28 kΩ. Table II shows the transfer function for this output mode of operation. A set of Kelvin connections to the analog ground input are also provided on the AD5542.

Assuming a perfect reference, the worst-case bipolar output voltage can be calculated from the following equation.

Bipolar mode worst case output

In the formula: VOS = external op amp input bias voltage;

RD=RFB and RIN resistance matching error;

A = op amp open loop gain.

Output amplifier selection

For bipolar mode, a precision amplifier should be used, powered by dual supplies. This will provide ±VREF outputs. In single-supply applications, choosing the right op amp can be more difficult because the amplifier's output swing typically does not include the negative rail, in this case, AGND. Unless the application doesn't use near-zero code, this may cause some degradation in specified performance.

The selected op amp needs to have a very low bias voltage (38µV for the DAC LSB and 2.5 V for the reference) to eliminate the need for output bias trimming. The input bias current should also be very low, as the bias current multiplied by the DAC output impedance (~6K) will increase the zero code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not hinder the settling time of the DAC. The output impedance of the DAC is constant regardless of code, but to reduce gain error, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3dB bandwidth of 1MHz or more. The amplifier adds another time constant to the system, which increases the settling time of the output. The higher 3db amplifier bandwidth results in a shorter effective settling time for the DAC and amplifier.

Force Amplifier Selection

These amplifiers will be single supply low noise amplifiers. Low output impedance at high frequencies is preferred as they need to be able to handle dynamic currents up to ±20mA.

reference and ground

Since the input impedance is code dependent, the reference pin should be driven by a low impedance source. The AD5541/AD5542 operate from a voltage reference of 2V to VDD. A reference lower than 2V will result in reduced accuracy. The full-scale output voltage of the DAC is determined by the reference voltage. Tables 1 and 2 summarize the analog output voltages or specific digital codes. For best performance, a Kelvin sense connection is provided on the AD5542.

If the application does not require separate force and sense wires, they should be tied close to the package to minimize the voltage drop between the package leads and the internal die.

power-on reset

These parts feature a power-on-reset function to ensure that the outputs are in a known state at power-up. At power-up, the DAC register contains all zeros until data is loaded from the serial register. However, the serial registers are not cleared at power up, so their contents are undefined. When initially loading data into the DAC, 16 bits or more should be loaded to prevent erroneous data on the output. If more than 16 bits are loaded, the last 16 bits are reserved; if less than 16 bits are loaded, the bits from the previous word are reserved. If the AD5541/AD5542 need to interface with data smaller than 16 bits, the data should be padded with zeros at the LSB.

Supply and Reference Bypass

For accurate high-resolution performance, it is recommended to bypass the reference and power pins with 10µF tantalum capacitors and 0.1µF ceramic capacitors in parallel.

Microprocessor interface

The microprocessor interfaces with the AD5541/AD5542 through a serial bus that uses a standard protocol compatible with DSP processors and microcontrollers. A communication channel requires a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5541/AD5542 require a 16-bit data word whose data is valid on the rising edge of SCLK. The DAC update can be done automatically when all data has been clocked, or it can be done under the control of the LDAC (AD5542 only).

AD5541/AD5542–ADSP-2101/ADSP-2103 Interface Figure 21 shows the serial interface between the AD5541/AD5542 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set to operate in motion transmission alternate frame mode. The ADSP-2101/ADSP-2103 is programmed through motion control registers and should be configured as follows:

Internal clock operation, active low frame, 16-bit word length. After enabling motion, a transfer is initiated by writing a word to the Tx register. On each rising edge of the serial clock when data is clocked, an inverter is required between the DSP and the DAC because the AD5541/AD5542 clock the data in on the falling edge of SCLK.

AD5541/AD5542 to 68HC11 interface

Figure 22 shows the serial interface between the AD5541/AD5542 and the 68HC11 microcontroller. The SCK of the 68HC11 drives the SCLK of the DAC, while the MOSI output drives the serial data line SDIN. The CS signal is driven by one of the port lines. The 68HC11 is configured in master mode; MSTR=1, CPOL=0, CPHA=0. The data displayed on the MOSI output is valid on the rising edge of SCK.

AD5541/AD5542 to Microwire Interface

Figure 23 shows the interface between the AD5541/AD5542 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5541/AD5542 on the rising edge of the serial clock. Since the DAC clocks data to the input shift register on the rising edge, no glue logic is required.

AD5541/AD5542 to 80C51/80L51 interface

The serial interface between the AD5541/AD5542 and the 80C51/80L51 microcontroller is shown in Figure 24. The microcontroller's TxD drives the AD5541/AD5542's SCLK, while the RxD drives the DAC's serial data line. P3.3 is a bit programmable pin on the serial port used to drive CS.

The 80C51/80L51 provide the LSB first, while the AD5541/AD5542 require the MSB of the 16-bit word first. Care should be taken to ensure that the transfer routine takes this into account.

When data is transferred to the DAC, P3.3 is taken low. The data on RxD is valid on the falling edge of TxD, so the clock must be inverted because the DAC clocks the data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmits its data in 8-bit bytes with only 8 falling clock edges during the transmission cycle. Since the DAC requires a 16-bit word, P3.3 must be held low after the first 8 bits are transferred and high after the second. The LDAC on the AD5542 can also be controlled by the 80C51/80L51 serial port output using another bit programmable pin P3.4.

application

Optocoupler interface

The digital inputs of the AD5541/AD5542 are Schmitt-triggered, so they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where optocouplers may be required to isolate the DAC from the controller. Figure 25 shows such an interface.

Decode Multiple AD5541/AD5542s

The CS pin of the AD5541/AD5542 can be used to select one of several DACs. All devices receive the same serial clock and serial data, but only one device receives the CS signal at any one time. The DAC address will be determined by the decoder. The digital input lines will have some digital feedthrough. Using a burst clock will minimize the effect of digital feedthrough on the analog signal path. Figure 26 shows a typical circuit.

Dimensions

Dimensions are in inches and (mm).

1. The temperature ranges are as follows: A, B, C versions: –40°C to +85°C. J, L versions: 0°C to 70°C.

2. The reference input resistance depends on the code, and the minimum value is 8555 hex. 3 Guaranteed by design, no production test. Specifications are subject to change without notice.