feature

2 matched ADCs with input signal conditioning; selectable bipolar input voltage ranges (0.5V, 1.0V, 2.0V); fully MIL-STD-883B compliant; 80dB spurious free dynamic range; trim channel matching.

application

Radar processing; communication receivers; FLIR processing; secure communications; any I/Q signal processing application.

General Instructions

The AD10242 is a complete dual signal chain solution including on-board amplifier, reference signal, ADC, and output buffer, providing unmatched overall system performance. Each channel is laser trimmed for gain and offset matching and provides better than 80dB channel-to-channel crosstalk performance. The AD10242 uses two of the AD9632, OP279 , and AD9042 in a custom MCM to gain space, performance, and cost advantages over previously available solutions.

The AD10242 operates at ±5.0V for analog signal conditioning and uses a separate 5.0V supply for analog-to-digital conversion. Each channel is completely independent, allowing operation with independent encoded or analog inputs. The AD10242 also provides the user with a choice of analog input signal ranges to minimize the additional signal conditioning required for multiple functions in a single system. At the heart of the AD10242 is the AD9042, designed for applications requiring a wide dynamic range.

The AD10242 is produced on the MIL-PRF-38534 MCM line for Analog Devices and is fully qualified. Units are packaged in custom co-fired ceramic 68-lead gull-wing assemblies and are specified to operate over a temperature range of -55°C to + 125 °C. Please contact the factory for more customization options, including an option that allows the user to directly AC-couple the ADC bypassing the front-end amplifier section. See the AD9042 data sheet for more details on ADC performance.

Product Highlights

1. The guaranteed sampling rate is 40 MSPS.

2. Specified dynamic performance over the entire Nyquist band; spurious @80 dBc for -1 dBFS input signal.

3. Low power consumption: <2W off ±5.0V power supply.

4. User-defined input amplitude.

5. Packaged in 68 lead ceramic leaded chip carrier.

Analog Bandwidth Specifications

definition

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3db.

Aperture delay

The delay between the 50% point of the rising edge of the encoded command and the instant the analog input is sampled.

Aperture uncertainty (jitter)

Sample-to-sample variation of aperture delay.

Differential nonlinearity

Deviation of any code from the ideal 1lsb step.

Code Pulse Width/Duty Cycle

Pulse width high is the minimum time that the encoded pulse remains in a logic "1" state to achieve rated performance; pulse width low is the minimum time that the encoded pulse remains low. These specifications define acceptable encoding duty cycles at a given clock rate.

Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the worst harmonic component.

Integral nonlinearity

Deviation of the transfer function from the reference line measured in fractions of 1 lsb as determined by a least squares curve fit to the "best straight line".

Minimum conversion rate

The signal-to-noise ratio of the lowest analog signal frequency is below the guaranteed limit not exceeding the code rate of 3db.

Maximum conversion rate

The encoding rate when performing the parametric test.

output propagation delay

Delay between the 50% point of the rising edge of the encoded command and the time when all output data bits are within the valid range

Overvoltage recovery time

The amount of time it takes for the converter to recover to 0.02% accuracy after reducing an analog input signal at a specified percentage of full scale to mid-scale.

power supply rejection ratio

Ratio of input offset voltage change to supply voltage change.

Signal to Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components (including harmonics but excluding DC).

Signal-to-noise ratio (signal-to-noise ratio, no harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and DC.

Spurious Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral components. Peak spurious components may or may not be harmonics. SFDR can be reported in dBc (that is, decreases as signal level decreases) or dBFS (always relative to converter full scale).

Transient response

Time required for the converter to reach 0.02% accuracy when a half-scale step function is applied to the analog input.

Two-tone intermodulation distortion suppression

Ratio of the rms value of the input tone to the rms value of the worst third-order intermodulation product; expressed in dBc.

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be IMD products. Two-tone SFDR can be reported in dBc (that is, decreases as signal level decreases) or dBFS (always relative to converter full scale).

logical level

Equivalent Circuit

AD10242 – Typical Performance Characteristics

theory of operation

See functional block diagram. The AD10242 uses three monolithic ADI components (AD9632, OP279, and AD9042) per channel, along with multiple passive resistor networks and decoupling capacitors, to fully integrate a complete 12-bit analog-to-digital converter.

The input signal first passes through a precision laser-trimmed resistor divider, allowing the user to select externally for operation with a full-scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by selecting the appropriate input terminal for the application. The result of the resistor divider is a full-scale input of approximately 0.4V applied to the non-rotating input of the internal AD9632 amplifier.

The AD9632 provides the dc-coupled level-shifting circuitry required to work with the AD9042 ADC. When configuring the amplifier in non-converting mode, the ac signal gain can be adjusted to provide a constant input to the ADC centered around the AD9042's internal reference voltage. This allows the converter to be used in multiple system applications without the need for external gain and level shifting circuits that typically require trimming. The AD9632 was selected for its excellent ac performance and input drive capability. These two specifications limit the ability of many amplifiers to drive high-performance ADCs. As new amplifiers are developed, pin-compatible improvements are planned to incorporate the latest operational amplifier technology.

The OP279 provides a buffer and inversion of the AD9042's internal reference to provide the summing node for the AD9632's input amplifier. This DC voltage is then added to the input voltage and applied to the input of the AD9042 ADC. The AD9042's reference voltage is designed to track the ADC's internal offset and drift and to ensure matching over the extended operating temperature range.

Apply AD10242

Code AD10242

The AD10242 is designed to interface with TTL and CMOS logic families. The source used to drive the encode pins must be clean and free of jitter. Sources with excessive jitter can limit the signal-to-noise ratio and overall performance.

The AD10242 encoded input is connected to the differential input stage (see Figure 4). The voltage divider biases the input to 1.6V with no input connected to the code or code input. For TTL or CMOS use, the code source should be connected to the code (pins 29 and/or 51). The encoder (pins 28 and/or 52) should be separated from ground using a low inductance or microwave chip capacitor. 0.01µF capacitors like the AVX 05085C103MA15 work well.

performance improvements

The performance of the AD10242 can be slightly improved by exploiting the internal characteristics of the amplifier and converter combination. By slightly increasing the 5v supply, users can achieve up to 5dB of SFDR improvement over the converter's entire frequency range. Exceeding 5.5 V on the analog supply is not recommended as there is no performance benefit beyond this range and care should be taken to avoid the absolute maximum ratings.

If a logic threshold other than the nominal 1.6 V is required, the following equations show how to use an external resistor Rx to raise or lower the trigger point (see Figure 4, R1 = 17 kΩ, R2 = 8 kΩ).

Lower the logic threshold.

Increase the logic threshold.

While single-ended encoding works well in many applications, differential-driven encoding will provide higher performance. Depending on the circuit layout and system noise, 1db to 3db of SNR improvement can be achieved. It is recommended to AC-couple the encoded signal into the encode and encode pins.

The simplest options are shown below. A low-jitter TTL signal is coupled with a limiting resistor (typically 100Ω) to the primary side of an RF transformer (these transformers are inexpensive and readily available; the part numbers in Figures 9 and 10 are from small circuits). The secondary side is connected to the encode and encode pins of the converter. Since both encoded inputs are self-biased, no additional components are required.

If no TTL source is available, a clean sine wave can be substituted. In the case of a sinusoidal source, the matching network is shown below. Since the impedance ratio of the specified matching transformer is 1:1, the load resistor R should be chosen to match the source impedance. In most cases, the input impedance of the AD9042 is negligible.

Another option, if a low-jitter ECL clock is available, is to AC couple the differential ECL signal to the encode input pins, as shown in Figure 11. The capacitors shown here should be chip capacitors, but no low inductance variation is required.

As a last resort, the ECL gate can be replaced by an ECL comparator. The input to the comparator can be a logic signal or a sinusoidal signal.

When AC coupling, care should be taken not to overdrive the encoder input pins. Although the input circuit is electrically protected from overvoltage or undervoltage conditions, overdriving the encoded input pins may result in improper circuit operation.

Use flexible input

The AD10242 is designed with user ease of operation in mind. Multiple input configurations are included on the board, allowing the user to select input signal levels and input impedance. While the standard inputs are ±0.5 V, ±1.0 V, and ±2.0 V, the user can select the input impedance of the AD10242 on any input using the other inputs as an alternative to ground or an external resistor. The following table summarizes the impedance options available for each input location:

When AIN2 and AIN3 are turned on, AIN1=100Ω.

When AIN3 is shorted to ground, AIN1=75Ω.

When AIN2 is shorted to ground, AIN1=50Ω.

When AIN3 is turned on, AIN2=200Ω.

When AIN3 is shorted to ground, AIN2=100Ω. When the external resistance from AIN2 to AIN3 is AIN2=300Ω, and AIN3 is shorted to ground, AIN2=75Ω.

When the external resistance from AIN2 to AIN3 is AIN2=100Ω, and AIN3 is shorted to ground, AIN2=50Ω.

AIN3=400 euros.

When the external resistance of AIN3 is 133Ω to ground, AIN3=100Ω. When the external resistance of AIN3 is 92Ω to ground, AIN3=75Ω. When the external resistance of AIN3 is 57Ω to ground, AIN3=50Ω.

Although the analog inputs of the AD10242 are designed for dc-coupled bipolar inputs, the AD10242 is capable of using unipolar inputs in a user-selectable mode by adding external resistors. This allows 1V, 2V, and 4V full-scale unipolar signals to be applied to the various inputs (AIN1, AIN2, and AIN3, respectively). Placing a 2.43 kΩ resistor (typically, offset calibration required) between UPOS and UCOM shifts the reference voltage set point to allow a unipolar positive voltage to be applied to the device input. To calibrate the offset, apply a midscale DC voltage to the converter while adjusting the unipolar resistor for midscale output conversion.

To operate with -1 V, -2 V, or -4 V full-scale unipolar signals, place a 2.67 kΩ resistor between UNEG and UCOM (typically, offset calibration is required). This again shifts the reference voltage set point to allow a unipolar negative voltage to be applied at the device input. To calibrate the offset, apply a midscale DC voltage to the converter while adjusting the unipolar resistor for midscale output conversion.

Grounding and Decoupling Analog and Digital Grounds

Proper grounding is essential in any high-speed, high-resolution system. A multilayer printed circuit board (PCB) is recommended to provide the best grounding and power scheme. Using ground and powered aircraft has distinct advantages:

1. Minimization of the loop area surrounded by the signal and its return path.

2. Impedances associated with ground and power paths are minimized.

3. The inherent distributed capacitor formed by the power supply board, the printed circuit board insulation layer and the ground plane.

These features both reduce electromagnetic interference (EMI) and improve overall performance.

It is important to design a layout to prevent noise coupling into the input signal. Digital signals should not run in parallel with the input signal traces and should be kept away from the input circuit. The AD10242 does not differentiate between analog and digital ground pins because the AD10242 should always be considered an analog component. All ground pins should be connected directly under the AD10242. The printed circuit board should have a ground plane covering all unused sections on the component side of the board to provide a low impedance path and manage power and ground currents. The ground plane should be kept away from the area near the input pins to reduce stray capacitance.

layout information

The schematic of the evaluation board (Figure 15) represents a typical implementation of the AD10242. The AD10242 has a very simple pinout for ease of use and high frequency/high resolution design practice. It is recommended to use high quality ceramic chip capacitors to connect each power pin directly to ground from the device. All capacitors except one placed in the encoder can be standard high quality ceramic chip capacitors. As mentioned earlier, the capacitors used on the encoder pins must be low inductance chip capacitors.

Care should be taken when placing digital outputs for operation. Because the digital outputs have such high slew rates, capacitive loading on the digital outputs should be minimized. The circuit traces for the digital outputs should be kept shorted and connected directly to the receive gate. Internal circuitry buffers the output of the AD9042 ADC through a resistor network to eliminate the need to externally isolate the device from the receive gate.

Evaluation Committee

The AD10242 evaluation board (see Figure 16) is designed to provide optimum performance for evaluation of the AD10242 analog-to-digital converter. The board includes everything needed to ensure the highest level of performance assessed by the AD10242.

The power for the analog power pins is connected through the banana jack. The analog supply powers the crystal oscillator, associated components and amplifiers, and the analog portion of the AD10242. The digital outputs of the AD10242 are powered through pin 1 of J9 or J10 on the digital interface connector. To power the evaluation board from a 5 V supply, connect a jumper wire between test points E1 to E4. Contact factory if additional layout or application assistance is required.

Dimensions