The ISL6310 is an integrated MOSFET driver. It provides precise voltage regulation systems for a variety of applications including but not limited to: high current low point load converters, embedded applications and other general low voltage media for high current applications. The integration of power MOSFET drivers into the controller IC marks a departure from the previous multi-stage product family of standalone PWM controller and driver configurations. By reducing the number of external components, this integration allows for a cost as well as space saving power management solution. The output voltage can be programmed using the on-chip DAC or an external precision reference. The two-bit code program DAC references one of 4 possible values (0.6V, 0.9V, 1.2V, and 1.5V). A unity-gain differential amplifier is provided for remote voltage sensing, compensating for any potential differences between remote and local ground. The output voltage can also be achieved by using a single external resistor. An optional droop function is also implemented to disable voltage change requirements or less severe step loads for applications with less stringent output requirements. A unique feature of the ISL6310 is the combined use of both DCR and Radio Data System (ON) current sensing. Load line voltage positioning and overcurrent protection are accomplished through continuous inductor DCR current sensing, while rDS(ON) current sensing is used for precise channel current balancing. The best advantages of each technique using the two current sampling methods. The protection functions of this controller IC include comprehensive overvoltage and overcurrent protection. The overvoltage causes the inverter to turn down the mosfet's clamp to protect the load against the rising output voltage. An OVP output is also provided to drive an optional crowbar mechanism. Set the overcurrent protection level through an external resistor. Additional protection features include preventing the remote control from disconnecting the sensor input. These features combine to provide advanced output load protection.

feature

Integrated multiphase power conversion - 1 or 2 phase operation

Accurate Output Voltage Regulation - Differential Remote Sensing Voltage - System Accuracy ±0.8% Over Temperature (Reference Voltage = 0.6V and 0.9V) - System Accuracy ±0.5% Over Temperature (Reference Voltage = 1.2V and 1.5V) - Can Be Used Not Exceeding 2.3 Output Voltage of V - Adjustable Reference Voltage Offset

Accurate channel current sharing - using lossless rDS (on) current sampling

Optional Load Line (Down) Programming - DCR Current Sampling with Lossless Inductor

Variable Gate Drive Bias -5V to 12V

Internal or external reference voltage setting - on-chip adjustable fixed DAC reference voltage 2-bit logic input to select voltage from 4 fixed references (0.6V, 0.9V, 1.2V, 1.5V) - reference can be changed dynamically - external voltage reference can be used

overcurrent protection

Multilayer Overvoltage Protection - Drives OVP Pin of Optional Crowbar Device

Selectable operating frequency up to 1.5MHz per phase

digital soft start

Capable of starting with pre-biased loads

Lead-free plus annealed (RoHS compliant) available

application

High Current DDR/Chipset Core Voltage Regulator

High Current, Low Voltage DC/DC Converters

High Current, Low Voltage FPGA/ASIC DC/DC Converters

Absolute Maximum Ratings

Supply voltage, VCC. -0.3V to +6V

Supply voltage, PVCC. -0.3V to +15V

Absolute startup voltage, VBOOT. Ground -0.3V to Ground + 36V

Phase voltage, V phase. Ground -0.3V to 15V (PVCC=12)

Ground -8V (<400ns, 20μJ) to 24V (<200ns, VBOOT-Phase=12V)

Upper gate voltage, VUGATE. Phase V -0.3V to VBOOT+0.3V

Phase V -3.5V (<100ns pulse width, 2μJ) to VBOOT+0.3V

Low gate voltage, VLGATE. Ground -0.3V to PVCC+0.3V

GND-5V (<100ns pulse width, 2μJ) to PVCC+0.3V

Input, output or I/O voltage. Ground -0.3V to VCC+0.3V

ESD classification. Class 1 JEDEC standard

Recommended Operating Conditions

VCC supply voltage. +5V±5%

PVCC supply voltage. +5V to 12V±5%

Ambient temperature (ISL6310CR, ISL6310CRZ). 0°C to 70°C

Ambient temperature (ISL6310IR, ISL6310IRZ). -40°C to 85°C

Hot information

Thermal resistance θJA (°C/W) θJC (°C/W)

QFN package (Note 1, 2). 35 5

maximum junction temperature. 150 degrees Celsius

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

1. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct connect" characteristics.

2. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Operating conditions recommended by electrical codes unless otherwise specified.

Operating conditions recommended by electrical codes unless otherwise specified. (continued)

Note:

3. The magnitude of the parameters guaranteed by the design. Not 100% tested.

Function pin description

VCC (Pin 3) provides bias power for the small signal circuits of the IC. Connect this pin to the +5V supply and use a mass 1.0µF ceramic capacitor for local decoupling.

PVCC (pin 15)

Power supply pin for MOSFET driver. This pin can be connected to any voltage between +5V and +12V, depending on the desired MOSFET gate drive level.

Ground (Pin 33)

Bias and reference ground for integrated circuits. ENLL (Pin 20) This pin is the input for the threshold sensitive (~0.66V) enable controller. Hold low, this pin disables controller operation. Pulled high, the pin enables the controller

operate.

A resistor from FS (pin 29) from FS to ground will set the switching frequency. See Equation 33 and Figure 24 for resistance calculations.

2PH (pin 31)

This pin is used to select between single-phase or two-phase operation. Connecting this pin to VCC allows 2-phase operation. Connecting the 2PH pin to GND causes the controller to

Single phase mode.

REF0 and REF1 (Pins 30, 21) These pins form the 2-bit input reference voltage that selects the fixed DAC. These pins respond to TTL logic thresholds. The ISL6310 decodes these inputs to establish one of four fixed reference voltages; see "Table 1" REF0 and REF1 Inputs and Reference Voltage Settings. These pins are pulled high internally, about 1.2V, through an internal current source of 40µA (typically); as the REF0 and REF1 voltages increase, the internal pull-up current decreases to 0 close to the internal pull-up voltage. The REF0 and REF1 pins are compatible with external pull-up voltages exceeding the IC's bias voltage (VCC).

VSEN and RGND (pins 8, 7)

VSEN and RGND are the input telemetry amplifiers of the precision differential and should be connected to the remote load pins of the telesensor. ICOMP, ISUM, and IREF (pins 10, 12, 13) ISUM, IREF, and ICOMP are the current meaning of the DCR The negative input, positive input, and output of the amplifier are, respectively. To accurately sense the DCR current, connect the phase node from each channel to ISUM and connect IREF to the summing point of the output inductor, roughly speaking. A parallel RC feedback circuit generates a voltage IREF between ISUM and ICOMP to ICOMP and the inductor DCR. This voltage is called the drop voltage and is added to the output of the differential sense amplifier. An optional 0.001-0.01µF ceramic capacitor from the IREF pin to the ISUM pin helps reduce pattern noise that may be introduced by the layout.

sag (pin 11)

This pin enables or disables droop. Tie this pin to the icon to enable drooping. To disable droop, connect this pin to the IREF pin.

VDIFF (pin 6)

VDIFF is the output of the differential telemetry amplifier. The voltage on this pin is equal to VSEN and RGND plus IREF and ICAMP. Therefore, VDIFF represents the VOUT voltage plus

drop voltage.

The inverting input and output of the error amplifier within FB and COMP (pins 5, 4) are respectively. FB is compensated via an external R or RC network depending on the desired type (Type II or Type III). COMP is tied to FB through an external RC network compensation regulator

DAC (pin 32)

The DAC pin is the direct output of the internal DAC. This pin uses a 1-5kΩ resistor to connect to the reference pin, which can be left open if using an external reference.

Reference (Pin 1)

The REF input pin is the positive input of the error amplifier. This pin can be connected to the DAC pin using a resistor when the internal DAC voltage is used as a reference voltage. When using an external voltage reference, it must be connected directly to the REF pin, and the DAC pin is left unconnected. The output voltage will be regulated to the voltage at the reference pin unless that voltage is greater than the voltage at the DAC pin. If an external reference pin is used here, its size cannot exceed 1.75V. Use a capacitor between the reference pin and ground to smooth the DAC voltage during soft-start.

OFT (pin 2)

The OFT pin provides a way to create an offset voltage across the resistor between FB and VIDIF. The offset current is passed through external resistors and a precision internal voltage reference. Polarity is achieved by connecting a resistor to GND or VCC. For no offset, the OFST pin should remain unconnected.

Catenary (Pin 9)

This is the overcurrent setting pin. Placing a resistor from OCSET to ICOMP allows 100 microamps of current to flow from this pin, creating the voltage reference. The internal circuit compares the voltage of OCSET to the voltage of ISUM, if ISUM exceeds OCSET, the over current protection is activated.

ISEN1, ISEN2 (pins 26, 16)

These pins are used to balance channel current through each channel's lower MOSFET sense current when it's conducting. Connect a resistor between ISEN1 and ISEN2 pins and their respective phase nodes. This resistor sets the current proportional to the current of the lower MOSFET during its conduction interval. UGATE1 and UGATE2 (pins 25, 17) connect these pins to the gate of the upper mosfet. These pins are used to control the upper mosfet to be monitored for fire prevention. The maximum single channel duty cycle is limited to 66%. BOOT1 and BOOT2 (pins 24, 18) These pins provide bias for the upper mosfet to drive. Connect these pins to appropriately selected external bootstrap capacitors. An internal bootstrap diode connected to the PVCC pin provides the necessary bootstrap charging. Phase 1 and Phase 2 (pins 23, 19) connect these pins to the power supply of the upper mosfet. These pins are the drive on the mosfet's return path. LGATE1 and LGATE2 (pins 27, 14) These pins are used to control the lower mosfet to be monitored for fire prevention. Connect these pins to the lower mosfet gate. External series gate resistors are not used as this may cause shoot-through.

PGOOD (Pin 28)

PGOOD is used to indicate the end of soft-start. It is an open-drain logic output that is low impedance until soft-start is complete and Vout equals the VID setting. Once normal operation PGOOD indicates whether the output voltage is within the specified overvoltage and undervoltage range. If the output voltage exceeds these limits or a reset event occurs (such as an overcurrent event), PGOOD becomes high impedance again. The potential of this pin should not exceed the potential of the VCC pin any time the forward diode drops

OVP (pin 22)

Overvoltage protection pin. when an overvoltage condition is detected. Connect this pin to a thyristor or MOSFET gate connected between VIN and ground to prevent damage to the load device.

operate

Multiphase Power Conversion

The advantages of modern low voltage DC/DC converter load current distributions having shifted to multiphase power conversion cannot be ignored. This technical challenge of producing a single-phase converter that is both economical and thermally feasible has forced us to change the cost-saving approach to multiphase. The ISL6310 controller helps simplify the implementation of minimal external components by integrating important functions and requirements. The block diagram on page 2 provides a top-level view of multiphase power conversion using the ISL6310 controller.

Switching converter for each channel based on ISL6310 with other channels. Therefore, the two-phase converter has twice the combined ripple frequency of one of the phases. In addition to this the combined inductor current is scaled down (Equations 1 and 2). Ripple frequency increases and ripple amplitude decreases generally translates to lower per-channel inductance and lower total output capacitance specifications for a given set of performance. Figure 1 illustrates the output ripple frequency. Dual channel currents (IL1 and IL2) are combined to form AC ripple current and DC load current. The ripple of the ripple component is the frequency of the current in each channel.

To understand ripple current amplitudes in polyphase circuits, examine the peak-to-peak inductor currents representing individual channels.

In Equation 1, VIN and VOUT are the input and output voltages, L is the single-channel inductance value, and FSW is the switching frequency. The output capacitor conducts the inductor current. In the case of multiphase converters the capacitive current is per individual channel. Combine Equation 1 with the expression for the peak-to-peak current after summing N symmetrically phase-shifted inductor current Equation 2. The peak-to-peak ripple current is reduced by an amount proportional to the number of channels. The output voltage ripple is a function of capacitance, equivalent series resistance (ESR) and inductor ripple current. Reducing inductor ripple current allows designers to use fewer or less expensive output capacitors.

Another benefit of interleaving is reducing input ripple current. The input capacitor section is determined by the maximum input ripple current. Multiphase topologies can increase overall system cost and scale by reducing input ripple, enabling designers to reduce the cost of input capacitors. The example in Figure 2 demonstrates the current total input ripple current into a two-phase converter.

Figures 25 and 26 in the section titled "Input Capacitors" can be used to determine the input capacitor RMS based on load current, duty cycle and channel selection. in determining the optimal input capacitance solution. The timing of the PWM operation of each converter branch is determined by the active channel. The default channel setting for the ISL6310 is two. One switching cycle is defined as the internal PWM1 pulse termination signal. The pulse termination signal is an internally generated clock signal that triggers the falling edge of PWM1. The cycle time of the pulse termination signal is reversed by switching the frequency set by a resistor between the FS pin and ground. When commanded by the clock signal, PWM1 goes low at the beginning of each cycle. A PWM1 transition means internally turning off the channel 1 MOSFET driver on the upper channel of channel 1 and turning on the channel 1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse terminates 1/2 of a period after the PWM1 pulse. One switching cycle of the ISL6310 is defined as between successive PWM pulse terminations (turning off the upper MOSFET on the channel). Each cycle begins with the switching clock signal commanding the upper MOSFET off. The upper MOSFET conduction of the other channel is terminated after 1/2 of a cycle. Once a PWM pulse transitions low, it will remain low for a minimum of 1/3 cycle. Forced off-time requirements ensure accurate current samples. Current sensing is described in the next section. When the forced off time expires, the PWM output will be enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the sawtooth ramp as shown in Figure 3. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output is highly transitioned. The internal MOSFET driver detects the changing state of the PWM signal and turns off the synchronous MOSFET and turns on the upper MOSFET. Before the pulse is terminated, the PWM signal will remain high by triggering the PWM signal low. Single-phase operation can be grounded optionally by connecting 2PH.

Channel current balance

An important advantage of multiphase operation is by distributing heat dissipation to multiple devices and larger areas. By doing so designers avoid the expense of driving parallel MOSFETs and using expensive heat sinks and exotic magnetic materials. To achieve thermal advantage, it is important that each channel in a multiphase converter is controlled to carry the same amount of current at any load level. To achieve this, the current through each channel must be sampled every switching cycle. The sampled current, In, is summed from each active channel and divided by the number of active channels. The resulting cycle average current, IAVG, provides a measurement cycle of the total load current demand on the converter during each switching period. Channel current balancing is performed by comparing the sampled currents of each channel to the cycle-averaged current and making appropriate adjustments to the error-based pulse width for each channel. Intersil's patented current balance method is shown in Figure 3, with errors indicating the correction of channel 1. In the figure, the loop compares the average current IAVG with channel 1 Example I1 for creating the error signal IER. The filtered error signal changes the pulse width by the VCOMP command to correct any imbalance and force closer to zero. The same method of correction of error signals is applied to each active channel.

Current sampling

To achieve proper current balance each channel must be sampled every switching cycle. This one does a sample low transition during the forced off time after PWM. During this time, the current sense amplifier uses the ISEN input to reproduce the inductor current, IL. Ethan, scaled version of sensed current inductor current. The example window is fully open for 1/6 of the switching period, tSW, low at the PWM transition. The example window then remains open for the remainder of the switching cycle until the PWM transitions high again, as shown in Figure 4. The sampling current is proportional to the inductor current at the end of the sampling and is held until the next switching cycle sample. The sampling current is only used for channel current balancing.

The ISL6310 supports MOSFET rDS(ON) current sensing to sample the current of each channel for channel current balance. The internal circuit shown in Figure 5 represents the n of the channel n-channel converter. This circuit repeats each channel in the converter, but may not be active depending on the state of the 2PH pin, as in the PWM operation part.

The ISL6310 senses the voltage on the MOSFET rDS(ON) by sampling the channel load current, as shown in Figure 5. A ground referenced op amp, connected internally to the ISL6310, rises through a resistor. The rising voltage is equivalent to the voltage drop across the rDS(ON) of the lower MOSFET when it is conducting. The resulting current into the ISEN pin is proportional to the channel current. The Eisen Current is sampled as described in the Current Sampling and Hold section. As can be seen from Figure 5, the following formula for In is where IL is the channel current.

Output Voltage Setting The ISL6310 uses a digital-to-analog converter (DAC) to generate reference voltages from logic signals at the REF0 and REF1 pins. The DAC decodes the 2-bit logic signal into a discrete voltage as shown in Table 1. Each REF0 and REF1 pin is pulled to an internal weak supply voltage of 1.2V (40µA current, reduced to 0 because the voltage on the REF0, REF1 pins is pulled up from 0 to the internal 1.2V voltage). External pull-up resistors or an active high output stage can increase the pull-up current supply up to 5V. The DAC pin must be connected to the reference pin with a 1-5kΩ resistor and filter capacitor (0.022µF) connected between REF and GND. The ISL6310 is adaptable to the use of external voltages If the output voltages are different, a reference connection to the reference pin is necessary. The DAC voltage must be set to at least the external reference. The internal non-vertical input of the error amplifier is the lower value of the reference or (DAC+300mV). A third way to set the output voltage is to use a resistive divider (RP1, RS1) at the output (VOUT) to set the output voltage level, as shown in Figure 6. This method produces up to 2.3V (reference voltage is set to 1.5V). In this case, the output voltage can be obtained as follows:

It is recommended to choose resistance values less than 500Ω for RS1 and RP1 resistors for better output voltage DC accuracy.

Voltage regulation

To regulate the output voltage to the specified level the ISL6310 uses an integrated compensation network as shown in Figure 6. This compensation network ensures that state errors in the output voltage are limited to the reference voltage (DAC output or external voltage reference) and offset error sources for the OFS current, remote sensing and error amplifiers. Intersil's specified guaranteed tolerances for ISL6310 include the combined tolerances of these components, unless an external reference or voltage divider is used, then the tolerances of these components must be considered.

The ISL6310 includes a sense amplifier in the feedback path of an internal differential remote control. The amplifier removes the voltage error encountered when measuring the output with respect to the voltage at the controller's ground reference, resulting in a more accurate method of sensing the output voltage. Connect the output sense pin of the load to the non-inverting input, VSEN, and the inverting input, RGND, to the remote control amplifier. The drop voltage VDROOP is also input to the remote control amplifier. The remote sense output, VDIFF, is therefore equal to the output voltage VOUT and the drop voltage. VDIFF is connected to the error amplifier through an external resistor. The output of the error amplifier VCOMP is used to generate a sawtooth wave of the pulse width modulated signal. The PWM signal controls the timing of the internal MOSFET driver to adjust the converter output so that the voltage at FB is equal to the reference voltage. This will regulate the output voltage equal to Equation 5. The circuit for internal and external control voltage regulation is shown in Figure 6.

Load line (drop) regulation applies precisely controlled output impedance to certain high current applications. This output voltage to load current relationship is often referred to as "droop" or "load line" regulation. Droop is an optional feature in the ISL6310. It may be enabled by connecting the ICOMP pin to the drop pin as shown in Figure 6. To disable it, connect the drop pin to the IREF pin. As shown in Figure 6, the voltage VDROOP and the total current in all active channels are input to the differential telemetry amplifier. The voltage generated by the remote control amplifier output is the output voltage and the drop voltage. As shown in Equation 5, entering this voltage into the compensation network causes the regulator to adjust the output voltage to equal the reference voltage minus the droop voltage. The droop voltage VDROOP is induced by the current through the output inductor. This completes the current sensing method using continuous DC resistance. The inductor winding has a distributed characteristic resistance or DCR (direct current resistance). For simplicity, the inductive DCR is considered an independent lumped quantity, as shown in Figure 7. The channel current, IL, flows through the inductor, through the DCR. Equation 6 shows the s-domain equivalent voltage, VL, across the inductor.

The inductor DCR is important because the voltage drop is proportional to the channel current. By using a simple RC network and a current sense amplifier, as shown in Figure 7, the voltage drop across all inductor DCRs can be extracted. The output of the current-sense amplifier, VDROOP, can be displayed as channel-proportional currents IL1 and IL2, as shown in Equation 7. If the RC network component is selected, the RC time constant matches the inductor L/DCR time constant, and VDROOP is equal to the sum of the voltages dropped through a single DCR, multiplied by the gain. As Equation 8 shows, VDROOP is therefore related to the total output current, IOUT.

By simply adjusting the value of RS, the load line can be set at any level, allowing the converter to operate at all load currents. It may also be necessary to compensate for temperature-induced DCR changes. These changes skew the load line and cause the RC time constant to not match the L/DCR time constant. If this becomes a problem a simple NTC resistor network can be used instead of RCOMP to compensate due to temperature. The output voltage offset programming of the ISL6310 allows the designer to precisely adjust the compensation voltage by connecting the resistor ROFS from the OFS pin to VCC or GND. When ROFS is connected between OFS and VCC, its voltage is regulated to 1.5V so that proportional current (IOFS) flows into OFS pin and out from FB pin. If ROFS is grounded, the voltage across it is regulated to 0.5V and IOF flows into the FB pin and OFS pin. The offset current through the resistor between VDIFF and FB will produce the desired offset voltage equal to the product (IOFS x R1). These functions are shown in Figures 8 and 9. Once the desired output offset voltage is determined, set ROF using the following formula: For positive offset (connect ROFS to GND)