functional application

10 fully differential input AC motor speed control 5 channels synchronous sampling three-phase power control plus 2 synchronous sampling

channel

Vibration Analysis

3 simultaneous 12-bit ADCs μ 12.8s throughput digital selectable input range ±5V power supply IUP/number serial digital input/output A1P/NADOUT1 number 3 digital signatures A2P/N number

Programmable Window Comparator IVP/N No. Description B1P/NADOUT2 No. B2P/No.

The VECANA01 consists of three 12-bit analog-to-digital converters, preceded by five IWP/numbers simultaneously for 10 differential inputs to operate sample-and-hold amplifiers and multiplexers. The ADC has an analog serial output for high-speed data transfer and data processing. AN1P/No. ADOUT3 No. AN2P/No. AN3P/No. VECANA01 also offers programmable gain amplifiers with programmable gains of 1.0V/V, 1.25V/V, 2.5V/V and 5.0V/V. Channel selection and gain selection can be re-output by serial input control word selection.

This part also contains an 8-bit digital-to-analog converter - a converter whose digital input is provided as part of the input control word.

Functional Description Figure 1. Functional diagram.

The VECAN01 is a triple 12-bit SAR a/D converter powered by dual ±5V supplies. This section includes three 12-bit successive approximation ADCs, 10 fully differential input multiplexers, 5 differential input synchronous sample-and-hold amplifiers, and two asynchronous sample-and-hold amplifiers. It communicates via three simultaneous SPI/SSI serial outputs and one input port. The VECANA01 runs on an external clock, which also determines the output data rate (see Figure 2).

multiplexer
The VECANA01 has multiple input multiplexers to select the desired analog inputs and connect the appropriate sample and hold outputs to the PGAs and A/D converters. The decoder receives its input from the input setup register and drives the mux (see Table VII and Table VIII for information on selecting the input channel). The input multiplexer can accept fully differential or single-ended signals (see Figure 4 and Table III). The analog signal is differentially sampled and held through the PGA all the way to the input of the A/D converter. This provides the best noise rejection.
Sample Hold The VECANA01 contains seven sample and hold amplifiers. Five of them (SH1 to SH5) are sampled at the same time, and the sample and hold timing is synchronized internally (timing is shown in Figure 2). Three sample and hold (SH1, SH3, and SH5) are connected to the input multiplexer so that they can provide simultaneous sampling for all channel inputs. Additionally, SH2 and SH4 simultaneously sample the third input of their channel (A2 and B2, respectively). This is useful in motor control applications where A1 and B1 are the quadrature inputs of one position sensor and A2 and B2 are the quadrature inputs of a second position sensor (see Figure 9). In this application, it is desirable to sample the quadrature inputs of a given position sensor simultaneously (even if they are converted in consecutive conversion cycles) (see Table VII) in order to capture their values at the same axis position. VECANA01 also has limited asynchronous sampling capability. The sampling of SH6 and SH7 is asynchronously controlled by the control signal NPSH (see Table 7). This allows two inputs, on Channel 1 and Channel 2 (see Table VIII), to be sampled asynchronously from another sample-and-hold timing. This is useful in motor control applications where the two inputs per channel need to be sampled asynchronously to a reference point.

ADCs and PGAs
figure 2. Timing diagram. The VECANA01 contains three signal channels, each with a 12-bit A/D converter output. The A/D converters work synchronously, and their serial outputs occur simultaneously (Table 9 shows the analog input/digital output relationship). The programmable gain amplifier is located before the A/D converter (the gain selection information is given in Table 9). For channel 1 and channel 2, the PGA is valid for all three analog inputs. For the third channel, the PGA only changes the gain of the IW input. Regardless of the gain selection value, the inputs AN1, AN2, and AN3 are connected to A/D Converter 3 with a fixed gain of 1.0V/V.

voltage reference
VECANA01 contains an internal 2.5V voltage reference. It can be obtained externally through the output buffer amplifier. If you need to use an external reference, you can connect one at the REFIN pin. The output resistance of this pin to the external reference voltage is typically 7kΩ. This then overrides the internal 2.5V reference and connects to the A/D converter. It can also be used as a buffered output for the re-output.
The reference voltage should be buffered on the REFIN pin and the REFOUT pin (see Figure 3) with external capacitors (~2.2µF) as close as possible to the pins.

image 3. Reference voltage connection. digital to analog converter

The 8-bit DAC provides 256 output voltage levels from 0V to 2.499V (see Table I for the input/output relationship). The DAC is controlled by the DAC input section of the input setup word. The DAC input portion of the word is selected into the DAC at the end of the conversion cycle (14th CLK pulse in Figure 2).
digital input
DAC Inputs 0-7
Analog output
+0.0098 Volt French Franc Table 1.DAC input/output relationship.
DAC output voltage
The value of the DAC output voltage is determined by the DAC input portion of the ADI word (bits 0 to 7, see Figure 2). The 8-bit DAC has 256 possible output steps from 0V to +2.499V. The value of 1LSB is 0.0098V.
Other digital input and output sampling and conversion are controlled by the ADCONV and ADCLK inputs (see Figure 2). The VECANA01 is designed to operate from an external clock provided at the ADCLK input. This allows transitions to be synchronized with system timing, thereby minimizing transient noise effects. The ADCLK signal can run continuously or only during a conversion sequence. The ADBUSY and DATACLK signals are generated internally and are provided to make interfacing with the microprocessor easier (see Figure 2 and Figure 9).
Power-On Initialization When the VECANA01 is powered up, initialization requires two conversion cycles before valid digital data is transmitted on the third cycle. The first conversion after power-up is performed with an indeterminate configuration value in the double-buffered output of the input setup register. The second conversion cycle loads the desired value into the register. The third conversion uses these values to perform the correct conversion and output valid digital data from each A/D converter.

Clock Position (1)
Description function
DAC input 0-7 set DAC output voltage gain selection 0-1 set PGA gain input selection 0-2 Condition determination multiplexer Note: (1) See Figure 2, "Clock Pulse Reference Number" Table 2. Description of configuration parameters.

Configurable parameters include: PGA gain input multiplexer and sample and hold selection DAC output voltage The configuration information for these parameters is contained in ADINword (see Figure 2). When a conversion is in progress, the configuration for the next conversion is loaded into the buffered input setup register via the ADIN word. Tables 1, 7, 8, and 10 show information about these parameters.
The analog-to-digital converter A/D converter is a 12-bit successive approximation type realized by a switched capacitor circuit.

clock rate
The clock for A/D converter conversion is provided externally from the ADCLK pin. The typical clock frequency for the specified accuracy is 1.25MHz. This results in a full conversion cycle (S/H acquisition and A/D conversion) of 10.4 microseconds.
input Output
The VECANA01 is designed for bipolar input voltages and uses a two's complement digital output code. Each A/D converter has a programmable gain function. This changes the converter's full-scale analog input range and analog resolution.
Differential and Common Mode Input Voltages
The VECANA01 is designed with a fully differential signal path from the multiplexer input to the A/D converter input. This is done to provide superior high frequency noise rejection. As with most differential input semiconductor devices, there is a compound limit to the combination of differential input voltage and common-mode input voltage. This problem is slightly complicated by the fact that most analog inputs can be affected by the programmable gain function. Possible differential and single-ended configurations are shown in Figures 4a and 4b. The maximum differential and common-mode limits are shown in Table 3.

Input Setup When the A/D converter converts and transmits its serial digital data during one conversion cycle, a setup word is received for use in the next conversion cycle. The 13-bit word is provided by ADINpin (see Figure 1) and stored in the buffered input setup register. The input select and gain select parts of the word are decoded and determine the state of the multiplexer and pga (see the Configurable Parameters section).
The input multiplexer and sample-and-hold select decode the input select portion of the ADIN word (bits 10, 11, and 12) (see Figure 2) and determine the multiplexer on/off conditions. This in turn determines which input signals are connected to the sample and hold, and which sample and hold is connected to the PGAs/adc.
The symbol of the input signal
VECANA01 contains seven comparators that take the signals of the first seven input analog signals. The digital output of the sign comparator is the signal xu COMP. If the positive input value is greater than the negative input value, the X-COMP output goes high (logic "1") or vice versa, the X-COMP output goes low (logic "0") (see Table 4).
Table 4. Input-output relationship.
Figure 4. (a) Differential signal source. (b) Single-ended input.

Typical hysteresis values for comparators UúCOMP, VúCOMP, and WúCOMP are 10mV. Typical hysteresis values for comparators A_1, A_2, B_1, and B_2 are 50mV. AC motor control applications typically use 10 mV hysteresis for phase current measurements and 50 mV hysteresis for position sensor measurements.
Over-distance recognition
VECANA01 also includes three window comparators for the three input signals IU, IV and IW. Each window comparator consists of two comparators that monitor the input values for the positive scale limit (UPLIM) and the negative scale limit (UNLIM). The output value of the window comparator is output through pins UúILIM, VúILIM and WúILIM. These two range limits are symmetrical to the zero point (UNLIM=–UPLIM) and are determined by pin Dan. A graphical view of the overrun setting function (usually used to set the current protection value) is shown in Figure 5, the DAN value will determine the fixed range. Typically, this pin is connected to DAOUT (DAC output). In order to be able to program the range value through the control value DAC input word, the DAC input is an 8-bit wide unsigned value that controls the digital-to-analog converter output voltage (DAOUT). The output voltage range of this D/A converter is 0V to 2.5V (see Table I).
Table 5: Overcurrent limit as input to functional DAC.
If the input voltage exceeds the positive range limit (IXP–IXN>UPLIM) or remains in the negative range (IXP–IXN Table 6: Limits as a function of DAC input.
When the gain selection is 3, the input voltage range of the comparator is the same as that of the A/D converter. The typical hysteresis value of the comparator is 50mV. Figure 5 shows the logic states of the U-COMP and U-ILIM outputs of the input signal IVP–IUN. The output resistance of the D/A converter is about 10kΩ. The output voltage, DAOUT, should be buffered by a capacitor of about 100nF (see Figure 6), resulting in a time constant of about 1ms, which usually does not interfere with most applications.
Input Signals for PGAS/ADC Table 7 shows the relationship between the values of input options 0-2 and the converted signal.
Input Select = 7H - Simultaneously sample and convert input signals IU, IV and IW.
Figure 5. Acquisition of current signal and overcurrent.

Note: (1) See Table 8 for operation.
Table seven. Synchronized sample-and-hold input control.
Input Selection = 4H, 5H, 6H - Simultaneously sample and convert input signals A1, B1 and AN1. These codes also cause SH2 and SH4 to sample their inputs. Values 4H, 5H, and 6H have different effects on the input of SH6 and SH7 (see Table VIII).
Table eight. Asynchronous sample-and-hold input control.
Input Select = 3H - Convert A2 via SH2, Convert B2 via SH4, and AN2 (A2 and B2 from values sampled in the previous conversion cycle with Input Select 4H, 5H, or 6H).
Input Select = 2H - Convert A2 via SH1, Convert B2 via SH3, and AN2.
Image 6. Basic circuit configuration.

Table 9: Analog input-digital output relationship.
Input Select = 1H - Input AN3 is converted by ADC3. The outputs of asynchronous sample and hold SH6 and SH7 are converted by PGA1/ADC1 and PGA2/ADC2, respectively. Note that the inputs to SH6 and SH7 are determined by the previous input selection values (see Table VIII). Therefore, to correctly convert an asynchronous sample-and-hold output, it first needs to select its input using the previous conversion cycle. Also, the output of SH6 or SH7 will only be converted if NPSH goes low before the ADCONV command is received.
Input Select = 0 H-AN3 is converted by ADC3. The inputs to PGA1/ADC1 and PGA2/ADC2 are undefined.
PGA gain
The PGA gain is determined by the gain selection section (bits 8 and 9) in the ADIN word (see Figure 2). There is a gain input that sets the same gain for all three PGAs. Gain values and allowable full-scale inputs are shown in Table X.
Table X. Gain selection information.
For Channel 1 and Channel 2, the PGA sets the gain for all three analog inputs. For the third channel, the PGA only changes the gain of the IW input. Regardless of the gain selection value, the inputs AN1, AN2 and AN3 are connected to A/D converter 3 with a fixed gain of 1.0V/V.
Asynchronous Example Hold Conversion Notes Note: The programmable gain feature applies to all three input channels of ADC1 and ADC2. However, the programmable gain function is only available for the first input (IW) of ADC3. The other three inputs (AN1, AN2, and AN3) are not affected by the gain selection input. They operate at a fixed gain of 1V/V and therefore have a fixed ±2.5V full-scale input range.
The decode input selection value also determines which inputs are applied to the sample hold (SH6 and SH7) of the two asynchronous controls (see Table VIII). The input selection value selects one of three possible inputs four, five or six years old. A "no effect" state means that these input select values have no effect on the multiplexer at the SH6 and SH7 inputs. When one of the "no effect" values of the input selection occurs, the multiplexer will not change (ie, its condition is determined by the last 4, 5 or 6 values of the input selection that existed before the "no effect" state). Note that the input Select=1H represents the output of SH6 and SH7 to PGA1/ADC1 and PGA2/ADC2 respectively (see Table 7). Therefore, to correctly convert an asynchronously sampled signal, it is necessary to first select an input signal with one load/convert cycle (input selection equal to 5 or 6 in Table VIII), and then convert the sample-and-hold output in a subsequent conversion cycle (in Table VII). input selection = 4).
power supply
VECANA01 requires an analog and digital supply voltage of ±5V. The substrate is connected to UP5V. The voltage difference between the analog and digital power pins is not allowed to exceed the maximum value of 300mV. Therefore, it is recommended to use the circuit shown in Figure 7 as a power supply. The analog and digital power supplies are driven by a common power supply. Intermediate resistors provide decoupling. The local current-limiting voltage regulator generates ±5V from the analog supply voltage ±UB. This ensures further noise reduction. The diodes are responsible for protecting regulation and preventing polarity reversal. Zener diodes prevent overvoltages from overvoltages to the analog inputs. Typical values for resistors and capacitors are:

RA≈3Ω

RD≈3Ω

CD≈22μF

Calcium ≈ 22 μF

CB≈100nF

Chromium ≈ 2.2 μF