feature

Low-power, smallest pin-compatible, four-nanometer digital-to-analog converter; AD5664R : 16-bit; AD5644R: 14-bit; AD5624R: 12-bit; user selectable external or internal reference; external reference default; on-chip 1.25 V/2.5 V , 5 ppm/°C reference; 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD ; and; Power-on reset to zero scale; power-down per channel; serial interface, up to 50 MHz.

application

Process Control; Data Acquisition Systems; Portable Battery-Powered Instruments; Digital Gain and Offset Adjustment; Programmable Voltage and Current Sources; Programmable Attenuators.

General Instructions

The AD5624R/AD5644R/AD5664R, members of the nanoDAC 174 ; family, are low power, four-bit, 12-/14-/16-bit buffered voltage output DACs. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design.

The AD5624R/AD5644R/AD5664R have an on-chip reference. The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference with a full-scale output range of 2.5 V; the AD56x4R-5 has a 2.5 V, 5 ppm/°C reference with a 5 V full-scale output range. The chip reference is turned off at power-up, allowing the use of an external reference; all devices can be operated from a single 2.7 V to 5.5 V supply. Internal references are enabled by software writing.

This part includes a power-on-reset circuit that ensures the DAC output powers up to 0v and remains there until a valid write occurs. This section includes a per-channel power-down feature that reduces the device's current consumption to 480NA at 5V, providing a software-selectable output load in power-down mode. The low power consumption of this part during normal operation makes it ideal for portable battery-operated devices.

The AD5624R/AD5644R/AD5664R use a multi-function 3-wire serial interface with an operating clock frequency up to 50MHz, and are compatible with standard SPI, QSPI 8482 ; MicroWire™ and digital signal processor interface standards. On-chip precision output amplifiers achieve rail-to-rail output swing.

Product Highlights

1. Four 12/14/16-bit DACs.

2. On-chip 1.25 V/2.5 V, 5 ppm/℃ benchmark.

3. Provide 10-lead MSOP, 10-lead, 3 mm×3 mm LFCSP-WD and 12-ball, 1.665 mm×2.245 mm WLCSP.

4. Low power, typically consumes 1.32mW at 3V and 2.25mW at 5V.

Typical performance characteristics

the term

Relative Accuracy or Integral Nonlinearity (INL)

For a DAC, relative accuracy or integral nonlinearity is a measure of the maximum deviations (LSBs) of a straight line passing through the endpoints of the DAC transfer function. A typical INL and code diagram is shown in Figure 5.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. Monotonicity is assured by differential nonlinearity specified to a maximum of ±1 LSB. The monotonicity of the DAC is guaranteed by design. A typical DNL and code diagram is shown in Figure 8.

Zero code error

Zero-scale error is a measure of the output error when the zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0V. Due to the combination of offset errors in the DAC and output amplifier, the output of the DAC cannot go below 0V, so the zero code error is always positive in the AD5664R. Zero-code errors are expressed in millivolts. A plot of zero code error versus temperature is shown in Figure 27.

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V-1 LSB. Full-scale error is expressed as a percentage of full-scale range. A plot of full-scale error versus temperature is shown in Figure 26.

gain error

This is a measure of the span error of the DAC. It is the deviation of the slope of the DAC transfer characteristic from the ideal, expressed as a percentage of FSR.

Zero code error drift

This is a way to measure the zero code error as a function of temperature. Expressed in microvolts/degree Celsius.

Gain temperature coefficient

This is a measure of gain error as a function of temperature. Expressed in parts per million FSR/°C.

offset error

Offset error is a measure of the difference between V (actual) and V (ideal) expressed in mV in the linear region of the transfer function. The offset error is measured on the AD5664R and the DAC register is loaded with code 512. It can be negative or positive.

DC Power Supply Rejection Ratio (PSRR)

This shows how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to the change in VDD for the full-scale output of the DAC. The unit is decibel. VREF remains at 2v and VDD varies by ±10%.

Output voltage settling time

This is the time required for the output of the DAC to settle to the specified level for a 1/4 to 3/4 full-scale input change, measured from the 24 falling edge of SCLK.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault region in nV-s, measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000) (see Figure 41).

digital feedthrough

Digital feedthrough is a measurement of the pulses injected into the DAC's analog output from the DAC's digital input, but when the DAC output is not being updated. It is specified in nV-s and is measured by a full-scale code change on the data bus, i.e. from 0 to 1 and vice versa.

reference feedthrough

Reference feedthrough is the ratio of the signal amplitude at the DAC output to the reference input when the DAC output is not being updated. Expressed in decibels.

noise spectral density

This is a measure of internally generated random noise. Random noise is characterized by its spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring the noise at the output. The unit of measurement is nV/√Hz. The noise spectral density plot is shown in Figure 47.

DC crosstalk

DC crosstalk is the DC change in the output level of one DAC as the output of another DAC changes. It is measured by the full-scale output change of one DAC (or soft power off and on) while monitoring the other DAC held at mid-scale. Expressed in μV.

DC crosstalk caused by load current changes is a way to measure the effect of a change in load current on one DAC on another DAC held at midscale. Expressed in μV/mA.

digital crosstalk

This is a glitch pulse that is midscale transferred to the output of one DAC in response to a full-scale code change in the input register of the other DAC (all 0s to all 1s and vice versa). It is measured in standalone mode and expressed in nV-s.

Analog crosstalk

This is a glitch pulse transferred to the output of one DAC due to a change in the output of the other DAC. It is measured by loading an input register for a full range of code changes (from 0 to 1 and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code has not changed. The fault area is denoted by nV-s.

DAC-to-DAC crosstalk

This is a glitch pulse transferred to the output of one DAC due to a change in the digital code of the other DAC and a subsequent change in the analog output. It is measured by using the commands write-to and update to load the attacking channel and making comprehensive code changes (from 0 to 1 and vice versa) while monitoring the output of the attacked channel at the mid-scale. The fault energy is expressed in nV-s.

Double the bandwidth

Amplifiers within a DAC have limited bandwidth. Multiplying bandwidth is one measure. A sine wave on the reference appears in the output (loading the full-scale code to the DAC). The octave bandwidth is the frequency at which the output amplitude drops 3db below the input.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and a decaying sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. The unit is decibel.

theory of operation

Digital-to-analog conversion part

The AD5624R/AD5644R/AD5664R digital-to-analog converters are fabricated using a CMOS process. The structure consists of a string DAC and an output buffer amplifier. Figure 51 shows a block diagram of the DAC architecture.

Because the input encoding of the DAC is straight binary, the ideal output voltage when using an external reference is given by:

The ideal output voltage when using the internal reference is given by:

where: D is the register loaded into the DAC:

AD5624R is 0 to 4095 (12 bits).

AD5644R is 0 to 16383 (14 bits).

0 to 65535 (16 bits) for AD5664R.

N is the DAC resolution.

resistor string

The resistor string is shown in Figure 52. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

output amplifier

The output buffer amplifier can generate rail-to-rail voltages at its output, allowing the output to range from 0v to VDD. It can drive a 2 kΩ load in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier are shown in Figures 34 and 35. The slew rate was 1.8 V/µs and the full settling time was 7 µs.

internal reference

The AD5624R/AD5644R/AD5664R on-chip reference is turned off at power-up and enabled by writing to the control register. See the Internal Reference Settings section for details.

The AD56x4R-3 has a reference voltage of 1.25 V, 5 ppm/°C, and a full-scale output of 2.5 V. The reference voltage of the AD56x4R-5 is 2.5 V, 5 ppm/°C, and the full-scale output is 5 V. The internal reference voltage associated with each part is available from the VREFOUT pin. A buffer is required if the reference output is used to drive an external load. When using the internal reference, it is recommended to place a 100 nF capacitor between the reference output and GND to ensure reference stability.

xref

The VREFIN pin on the AD56x4R-3 and AD56x4R-5 allows the use of an external reference if required by the application. The default condition of the chip reference is to turn off at power up. All devices (AD56x4R-3 and AD56x4R-5) can be operated from a single 2.7 V to 5.5 V supply.

serial interface

The AD5624R/AD5644R/AD5664R have a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and MICROWIRE interface standards and most DSPs. A timing diagram of a typical write sequence is shown in Figure 2.

Pull the sync line low at the beginning of the write sequence. Data from the data line is recorded into a 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the AD5624R/AD5644R/AD5664R compatible with high-speed DSPs. On the 24 falling clock edge, the last data bit is clocked and performs the programming function, ie, a change in DAC register contents and/or a change in operating mode.

During this phase, the sync line can be held low or high. In both cases, it must be brought up at least 15 ns before the next write sequence, so that the falling edge of synchronization can initiate the next write sequence.

Because the sync buffer draws more current when VIN=2v compared to when VIN=0.8v, the sync between write sequences should be in a low idle state for lower power operation. However, as mentioned earlier, it must be turned up again before the next write sequence.

input shift register

The width of the input shift register is 24 bits (see Figure 53). The first two don't care. The next three are the command bits, C2 to C0 (see Table 8), followed by the 3-bit DAC address, A2 to A0 (see Table 9), and then the 16-, 14-, and 12-bit data words. The data word consists of a 16-, 14-, and 12-bit input code followed by 0, 2, or 4 don't care bits for the AD5664R, AD5644R, and AD5624R, respectively (see Figure 53, Figure 54, and Figure 55). These data bits are transferred to the DAC register on the falling edge of SCLK 24.

Sync outage

In a normal write sequence, the sync line is held low for at least 24 falling edges of SCLK, and the DAC is updated on 24 falling edges. However, if sync is brought high before the falling edge of 24, then this will act as an interruption to the write sequence. The input shift register is reset and the write sequence is considered invalid. Neither an update of the DAC register contents nor a change in operating mode occurs (see Figure 56).

power-on reset

The AD5624R/AD5644R/AD5664R family includes a power-on reset circuit that controls the output voltage during power-up. The AD5624R/AD5644R/AD5664R digital-to-analog converters output power up to 0V, and the output remains in this position until a valid write sequence to the digital-to-analog converter is performed. This is useful in applications where it is important to know the state of the output of the DAC during power up.

software reset

The AD5624R/AD5644R/AD5664R include a software reset function. Command 101 is reserved for the software reset function (see Table 8). The software reset command contains two reset modes, which are software programmable by setting bit DB0 in the control register.

Table 10 shows how the state of the bits corresponds to the software reset mode of operation of the device. Table 12 shows the contents of the input shift register during the software reset mode of operation.

Power down mode

The AD5624R/AD5644R/AD5664R contain four independent modes of operation. Command 100 is reserved for the power down function (see Table 8). These modes are software programmable by setting two bits in the control register (DB5 and DB4). Table 11 shows how the state of the bits corresponds to the operating mode of the device. All DACs (DAC D to DAC A) can be turned off to the selected mode by setting the corresponding four bits (DB3, DB2, DB1 and DB0) to 1.

By executing the same command 100, any combination of dacs can be started by setting the bits (DB5 and DB4) to normal operating mode. To select the combination of DAC channels to power up, set the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. The contents of the input shift register during power-down/power-up operation are shown in Table 13.

When bit DB5 and bit DB4 are set to 0, the part operates normally at 5v and its normal power consumption is 450 microamps. However, the supply current drops to 480na at 5v (200na at 3v) for the three power down modes. Not only does the supply current drop, but the output stage also switches from inside the amplifier's output to a network of resistors of known value. This allows the output impedance of the component to be known when the component is in power down mode. The output can be internally connected to GND through a 1kΩ resistor, or left open (tri-stated) as shown in Figure 57.

When power-down mode is activated, the bias generator, output amplifier, resistor string, and other associated linear circuits are turned off. However, when powered down, the contents of the DAC registers are not affected. For VDD=5 V and VDD=3 V, the time to exit power down is typically 4 microseconds (see Figure 40).

LDAC function

The AD5624R/AD5644R/AD5664R DACs have a two-buffered interface consisting of two sets of registers: the input register and the DAC register. The input registers are connected directly to the input shift registers, and the digital code is transferred to the associated input register upon completion of a valid write sequence. The DAC register contains the digital code used by the resistor string.

The double-buffered interface is useful if the user needs to update all DAC outputs simultaneously. The user can write to each of the three input registers, then write to the remaining input registers, updating all DAC registers at the same time. Command 010 is reserved for this software LDAC.

Access to the DAC registers is controlled by the LDAC function. The LDAC register contains two modes of operation for each DAC channel. The DAC channel is selected by setting bits in the 4-bit LDAC register (DB3, DB2, DB1, and DB0). Command 110 is reserved for setting the LDAC register. When the LDAC bit register is set low, the corresponding DAC register is latched and the input register can change state without affecting the contents of the DAC register. However, when the LDAC bit register is set high, the DAC registers become transparent and the contents of the input registers are transferred to them on the falling edge of the 24 SCLK pulses. This is equivalent to pinning the LDAC hardware pin permanently low for the selected DAC channel (i.e. synchronous update mode). See Table 14 for the LDAC register operating modes. During the LDAC register set command, the contents of the input shift register are shown in Table 16.

This flexibility is useful in applications where the user wants to update selected channels at the same time, while other channels are updated synchronously.

Internal reference settings

By default, the on-chip reference is turned off at power-up. This reference can be turned on or off by setting software programmable bit DB0 in the control register. Table 15 shows how the state of the bits corresponds to the operating mode. Command 111 is reserved for setting internal references (see Table 8). Table 16 shows how the state of the bits in the input shift register corresponds to the operating mode of the device during internal reference setup.

Microprocessor interface

AD5624R/AD5644R/AD5664R to Blackfin ADSP-BF53x Interface

Figure 58 shows the serial interface between the AD5624R/AD5644R/AD5664R and the Blackfin® ADSP-BF53x microprocessors. The ADSP-BF53x processor family includes two dual-channel synchronous serial ports SPORT1 and SPORT0 for serial and multiprocessor communications. Use SPORT0 to connect to the AD5624R/AD5644R/AD5664R, the interface is set up so that DT0PRI drives the DIN pins of the AD5624R/AD5644R/AD5664R and TSCLK0 drives the SCLK of the part. Synchronization is driven by TFS0.

AD5624R/AD5644R/AD5664R to 68HC11/68L11 Interface

Figure 59 shows the serial interface between the AD5624R/AD5644R/AD5664R and the 68HC11/68L11 microcontroller. The SCK of the 68HC11/68L11 drives the SCLK of the AD5624R/AD5644R/AD5664R, while the MOSI output drives the serial data line of the DAC.

The sync signal comes from the port line (PC7). The setup condition for correct operation of this interface is that the 68HC11/68L11 is configured with its CPOL bit set to 0 and its CPHA bit set to 1. When data is being transferred to the DAC, the sync line is taken low (PC7). When the 68HC11/68L11 is configured as described above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11/68L11 is transferred in 8-bit bytes with only 8 falling clock edges during the transfer cycle. The data MSB is transferred first. To load data into the AD5624R/AD5644R/AD5664R, after the first 8 bits have been transferred, PC7 is held low and a second serial write to the DAC is performed; at the end of the process, PC7 is taken high.

AD5624R/AD5644R/AD5664R to 80C51/80L51 Interface

Figure 60 shows the serial interface between the AD5624R/AD5644R/AD5664R and the 80C51/80L51 microcontroller. The interface setup is that the TxD of the 80C51/80L51 drives the SCLK of the AD5624R/AD5644R/AD5664R, and the RxD drives the serial data line of the part. Synchronization signals come from bit-programmable pins on the port. In this case, use port line P3.3.

P3.3 is taken low when data is being transferred to the AD5624R/AD5644R/AD5664R. The 80C51/80L51 only transmits data in 8-bit bytes; therefore, only 8 falling clock edges occur during the transmit cycle. To load data into the DAC, P3.3 is held low after the first 8 bits have been sent and a second write cycle is initiated to send the second byte of data. P3.3 rises after this cycle is completed. The 80C51/80L51 outputs serial data in LSB first format. The AD5624R/AD5644R/AD5664R must receive data with the MSB first. The 80C51/80L51 transfer routines should take this into account.

AD5624R/AD5644R/AD5664R to Microwire Interface

Figure 61 shows the interface between the AD5624R/AD5644R/AD5664R and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5624R/AD5644R/AD5664R on the rising edge of SK.

application information

Use the reference as a power source

AD5624R/AD5644R/AD5664R

Since the supply current required by the AD5624R/AD5644R/AD5664R is extremely low, another option is to use a voltage reference to supply the required voltage to the part (see Figure 62). This is especially useful if the power supply is noisy, or if the system supply voltage is not 5V or 3V, such as 15V. The voltage reference outputs the regulated supply voltage for the AD5624R/AD5644R/AD5664R (see Figure 60). If a low dropout REF195 is used, it must supply 450 µA to the AD5624R/AD5644R/AD5664R with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply current to the load. The total current required (with a 5 kΩ load output on the DAC) is: 450 μA + (5 V/5 kΩ) = 1.45 mA

The load regulation of the REF195 is typically 2ppm/mA, resulting in a 2.9ppm (14.5µV) error for a 1.45ma current. This corresponds to a 0.191 LSB error.

Bipolar Operation Using the AD5624R/AD5644R/AD5664R

The AD5624R/AD5644R/AD5664R are designed for single-supply operation, but a bipolar output range can also be achieved using the circuit in Figure 63. The output voltage range of this circuit is ±5 V. Using the AD820 or OP295 as the output amplifier enables rail-to-rail operation at the output of the amplifier.

The output voltage of any input code can be calculated as follows:

where D represents the input code in decimal (0 to 65536). VDD=5V, R1=R2=10kΩ,

This is an output voltage range of ±5 V, 0x0000 corresponds to -5 V output and 0xFFFF corresponds to +5 V output.

Using AD5624R/AD5644R/AD5664R with Galvanically Isolated Interface

In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the control circuit from any dangerous common-mode voltages that may be present in the area where the DAC operates. Isocouplers provide isolation in excess of 3 kV. The AD5624R/AD5644R/AD5664R use a 3-wire serial logic interface, so the ADuM130x 3-channel digital isolators provide the required isolation (see Figure 64). The power supply to this part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required by the AD5624R/AD5644R/AD5664R.

Power Bypass and Ground

When accuracy is important in a circuit, it is helpful to carefully consider the power and ground return layout on the board. A printed circuit board containing the AD5624R/AD5644R/AD5664R should have separate analog and digital sections, each with its own board area. If the AD5624R/AD5644R/AD5664R are in a system where other devices require an AGND-to-DGND connection, the connection should only be made at one point. This ground point should be as close as possible to the AD5624R/AD5644R/AD5664R. The power supplies to the AD5624R/AD5644R/AD5664R should be bypassed with 10µF and 0.1µF capacitors. Capacitors should be placed as close to the device as possible, ideally a 0.1µF capacitor should be placed close to the device. The 10µF capacitors are of the tantalum bead type. 0.1µF capacitors must have low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic capacitors. This 0.1µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents generated by internal logic switches.

The power cord itself should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power cord. Clocks and other fast switching digital signals should be shielded from the rest of the board by digital ground. Avoid crossover of digital and analog signals as much as possible. When the traces cross on opposite sides of the board, make sure they run at right angles to each other to reduce the effect of feedthrough through the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane, and the signal traces are placed on the solder side. However, this is not always possible with 2-layer boards.

Dimensions