The ISL 6564A is a control microprocessor core voltage regulator that drives up to 4 synchronous rectified buck channels. It features a bandwidth control loop that provides optimal response to load transients. Switching frequencies up to 1.5MHz per phase, ISL6564A based voltage regulators require minimal components and PCB area in DC/DC converter applications. The ISL6564A utilizes a patented inductive current-measurement on-resistance voltage technology that outputs low mosfet or DCR rDS(on) inductances across their conduction intervals. Current sensing provides the signals needed for accurate droop, channel current balancing, and overcurrent protection. A unity gain differential amplifier is provided for remote voltage sensing. Any potential difference between remotes uses a remote amplifier. Eliminate ground differences to improve adjustment and protection accuracy. A threshold-sensitive enable input can be used to precisely coordinate the startup of the ISL6564A with any other voltage rail. Dynamic Video 8482 ; technology allows seamless real-time video changes. Offset pins allow precise voltage offset settings independent of the video settings. The 6564A island uses a 5V bias and has a built-in shunt regulator for a 12V bias using only a small external limiting resistor.

feature

Precision multi-phase iron core voltage regulation-differential remote sensing voltage-system accuracy ±0.5%-adjustable reference voltage offset

Accurate rDS(on) or DCR Current Sensing - Accurate Loadline Programming - Accurate Channel Current Balancing - Differential Current Sensing - Low Cost, Lossless Current Sensing

Internal Shunt Regulator for 5V or 12V Bias

Microprocessor Voltage Identification Input - Self-Clocked Dynamic Video™ Control Technology - 6-Bit Video Input - 0.525V to 1.300V in 12.5mV Steps

Power Threshold Sensitive Enable Function Sequence Control

overcurrent protection

Overvoltage protection - no additional external components required - OVP pin to actuate the crowbar device

1, 2, 3 or 4 phase operation

Operating frequency up to 1.5MHz per phase (>6MHz ripple) QFN package - JEDEC PUB95 MO-220 QFN compliant - No potential customers for four-story apartment - Product overview - QFN near chip scale package area; improved PCB efficiency, thinner profile provides no Lead plus annealing (RoHS compliant)

Absolute Maximum Ratings

Supply voltage, VCC. +5.5V

Input and output voltages (except OVP). Ground -0.3V to VCC+0.3V

Overvoltage. +15V

mannequin. >4kV

ESD (machine model). >300V

ESD (charging unit model). >2kV

operating conditions

Supply Voltage, VCC (5V Bias Mode, Note 3). +5V±5%

Ambient temperature (ISL6564ACRZ). 0°C to +70°C

Ambient temperature (ISL6564AIRZ). -40°C to +85°C

Hot information

Thermal resistance θJA (°C/W) θJC (°C/W)

QFN package (Note 1, 2). 32 3.5

maximum junction temperature. +150 degrees Celsius

Maximum storage temperature range. -65°C to +150°C

Maximum lead temperature (10s for soldering). +300 degrees Celsius

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation of the device under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

1. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct connect" characteristics.

2. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Electrical Specifications Operating Conditions: VCC=5V or ICC<25mA (Note 3). unless otherwise specified.

Electrical Specifications Operating Conditions: VCC=5V or ICC<25mA (Note 3). unless otherwise specified. (continued)

notes:

3. When using the internal shunt regulator, VCC is clamped to 6.2V (max). Current must be limited to 25mA or less.

4. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

5. Guaranteed by design.

6. During soft start, VDAC rises from 0 to VID. Overvoltage trip level is higher of 1.5V and VDAC+0.2V

Function pin description

Provides all the power needed to operate the chip. This occurs when the voltage on this pin exceeds the rising POR threshold and the voltage on this pin falls below the falling POR threshold. Connect this pin directly to the +5V supply or through a series 300Ω resistor to the +12V supply. Ground Bias and reference ground for ICs. EN This pin is the controller. Provides a method for synchronizing the power-up of the controller and MOSFET driver chips through appropriate resistor dividers. When the EN voltage is higher than 1.29V, the ISL6564A activation depends on the status of ENLL, internal POR and pending fault status. Driving below 1.16V will clear all fault conditions and charge the ISL6564A into a soft-start state when re-enabled.

This pin is the logic level enable input of the controller. Asserted to logic high, ISL6564A activation depends on the state of EN, internal POR, VID input, and pending fault status. Removing ENLL will clear all fault conditions and re-charge the ISL6564A to soft start. When floating, the inner ring pin is pulled to a higher position with a typical voltage of 1.15V. The Four Seasons resistor RT from FS to ground will set the switching frequency. There is an inverse relationship between resistor value and switching frequency. See Figure 20 and Equation 30. Video 5, Video 4, Video 3, Video 2, Video 1 and Video 0 are reference voltages for output regulation. Connecting these pins turns on sinking outputs (with or without external pull-ups) with resistors or active pull-up outputs. VID5-VID0 have 45µA when the voltage is higher than logic high. These inputs can be as high as VCC+0.3V.

VDIFF, VSEN, and RGND VSEN and RGND form a precision differential telemetry amplifier. This amplifier converts the differential remote output to a single-ended voltage referenced to local ground. VDIFF is the output of the amplifier and the input to the conditioning and protection circuits. Connect VSEN and RGND to the remote's sense pin mount. FB and COMP invert the input and output of the error amplifier, respectively. FB is connected to VDIFF through a resistor. A current pin proportional to the output current exists on the negative FB. A properly sized resistor load line (drop) between VDIFF and the FB group. The droop scaling factor is determined by the ratio of the ISEN resistance to the low MOSFET rDS(ON). COMP is tied to FB with no DC connection through an external RC network to compensate the regulator.

The DAC and REFDAC output pins are precision internal DAC references. The REF input pin is the error amplifier. In a typical application, a 1kΩ, 1% resistor is used to generate an accurate offset voltage between the DAC and REF. This voltage is proportional to the offset current determined by the offset resistor of OFS to ground or VCC. One uses a capacitor between REF and ground to smooth voltage transitions in Dynamic Video™ operation. PWM1, PWM2, PWM3, PWM4 pulse width modulation output. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels consists of PWM3 and password 4. Leave PWM4 unconnected and connect PWM3 to VCC to configure for 2-phase operation. Connect PWM4 to VCC to configure for three-phase operation. Connect PWM4 and PWM3 for single-phase operation high

ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+, ISEN4+- ISEN+ and ISEN- pins are independent differential amplifiers. Use sensed current for channel balance, protection, and regulation. Inactive channels should have their respective sense inputs left open (e.g., open ISEN4+ for three-phase operation. For DCR sensing, connect each ISEN-pin to a node between the RC sense elements. Tie the ISEN+ pin to another The sense capacitor at one end, through a resistor, rises. The voltage across the capacitor is sensed versus the inductor current. The sense current versus the output current, scaled by the DCR of the inductor, divided by the rise. When configured for rDS(ON) current sensing, ISEN1-, The ISEN2-, ISEN3-, and ISEN4- pins are grounded at the lower MOSFET source. The ISEN1+, ISEN2+, ISEN3+, and ISEN4+ pins are pinned to virtual ground so that the resistor connected between them, and the associated low MOSFET, will carry a The current is proportional to the current flowing through that channel. This current is determined by the resulting negative voltage across the lower MOSFET's rDS(ON), which is the channel's current scaled by rDS(ON).

PGOOD is used as an indication of the end of the soft-start microprocessor specification. This is an exposed logic low impedance output until soft-start is complete. once the undervoltage point is reached. The OFS pin provides a way to program a DC offset current that produces a DC offset voltage at the reference input. Bias current is through an external resistor and precision internal voltage reference. Polarity Select the offset by connecting a resistor to GND or VCC. For no offset, the OFS pins should remain unterminated. Overvoltage protection pin. This pin is pulled to VCC to lock when an overvoltage condition is detected. Connect this pin to slave VIN or ground to prevent damage to the load. This pin can be used with external resistors for voltages up to 15V above VCC. However, it can only be pulled low when VCC is above 2V.

Driver enable pin. This pin can be used to enable drivers with enable pins like ISL6605 or ISL6608. If the ISL6564A is used with the Intersil ISL6612 driver, then this pin must not be used. IDROOP and IOUT IDROOP and IOUT are the output pins that sense the average value of the channel current proportional to the load current. They are designed for flexible application purposes. In applications that do not require a load line, leave the IDROOP pin open. In an application that requires a load line, connect the IDROOP pin to FB so that the average sensed current will flow through a resistor between FB and VDIFF creating a voltage drop proportional to the load current. IOUT is usually used for load current indication.

operate

Multiphase Power Conversion

The microprocessor load current profile has been changed to point out that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing single-phase converters are both cost-effective and thermally feasible, forcing a move to multi-phase cost-saving approaches. The ISL6564A controller helps reduce the minimum output components by integrating important functions and requirements. Blocks 3, 4, 5, 6, and 7 on the page provide a top-level view of the polyphase power conversion using the ISL6564A controller.

The switching of each channel in the polyphase converter is

Symmetrical out-of-phase channels with each other. In a three-phase converter, each channel switches 1/3 of the loop after the previous channel, while tracking the channel. Therefore, the combined ripple frequency of the three-phase converter is higher than the ripple frequency of any one phase. Furthermore, the peak-to-peak amplitude reduction of the combined inductor current is proportional to the number of phases (Equations 1 and 2). Ripple frequency increases and ripple amplitude decreases. Designers can use less inductance per channel and lower total output capacitance specifications for any performance. Figure 1 illustrates the frequency of the multiplication effect of the output ripple. The three channel currents (IL1, IL2 and IL3) are combined to form the AC ripple current and the DC load current. The ripple of the ripple component is the frequency of the current in each channel. Each PWM pulse in the previous stage. The peak-to-peak current per phase is about 7A, and the DC component of the inductor current combines to deliver the goods. To understand the ripple current amplitude in a polyphase circuit, examine the peak-to-peak inductor current representing a single channel.

In Equation 1, VIN and VOUT are the input and output voltages, L is the single-channel inductance value, and fS is the switching frequency.

The output capacitor conducts the inductor current. In the case of multiphase converters the capacitive current is per individual channel. Combine Equation 1 with the expression for the peak-to-peak current after summing N symmetrically phase-shifted inductor current Equation 2. The peak-to-peak ripple current is reduced by an amount proportional to the number of channels. The output voltage ripple is a function of capacitance, equivalent series resistance (ESR) and inductor ripple current. Reducing inductor ripple current allows designers to use fewer or less expensive output capacitors.

Another benefit of interleaving is reducing input ripple current. The input capacitor section is determined by the maximum input ripple current. Multiphase topologies can increase overall system cost and scale by reducing input ripple, enabling designers to reduce the cost of input capacitors. The example in Figure 2 demonstrates the current total input ripple current into a three-phase converter. The converter shown in Figure 2 delivers 36A from a 12V input to a 1.5V load. The rms input capacitor current is 5.9A. Compare this to a single-phase converter for the same buck, which is 12V to 1.5V at 36A. The single-phase converter has 11.9A rms input capacitor current. Single-phase converters must use an input capacitor bank with twice the rms current capacity equivalent to three-phase converters. Figures 21, 22 and 23 in the section titled "Input Capacitors" selection can be used to determine the input capacitor RMS based on load current, duty cycle and channel. in determining the optimal input capacitance solution. Figure 24 shows a phase input capacitor rms current comparison.

PWM operation

The timing of each converter branch is determined by the active channel. The default channel setting of the ISL6564A is 4. A switching cycle is defined as the time between the PWM1 pulse termination signals. The pulse termination signal is an internally generated clock signal that triggers the falling edge of PWM1. The cycle time pulse termination signal is opposite to the switch at the frequency set by a resistor between the FS pin and ground. When commanded by the clock signal, the PWM output of channel 1 goes low at the beginning of each cycle. The PWM1 transition signals the Channel 1 MOSFET driver to turn off the Channel 1 MOSFET and turn on the Channel 1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse ends 1/4 of a period after PWM1. After PWM2, the output of PWM3 is 1/4 of a cycle again. PWM4 terminates another 1/4 of the cycle after PWM3. If PWM3 is connected to VCC, the PWM2 pulse is terminated after 1/2 cycle when dual channel operation is selected. Connect PWM4 to VCC to select three-channel operation at pulse termination intervals of 1/3 cycle increments. Connect PWM3 and PWM4 to VCC to select single channel operation. Once the PWM signal transitions low, it will remain low for a minimum of 1/3 cycle. Forced off-time requirements ensure accurate current samples. Current sensing is described in the next section. When the forced off time expires, the PWM output will be enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the sawtooth ramp as shown in Figure 7. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output is highly transitioned. The MOSFET driver detects the state of the PWM signal and turns off the MOSFET above it synchronously. The PWM signal starts the next cycle by triggering a low PWM signal at the end of the pulse signal

Current sampling

During the forced off time after the PWM transitions low, the associated channel current sense amplifier uses the ISEN input to reproduce the inductor current, IL. No matter what the current method of sensing is to induce current, Ethan, it's just inductive current. Consistent with the falling edge of the pulse width modulation signal, the sampling and holding circuit sampling is shown in Figure 3. The sample window hold time, tHOLD, is fixed and equal to 1/3 of the switching period, tSW Therefore, the sampling current In and the output current are held for one switching period. The sample current is used for current balancing, load line regulation and overcurrent protection.

Current sensing

The ISL6564A supports inductive DCR sensing, MOSFETrDS(on) sensing, or resistive sensing techniques. This internal circuit, shown in Figures 4, 5 and 6, represents the n-channel of the n-channel converter. This circuit is repeated for each channel in the converter, but the pins cannot be activated based on the state of PWM3 and PWM4, as described in the "Pulse Width Modulation Operation" section. Inductive DCR Inductive inductor windings have resistance (direct current resistance) parameters measured by DCR. Think of the inductive DCR as a separate concentrated quantity, as shown in Figure 4. This channel current IL flowing through the inductor also passes through the DCR. Equation 4 shows the equivalent voltage across the s-domain inductance VL.

The DCR voltage is extracted through a simple RC network of inductors, as shown in Figure 4. The voltage VC across the capacitor can be shown to be proportional to the channel current IL, see equation

If the RC network component is selected, the RC time constant matches the inductor L/DCR time constant, and VC equals the DCR.

The capacitor voltage VC then rises across the sense resistor. The current through the sense resistor is proportional to the inductor current. Equation 6 shows the proportional current ISEN of the channel current to the sense current, the selection of the inductor and the DCR driven by the value of the sense resistor.

DCR varies with temperature, so a positive temperature sensor should choose a coefficient of (PTC) resistor resistance to rise.

Resistive sensing

If DCR sensing is not used, independent current sensing resistors in series with each output inductor can serve as the sensing element (see Figure 5). This technique is accurate, but due to adding lossy elements directly in the output path.

The MOSFET rDS(ON) sensing controller can also sample the voltage through the lower MOSFET rDS(ON) (see Figure 6). The amplifier ground reference connects the ISEN input to the source MOSFET below. ISEN+ rises through a resistor. The rising voltage is equivalent to the voltage drop across the rDS(ON) of the lower MOSFET when it is conducting. The current into the Ethan + pin is proportional to the channel current IL. The current is sampled and held after sufficient settling time. The sampling current In is used for channel current balance, load line regulation, and overcurrent protection. From Figure 6, Equation 7 for ISEN is derived.

where IL is the channel current. Since the MOSFET rDS(on) increases with temperature, the PTC resistor should be chosen to compensate for this change.

Channel current balance

The sum of the sampled currents in each active channel divided by the number of active channels. The resulting circulating average current, IAVG, provides a measure of the inverter's total load current demand during each switching cycle. Channel current balancing is achieved by comparing the sampled currents of each channel to achieve a circulating average current and adjusting the pulse width of each channel according to the error. Intersil's patented current balance method, shown in Figure 7, represents the error correction for channel 1. At this figure, the cycle-averaged current and channel 1 are sampled, I1, to create the error signal IER. This filtered error signal is modified by VCOMP to correct any imbalance and drive the IER towards zero. The same error signal correction method applies to each active channel.

Channel current balance is a key advantage of multiphase operation to achieve thermal balance. The heat generated is downconverted across multiple devices and larger areas. Designers avoided the complexity of driving multiple parallel mosfets, as well as the expense of using thermal sinks and non-standard magnetic materials. The voltage regulation integrated compensation network shown in Figure 8 ensures that the steady-state error of the output voltage is limited to the error of the reference voltage (offset error of the output and OFS current sources, telemetry and error amplifiers. Intersil specifies that the guaranteed tolerance of the ISL6564A includes these elements of Combination tolerance. The output of the error amplifier VCOMP and the sawtooth wave that produces the pulse width modulated signal. The pulse width modulated signal controls the internal MOSFET driver and regulates the converter output to the specified reference voltage. The internal and external circuit voltage regulation of the control is shown in Figure 8 shown.

The ISL6564A integrates an internal differential remote sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output relative to the voltage at the local controller ground reference to obtain a more accurate sensed output method voltage. Connect the microprocessor sense pins to the non-inverting input VSEN and the inverting input RGND of the remote control amplifier. The remote sense output, VDIFF, is through an external resistor. A digital-to-analog converter (DAC) generates a reference signal voltage based on the logic signal state on pin VID4 through Section 12.5. The DAC decodes a 6-bit logic signal (VID) to one of the discrete voltages shown in Table 1. Each VID input provides a 45µA pull-up to an internal 2.5V supply for open-drain outputs. The pull-up current is decremented to zero above the logic threshold to protect voltage-sensitive output devices. External pull-up resistors if the case leaks into the drive device is greater than 45µA. Load Line Regulation Some microprocessor manufacturers require precise control of the output resistance. This dependence on output load voltage and current is often referred to as "drop" or "load line" regulation. By adding well-controlled output impedance, the output voltage can be efficiently regulated in the direction of the load line required by these manufacturers.