The ISL6445 is a high-performance dual-output PWM for converting wall adapters, batteries, or supplying network intermediate bus DC input power supply voltages to systems required for various applications. Each output is regulated to 0.8V synchronously 180o out of phase to reduce RMS input current and ripple voltage. The ISL6445 has various protection functions. An adjustable overcurrent protection circuit monitors the output current by sensing the voltage drop across the lower MOSFET. Hiccup mode overcurrent operation protects damaged DC/DC components from overload/short circuit conditions during output. Each PWM has an independent logic level shutdown input (SD1 and SD2). When the soft-start is complete, a PGOOD signal is issued on both PWM controllers whose outputs are at setpoint. Thermal shutdown circuitry shuts down the device if the junction temperature exceeds +150°C.

feature

Wide input supply voltage range -5.6V to 24V -4.5V to 5.6V

Two independently programmable output voltages

On-off level. 1.4 MHz

Out-of-phase PWM controller operation - reduces required input capacitance and power supply inductive loads

No External Current Sense Resistor - Use Lower MOSFET's rDS(On)

Programmable soft start

Extensive circuit protection functions - Pugood - UV radiation - over current - over temperature - independent shutdown of two PWMs

Excellent Dynamic Response - Current Mode Control Voltage Feedforward

Lead-free plus annealed (RoHS compliant) available

application

Power supply with two outputs

xDSL modem/router

DSP, ASIC and FPGA power supplies

set top box

Dual Output Power Supplies for Digital Signal Processors, Memory, Logic, μP Cores and I/O Telecom Systems

Absolute Maximum Ratings Thermal Information

Supply voltage (VCC_5V pin). -0.3V to +7V

Input voltage (VIN pin). +27V

BOOT1, 2 and UGATE1, 2. +35V

Stages 1, 2 and ISEN1, 2. +27V

BOOT1, 2 are relative to stage 1, 2. +6.5V

UGATE1, 2. (1 phase, 2-0.3V) to (BOOT1, 2+0.3V)

Thermal Resistance (Typical) θJA (°C/Watt)

24-lead QSOP (Note 1). 85

Maximum connection temperature (plastic packaging). -55°C to 150°C

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius

temperature range. -40°C to 85°C

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air.

Operating conditions recommended by electrical codes unless otherwise stated. Refer to the block diagram and typical application schematic. VIN = 5.6V to 24V, or VIN = 5V ±10%, TI = -40°C to 85°C (Note 3), typ. TA = 25°C

Operating conditions recommended by electrical codes unless otherwise stated. Refer to the block diagram and typical application schematic. VIN = 5.6V to 24V, or VIN = 5V ± 10%, TI = -40°C to 85°C (Note 3), typ. TA = 25°C (continued)

notes:

2. Specifications at -40°C and 85°C are guaranteed by design, not production tested.

3. In normal operation, the VCC_5V pin provides a voltage of 5V that can output 60mA (min) when the device provides voltage on the Vehicle Identification Number (VIN) pin. When the VCC_5V pin is used as a 5V power supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the VCC_5V pin. (See the Pin Descriptions section for details.)

4. This is the total off current when VIN=VCC_5V=PVCC=5V.

5. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current.

6. Peak-to-peak sawtooth amplitude is production tested at 12V only; at 5V, this parameter is guaranteed by design.

7. Guaranteed by design; not production tested.

8. Not production tested; guaranteed by characterization only.

9. Guaranteed by design. A full-scale current of 32 µA is recommended for optimal current sample and hold operation. Check out the compensation section below the feedback loop.

Typical Performance Curve (from ISL6445EVAL1 Evaluation Committee)

Typical Performance Curves (continued) (from ISL6445EVAL1 Evaluation Committee)

Pin Description

BOOT2, BOOT1 - These pins power the MOSFETs above the drivers for each PWM converter. Connect this pin to the bootstrap capacitor and bootstrap diode. The anode of the bootstrap diode is connected to the VCC_5V pin. UGATE2, UGATE1 - These pins are for upper MOSFETs. Phase 2, Phase 1 - These pins connect to headers for the upper mosfet source, the output filter inductor and the drain of the lower mosfet source MOSFETs. LGATE2, LGATE1 - These pins are the lower MOSFETs. PGND - This pin is the lower gate driver for PWM1 and PWM2. This pin should be connected to the lower mosfet source as well as the (-) terminal of the external input capacitor. FB2, FB1 - These pins connect to the feedback resistor divider and provide the voltage feedback signal to the respective controller. They set the output voltage of the converter. In addition, the PGOOD circuit uses these inputs to monitor the output voltage state. ISEN2, ISEN1 - These pins are used to monitor the low MOSFET voltage drop of voltage current loop feedback and overcurrent protection.

PGOOD - This is an open drain logic output used to indicate the state of the output voltage. when either of the two PWM outputs are not at their respective nominal voltages. SGND - This is the small signal ground, the two share the controller and must be routed separately from the high current ground (PGND). All voltage levels are used on this pin. Connect additional SGND pins to this pin. VIN - Use this pin to provide external power to the device. The supply voltage range is 5.6V to 24V, 5V ±10% operation, connect this pin to VCC5. VCC5 - This pin is the internal +5V linear output regulator. This output provides the bias side gate driver for the IC and the side gate driver for the external start-up circuit. The IC can be powered directly by a 5V (±10%) supply on this pin. When used as a 5V power input, this pin must be externally connected to the VIN. The VCC5 pin must always be disconnected from the power supply ground. A minimum 4.7µF ceramic capacitor is recommended, very close to the pin. Bias - This pin must be connected directly to VCC5. SS1, SS2 - These pins provide the soft-start function for their respective PWM controllers. When the chip starts up a regulated 5µA pull-up current source charges the capacitor from this pin to ground. Error Amplifier When the voltage is turned on, the reference voltage is gradually raised from 0 to 0.8V on the soft-start pin from 0 to 0.8V. SD1, SD2 - These pins provide the respective PWM outputs for the enable/disable function. When this pin is floating or pulled high, when the pin is pulled low. OCSET2, OCSET1 - Overcurrent threshold for each pulse width modulated resistor from this pin to the ground group.

Function description

General Instructions

The ISL6445 integrates two synchronous control circuit buck converters. The two sync blocks run 180 degrees out of phase to drastically reduce input ripple and thus reduce input filter requirements. The chip has four control lines (SS1, SD1, SS2, and SD2) that provide independent control outputs for each sync buck. The PWM controller uses 1.4 MHz. Current Mode Control Scheme with Input The voltage feed-forward ramp input of the modulator provides excellent rejection of input voltage variations and provides simplified loop compensation. Internal 5V Linear Regulator (VCC5) All ISL6445 functions are powered internally by an on-chip, low power, +5V regulator. The maximum regulator input voltage is 24 volts. Bypass regulator output (VCC5) 4.7µF capacitor to ground. The voltage drop of this LDO is usually 600mV, so when VIN is greater than 5.6V, VCC5V is +5V. The ISL6445 also employs an undervoltage lockout circuit that shuts down both regulators when VCC5 is below 4.4V. The internal LDO can provide over 60mA to power the IC, power the low-side gate drivers, charge the external boot capacitors and provide a small external load. With a large FET on drive, little or no regulator current is available for external loads.

For example, a large FET with 30nC total gate charge requires 30nC x 1.4MHz = 42mA. So a total of four FETs require 36mA. The internal bias is 3mA and the external +5V supply is about 20mA. Also, at higher input voltages and larger FETs, the power dissipation inside 5V will increase. Excessive dissipation must be avoided across this regulator to prevent the connection from rising in temperature. Larger fets can be used with 5V ±10% input applications. The thermal overload protection circuit will trigger if the VCC5 output is shorted. Connect VCC5 to VIN for 5V±10% input applications

soft start operation

When the soft-start starts up due to the 5µA current of the input external capacitor. The output voltage follows the soft-start voltage. When the SS pin voltage reaches 0.8V, the output voltage for the enabled PWM channel reaches the regulation point and the soft-start pin voltage continues to rise. At this point the PGOOD and fault circuits are enabled. This completes the soft-start sequence. Any further rise in the SS pin voltage does not affect the output voltage. By changing the soft-start capacitor, the main output at startup can be provided. The soft-start time can be obtained from the following equation:

An optional soft-start capacitor provides start-up tracking for two PWM outputs. This can be achieved by choosing the soft-start capacitors so that the soft-start capacitor ratios are equal to the respective PWM output voltage ratios. For example, if I use PWM1=1.2V and PWM2=3.3V then the soft-start capacitor ratio should be, CSS1/CSS1=1.2/3.3=0.364. Figure 14 shows the soft-start waveforms CSS1=0.01µF and CSS2=0.027µF.

OUTPUT VOLTAGE PROGRAMMING A resistive divider from the output to ground sets the output voltage for either PWM channel. The center point voltage divider should be connected to the FBx pin. The output voltage value is determined by the following formula.

where R1 is the top resistor of the feedback divider network and R2 is the resistor from FB1 or FB2 to ground.

Out-of-phase operation

The two PWM controllers in the ISL6445 operate at 180 degrees phase to reduce input ripple current. This reduces input capacitor ripple current requirements, reduces power supply induced noise, and improves EMI. This effectively helps reduce component cost, save board space and reduce EMI. The dual power supplies usually work in phase and turn on the FET at the same time. The input capacitor must support the instantaneous current requirements of both controlled simultaneously, resulting in increased voltage and current ripple. The higher rms ripple current reduces the efficiency of the input capacitor due to power losses caused by electroslag remelting. This typically requires lower ESR shunt capacitors to reduce input voltage ripple ESR related losses, or to meet the required ripple current rating. In the case of dual synchronous out-of-phase operation, the high-side mosfet of the ISL6445 is turned on 180 degrees out of phase. The long overlap of the instantaneous input current peaks of the two regulators results in an rms ripple current that reduces the input voltage ripple. This reduces the required input capacitor ripple current rating, allows for fewer or less expensive capacitors, and reduces shielding EMI requirements. A typical operating curve shows simultaneous 180-degree out-of-phase operation.

Input voltage range

The ISL6445 is designed to operate from input power from 4.5V to 24V. However, the input voltage range effectively limits the maximum duty cycle available (DMAX=93%).

Vd1 = Sum of parasitic voltage drops in the inductor discharge path, including lower FET, inductor and PC.

Vd2 = the sum of the voltage drops in the charging path, including the upper FET, inductor, and PC board resistance. The maximum input voltage and minimum output voltage are limited by the minimum turn-on time (tons (minutes)).

gate control logic

The gate control logic converts the generated PWM signal to provide an amplified, level-shifted gate drive signal through the guard firing. Gatekeeper has a range of circuit operating conditions that help optimize integrated circuit performance. As MOSFET switching times vary widely depending on the type and input voltage, the gate control logic provides adaptive dead time by monitoring the upper and upper low MOSFETs. The penetration control logic provides a 20ns dead time to ensure that the upper and lower MOSFETs do not turn on at the same time and cause a shoot-through condition. Gate Driver The low-side gate driver is provided by VCC5 and provides a peak sink current of 400 mA. The high-side gate driver can also draw 400mA. The gate drive voltage for the upper N-channel MOSFET is driven by the flying capacitor to start the circuit. The boot capacitor is connected from the boot pin of the phase node for the high-side MOSFET driver. To limit peak currents in the IC, external resistors can be placed between the molar pins and the gate of the external MOSFET. This small series of resistors also dampens any oscillating circuit board parasitic inductances caused by resonance to the slot FET's gate-to-drain capacitance.

At startup, the low-side MOSFET turns on and forces phase-to-ground in order to charge the bootstrap capacitor to 5 volts. After the low-side MOSFET turns off, the high-side MOSFET boots through and wears off. This provides the necessary gate-to-source voltage to turn on the upper MOSFET, an action that boosts the 5V gate drive signal above the VIN. Current driving the upper MOSFET requires a 5V regulator from the internal. Protection Circuit The inverter output is monitored and protected against overload, short circuit and undervoltage conditions. A sustained overload on one output sets PGOOD low to initiate hiccup mode. Both PWM controllers use the lower MOSFET on-resistance rDS(on) to monitor the current in the converter. Compares the detected voltage drop with the threshold set by the resistor from the OCSETx pin to ground.

where IOC is the desired overcurrent protection threshold and RCS is the value of the current sense resistor connected to the Ethan pin. If the lower MOSFET current exceeds the overcurrent threshold, an overcurrent condition is detected. If an overcurrent is detected for two consecutive clock cycles, the IC enters a soft-start state by turning off the gate driver and entering hiccup mode. The IC will cycle 2 times trying to soft-start before restarting. The IC will continue to cycle through soft-start until the overcurrent condition is removed. Figure X shows this behavior (figure to be added). Because of the nature of this current sensing technique to accommodate a wide range of rDS(ON) variants, the overcurrent threshold that can be used should represent an overload current of approximately 150% to 180% of the maximum operating current. If more accurate current protection is required combine the current sense resistor with a low MOSFET source.

Selecting RCS to supply 32µA of current is recommended to use a sample and hold circuit, but lower values can be used from 2µA to 100µA. Due to current loop feedback, the modulator has a pole response with a -20dB slope when frequency is determined by load.

where RO is the load resistance and CO is the load capacitance. For this type of modulator, a type 2 compensation circuit is usually sufficient. Figure 16 shows a Type 2 amplifier with its edge current-mode modulator and converter. Type 2 amplifiers, in addition to the origin, have a pole-zero pair, at frequencies between the zero and the pole

Zero frequency, amplifier high frequency gain and modulator gain selected to meet the most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier's high frequency gain. The only task the system designer has to accomplish is to specify that the output filter capacitors place the main pole of the load somewhere below the zero frequency of the amplifier within a decade. There is a phase "boost" of this type due to the pole-to-zero pair. Only when the main load bar is placed too much on the left side of the frequency axis due to excessive output filter capacitance. The ESR zeros in the 1.2kHz to 30kHz range in this case give some additional "boost" stage. Some phase enhancement can also be achieved by connecting capacitor CZ to the value of resistor R1 on top of the voltage divider that sets the output voltage. Please refer to the Output Inductor and Capacitor Selection section for more details. Layout guidelines for successful implementation of ISL6445 based DC/DC converters. The ISL6445 switches at a very high frequency so the conversion time is very short. At these switching frequencies, even the shortest traces have effective impedance. At the same time the peak gate drive current rises significantly in a very short time. The transition speed of current from one device to another can cause voltage spikes across impedance and parasitic circuit elements. These voltage spikes can reduce efficiency, generate electromagnetic interference, and increase device overvoltage stress ringing. Careful component selection and proper PC board layout minimize the magnitude of these voltage spikes.

There are two sets of key components in the DC/DC converter that use the ISL6445. Switching power supply components and small signal components. This switching power supply assembly is a layout angle because they switch a lot so they generate a lot of noise. Critical small-signal components are those that connect to sensitive nodes or supply critical bias currents. One recommends using a multilayer printed circuit board. Layout Considerations

1. Input capacitors, upper FETs, lower FETs, and inductor output capacitors should be placed in the first place. Isolate the ground terminals of the power components on top of these boards adjacent to each other. Place input high frequency decoupling ceramic capacitors for MOSFETs. Make the gate traces shorter and thicker and the parasitic inductance smaller reduces the dv/dt level seen at the lower gate FET when the upper FET is turned on.

2. Use separate ground planes for power ground and small ground signal ground. Connect SGND and PGND together to turn off the IC. don't connect them together

3. The input capacitor, top FET and bottom FET must be as small as possible.

4. Make sure that from the input capacitor to the output inductor and the output capacitor as short as possible, the maximum track width allowed.

5. Place the PWM controller IC close to the lower FET. This LGATE connection should be short and wide. ICs can be best placed on quiet ground. Avoid switching ground loop currents in this area.

6. Place the VCC5 bypass capacitor very close to the IC and connect its ground to the PGND plane.

7. Place the gate drive components boot diode and boot capacitor near the controller IC.

8. The output capacitor should be placed as loaded as possible. Use a short wide copper area to connect the output capacitor to the load to avoid inductance and resistance.

9. Use copper-filled polygons or wide, short traces to connect the connectors on the FETs. Low FET and output inductor. Also keep the phase node connections to the IC short. Do not oversize the copper island phase node unnecessarily. Because the phase nodes are exposed to high dv/dt voltages, stray capacitances formed between these islands and the surrounding lines tend to couple switching noise.

10. Remove all high-speed switching nodes from the control circuit.

11. Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. All small signal ground paths include feedback resistors, current limit setting resistors, and SDx pull-down resistors should be connected to this SGND plane.

12. Make sure the feedback connections to the output capacitors are short and direct.

Parts Selection Guide

MOSFET Considerations

Choosing a logic-level MOSFET for optimum efficiency takes into account the potentially wide input voltage range and output power requirements. Two N-channel MOSFETs are used for each synchronous rectification buck converter PWM1 and PWM2 output. These mosfets should be selected based on the radio data system (on), door power requirements, and thermal management considerations. Power dissipation consists of two loss components; conduction losses and switching losses. These losses are distributed between the upper and lower mosfet according to the duty cycle (see equation below). This conduction loss is the main component of power loss in low mosfet. Only the upper MOSFET has significant switching losses as the lower device turns on and off near zero voltage. The equations assume linear voltage-to-current conversion and do not model the lossy body diode due to reverse recovery of power low MOSFETs.

The large gate charge increases the switching time, tSW, which increases the upper MOSFET switching losses. Ensure that both mosfets are within their maximum junction temperature at high ambient temperature. Calculate temperature rise thermal resistance specification as per package. The internal +5V regulator increases as the input voltage increases. To ensure that the ISL6445 does not overheat select the external mosfet based on the total FET gate charge according to Figure 17. Plots showing different maximum ambient operating temperatures. The power dissipation of the internal LDO comes from the bias current of the chip and the external Mossfetter provided to drive it. This graph uses the recommended maximum operating junction temperature of 125°C and calculates the maximum drive current that can be supplied by the internal LDO based on the die temperature and

Output Capacitor Selection The output capacitor for each output is a unique requirement. In general, the output capacitor should be selected to meet dynamic regulation requirements including ripple voltage and load transients. The selection of the output capacitor also depends on the output inductance, so analysis of the inductance is required to select the output capacitor. One of the parameters limiting a converter's response to load transients is the time it takes for the inductor current to switch to a new level. The ISL6445 will provide a 71% duty cycle for 0% or load transient response. The response time is the transition from the initial current value to the current level of the load's inductor current. During this time the inductor current and transient current levels must be powered by the output capacitor. Minimizing the response time minimizes the required output capacitance. Also, if the load transient rise time is slower than the inductor response time, as in a hard disk drive or CD drive, it reduces the output capacitor requirement. The maximum capacitor value required for the rising step, transient load current inductor response time is

where COUT is the desired output capacitor, LO is the output inductance, ITRAN is the transient load current step, VIN is the input voltage, VO is the output voltage, and DVOUT is the allowable output voltage drop during load transients. High frequency capacitors initially provide transient currents and slow down the rate of change of load seen by bulk capacitors. The bulk filter capacitor value is usually determined by ESR (equivalent series resistance) and rated voltage requirements and actual capacitance requirements. The output voltage ripple is caused by the inductor ripple current and the ESR of the output capacitor

where IL is calculated in the inductor selection section. High frequency decoupling capacitors should be placed as close as possible to the power pins of the load. Be careful not to add inductance to the board layout that might cancel out the effects of these low inductance components. Consult the load manufacturer for circuit specific decoupling requirements. Use only dedicated low ESR capacitor switching regulators for application capacitors at 1.4MHz. In most cases, multiple small electrolytic cell capacitors perform better than a single large capacitor. Output selection stability requires capacitors to be 'ESR zero', fZ, at 1.2kHz and 30kHz. This range is set by an internal, single offset set to zero at 6kHz. The ESR zero can be one side of the internal zero and still contribute to the phase margin of the control loop. So, in summary, the output capacitor must meet three criteria:

1. They must have sufficient bulk capacitance to maintain the output voltage during load transients and the inductor current turns to the load value for short periods of time,

2. The ESR must be low enough to meet the output voltage ripple caused by the required output inductor current, and

3. The ESR zero should be placed in a fairly wide range to provide additional phase margin. The recommended output capacitor value for the ISL6445 is between 150 and 680 µF to meet stability criteria with external compensation. Using aluminum electrolytics, POSCAP or tantalum type capacitors are recommended. Using low ESR ceramic capacitors is possible, but requires more rigorous loop analysis to ensure stability. Output Inductor Selection Output inductors are required for PWM converters. The output selects the inductor to meet the output voltage ripple requirements. The inductor value determines the converter's ripple current and ripple voltage as a function of ripple current and output capacitor ESR. The ripple voltage is given an expression in the capacitor selection section, and the ripple current is approximated by the following equation:

For the ISL6445, use an inductor value between 1 and 3.3µH. Input Capacitors The important parameters for selecting a bulk input capacitor are the voltage rating and the rms current rating. For reliable operation, choose a voltage and current rating higher than the maximum input voltage and maximum rms current required by the circuit. The capacitor voltage rating should be at least 1.5 times higher than the maximum input voltage and a conservative value guideline. AC RMS input current varies with load. The total rms current provided by the input capacitor is:

DC is the duty cycle of each PWM. Depending on the input power and its impedance, most (or all) of this current flows through the input capacitor. Figure 18 shows the out-of-phase operation of the PWM converter. If the converters are operating in phase, the combined rms current is the algebraic sum, which is a larger value as shown. The combined out-of-phase current is the square root of the individual sum of squares reflected current and in-phase current.

Use a hybrid input bypass capacitor to control the voltage ripple on the mosfet. Use ceramic capacitors for high frequency decoupling and bulk capacitors for rms current. Small ceramic capacitors can be placed close to the upper MOSFET to suppress impedance in voltage-induced parasitic circuits. For board designs that allow through-hole components, the Sanyo OS-CON® series offers low ESR and good temperature performance. For surface mount designs, solid tantalum capacitors can be used, but care must be taken regarding capacitor inrush current ratings. These capacitors must be able to handle inrush current when powered up. The TPS series offered by AVX is inrush current test.