feature

At 185 MHz AIN and 250 MSPS, the signal-to-noise ratio is 70.6 dBFS; at 185 MHz AIN and 250 MSPS, SFDR=85 dBc-151.6 dBFS/Hz input noise, 185 MHz, -1 dBFS AIN and 250 ms/sec; Total power consumption: 785 mW at 250 MSPS; 1.8V supply voltage; LVDS (ANSI-644 grade) output; integer 1 to 8 input clock divider (maximum input 625 MHz); sampling rate up to 250 MSPS; IF sampling frequency Up to 400 MHz; internal ADC voltage reference; flexible analog input range; 1.4 V pp to 2.0 V pp (1.75 V pp nominal); ADC clock duty cycle stabilizer; 95 dB channel isolation/crosstalk; serial port control ; Energy saving power-down mode.

application

Communication; Diversity Radio System; Multimode Digital Receiver (3G); TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE; I/Q Demodulation System; Smart Antenna System; General Software Radio; Ultrasonic Equipment; Broadband data application.

General Instructions

The AD9643 is a dual 14-bit analog-to-digital converter (ADC) with sampling speeds up to 250 MSPS. The AD9643 is designed to support low-cost, small-scale communications applications requiring size, wide bandwidth, and versatility.

The dual ADC core has a multi-stage differential pipeline architecture with integrated output error correction logic. Each ADC has support for a variety of user-selectable input ranges. An integrated voltage reference simplifies design considerations. A duty cycle stabilizer is provided in order to compensate for variations in the duty cycle of the ADC clock so that the converter maintains good performance.

ADC output data is routed directly to two external 14-bit LVDS output ports in either interleaved or channel multiplexed format.

Flexible power-off options provide significant power savings, if needed.

Setup and control are programmed using a 3-wire SPI compatible serial interface.

The AD9643 is available in a 64-lead LFCSP and is protected by a US patent with an industrial temperature range of -40°C to +85°C.

Product Highlights

1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS adc.

2. Operates from a single 1.8V power supply and a separate digital power supply. The output drive power supply regulates the LVDS output.

3. Proprietary differential input maintains good SNR performance for input frequencies up to 400 MHz.

4. Sync input allows multiple devices to be synchronized.

5. 3-pin 1.8V SPI port for register programming and register readback.

6. Pin compatible with AD9613, allowing down-migration from 14-bit to 12-bit. This part is also pin compatible with the AD6649 and AD6643.

Absolute Maximum Ratings

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Thermal characteristics

The exposed blades must be soldered to the ground plane of the LFCSP package. This increases the reliability of the solder joints and maximizes the thermal performance of the package.

1. According to JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2. According to JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3. In accordance with MIL Std 883 , Method 1012.1.

4. According to JEDEC JESD51-8 (still air).

A typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow increases heat dissipation, which reduces θJA. Additionally, the metal in direct contact with the package is drawn from metal traces, vias, ground and power planes, reducing θJA.

Typical performance characteristics

AVDD=1.8 V, DRVDD=1.8 V, Sampling Rate=Maximum sampling rate per speed grade, DCS enabled, 1.75 V pp differential input, VIN=-1.0 dBFS, 32k samples, TA=25° unless otherwise noted C.

Equivalent Circuit

theory of operation

The AD9643 has two analog input channels and two digital output channels. Intermediate frequency (IF) signals go through several stages before appearing at the output ports.

A dual ADC design can be used for signal diversity reception, where the ADCs operate identically on the same carrier, but from two separate antennas. ADCs can also be operated with separate analog inputs. Users can sample frequencies from dc to 300mhz using appropriate low-pass or band-pass filtering at the ADC input with little loss of ADC performance. Operation on 400 MHz analog inputs is allowed, but at the expense of increased ADC noise and distortion.

Synchronization is provided to allow synchronized timing between multiple devices.

Programming and control of the AD9643 is accomplished using a 3-pin, SPI-compatible serial interface.

ADC Architecture

The AD9643 architecture consists of a dual front-end sample-and-hold circuit and a pipelined switched-capacitor ADC. In the digital correction logic, the quantized outputs from each stage are combined into a final 14-bit result. The pipelined architecture allows the first stage to operate on new input samples and the remaining stages to operate on previous samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last stage, consists of a low-resolution flash ADC connected to a switched-capacitor digital-to-analog converter (DAC) and an interstage residual amplifier (MDAC). The MDAC amplifies the difference between the reconstructed DAC output and the flash input for use in the next stage. One bit redundancy is used per stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage of each channel contains a differential sampling circuit that can be coupled ac or dc in differential or single-ended mode. The output scratch block aligns the data, corrects errors, and passes the data to the output buffer. The output buffer is powered by a separate power supply, allowing the digital output noise to be separated from the analog core. During power down, the output buffers go into a high impedance state.

Analog Input Considerations

The analog input to the AD9643 is a differential switched capacitor circuit designed for optimum performance when dealing with differential input signals.

The clock signal alternately switches the input between sample mode and hold mode (see the configuration shown in Figure 46). When the input switches to sampling mode, the signal source must be able to charge the sampling capacitor and settle in 1/2 the clock cycle.

Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. A parallel capacitor can be placed at the input to provide dynamic charging current. This passive network creates a low-pass filter at the ADC input; therefore, the exact value depends on the application.

In IF undersampling applications, parallel capacitors should be reduced. Combined with the drive source impedance, the shunt capacitor limits the input bandwidth. Refer to the AN-742 application note, Domain Response of Frequency Switched Capacitor ADCs; AN-827 Application Note, Resonance Methods for Interfacing Amplifiers to Switched Capacitor ADCs; and the Analog Dialogue article, "Transformer-Coupled Front Ends for Wideband A/D Converters", for more information on this topic.

For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched and the inputs should be differentially balanced.

Input common mode

The analog inputs of the AD9643 have no internal dc bias. In AC-coupled applications, the user must provide this bias externally. Set the device to VCM=0.5×AVDD (or 0.9 V) for best performance. An on-board common-mode voltage reference is included in the design, available from the VCM pin. It is recommended to use the VCM output to set the input common mode. Best performance is obtained when the common-mode voltage of the analog inputs is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be separated from ground by a 0.1µF capacitor, as described in the Applications Information section. This decoupling capacitor should be placed close to the pin to minimize the series resistance and inductance between the part and this capacitor.

Differential Input Configuration

Best performance is obtained when driving the AD9643 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 differential drivers provide excellent performance and a flexible ADC interface.

The output common-mode voltage of the ADA4930-2 is easily set with the VCM pin of the AD9643 (see Figure 47), and the driver can be configured in a Sallen key filter topology to provide band limiting of the input signal.

For baseband applications where signal-to-noise ratio is a critical parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 48. To bias the analog input, the VCM voltage can be connected to the center tap of the transformer secondary winding.

Signal characteristics must be considered when selecting a transformer. Most RF transformers have saturation frequencies below a few megahertz. Excessive signal power can also cause the core to saturate, resulting in distortion.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is insufficient to achieve the true SNR performance of the AD9643. Suitable for signal-to-noise ratio is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 50). In this configuration, the inputs are AC coupled, and the VCM voltage is supplied to each input through 33Ω resistors. These resistors compensate for losses in the input balun, providing a 50Ω impedance to the driver.

In dual balun and transformer configurations, the values of the input capacitors and resistors depend on the input frequency and source impedance. Based on these parameters, the values of the input resistors and capacitors may need to be adjusted, or certain components may need to be removed. Table 10 shows suggested values for setting up the RC network for different input frequency ranges. However, these values are dependent on the input signal and bandwidth and should only be used as a start-up guide. Note that the values given in Table 10 apply to each of the R1, R2, C2 and R3 components shown in Figure 48 and Figure 50.

Another way to use a transformer-coupled input at the frequency of the second Nyquist zone is to use a variable gain amplifier. The AD8375 or AD8376 digital variable gain amplifiers (DVGAs) provide good performance for driving the AD9643. Figure 49 shows an example of the AD8376 driving the AD9643 through a bandpass antialiasing filter.

voltage reference

A stable and accurate voltage reference is built into the AD9643. The full-scale input range can be adjusted by changing the reference voltage via SPI. The input range of the ADC tracks linear changes in the reference voltage.

Clock Input Considerations

For best performance, the AD9643 sampling clock inputs, CLK+ and CLK-, should be clocked with differential signals. Signals are typically AC coupled to the CLK+ and CLK- pins through transformers or capacitors. These pins are internally biased (see Figure 51) and do not require external biasing. If the input is floating, the CLK pin is pulled low to prevent false clocks.

Clock input options

The AD9643 has a very flexible clock input structure. The clock input can be CMOS, LVDS, LVPECL, or a sine wave signal. Regardless of the type of signal used, clock source jitter is of greatest concern, as described in the Jitter Considerations section.

Figure 52 and Figure 53 show two preferred methods for clocking the AD9643 (at clock rates up to 625mhz). Low-jitter clock sources use RF baluns or RF transformers to convert from single-ended to differential signals.

For clock frequencies between 125 MHz and 625 MHz, an RF balun configuration is recommended; for clock frequencies between 10 MHz and 200 MHz, an RF transformer is recommended. Back-to-back Schottky diodes on the secondary side of the transformer limit the clock skew of the AD9643 to approximately 0.8V pp differential. This limit helps prevent large voltage fluctuations of the clock from being fed through other parts of the AD9643, while maintaining the fast rise and fall times of the signal, which are critical for low jitter performance.

If a low-jitter clock source is not available, another option is to ac-couple the differential PECL signal to the sampling clock input pins, as shown in Figure 54. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, AD9524 and ADCLK905/ADCLK907/ADCLK925 clock drivers provide excellent jitter performance.

A third option is to AC couple the differential LVDS signal to the sample clock input pins, as shown in Figure 55. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers provide excellent jitter performance.

input clock divider

The AD9643 includes an input clock divider capable of dividing the input clock by an integer value between 1 and 8. By default, the duty cycle stabilizer (DCS) is enabled at power-up.

The AD9643 clock divider can be synchronized using an external synchronization input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after a register write. A valid synchronization causes the clock divider to reset to its initial state. This synchronization feature allows alignment of clock dividers in multiple sections to ensure simultaneous input sampling.

clock duty cycle

Typical high-speed ADCs use two clock edges to generate various internal timing signals, and the results can be sensitive to the clock duty cycle. Typically, a ±5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics. The AD9643 includes a duty cycle stabilizer (DCS) that retimes the non-sampling (falling) edges to provide an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9643.

Jitter on the rising edge of the input clock is still the most important issue, and the duty cycle stabilizer does not reduce jitter. The duty cycle control loop is nominally unsuitable for clock rates below 40 MHz. When the clock rate can vary dynamically, the time constant associated with the loop must be considered. After the dynamic clock frequency is increased or decreased, a wait time of 1.5 microseconds to 5 microseconds is required before the DCS loop relocks to the input signal. During the period when the loop is not locked, the DCS loop is bypassed and the internal device timing depends on the duty cycle of the input clock signal. In this application, the duty cycle stabilizer can be appropriately disabled. In all other applications, it is recommended to enable the DCS circuit to maximize AC performance.

Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given input frequency (fIN), the signal-to-noise ratio degradation due to jitter (tJ) can be obtained by:

In the equation, rms aperture jitter represents the root mean square of all jitter sources, including clock input, analog input signal, and ADC aperture jitter specifications. If the undersampling application is particularly sensitive to jitter, as shown in Figure 56.

AD9643 If aperture jitter may affect the dynamic range of the AD9643, the clock input should be treated as an analog signal.

The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

Refer to AN-501 Application Note, Aperture Uncertainty and ADC System Performance, and AN-756 Application Note, Effects of Sampling System and Clock Phase Noise and Jitter for more information on ADC jitter performance.

Power Consumption and Standby Modes

As shown in Figure 57, the power dissipated by the AD9643 is proportional to its sampling rate. The data in Figure 57 was obtained using the same operating conditions as in the Typical Performance Characteristics section.

By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9643 is placed in power-down mode. In this state, the ADC typically dissipates 10 mW. When powered down, the output drivers are in a high impedance state. Asserting the PDWN pin low returns the AD9643 to its normal operating mode. Note that PDWN refers to the digital output drive power supply (DRVDD), which should not be exceeded.

Low power consumption in shutdown mode is achieved by turning off the reference, reference buffer, bias network and clock. Internal capacitors are discharged when entering power-down mode and must then be recharged when normal operation is resumed. Therefore, the wake-up time is related to the time spent in power-down mode, and a shorter power-down period will reduce the wake-up time accordingly.

When using the SPI port interface, the user can place the ADC in power-down or standby mode. Standby mode allows the user to keep the internal reference circuit powered up when a faster wake-up time is required. For more details, see the Memory Mapped Register Descriptions section and the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

digital output

The AD9643 output driver can be configured as ANSI LVD or reduced driver LVD using a 1.8 V DRVDD supply.

As described in the AN-877 application note, through the SPI interface to the high-speed ADC, when using SPI control, the data format of offset binary, two's complement, or gray code can be selected.

Digital output enable function (OEB)

The AD9643 has flexible tri-state capability for digital output pins. Tri-state mode is enabled using the OEB pin or via the SPI interface. If the OEB pin is low, the output data driver is enabled. If the OEB pin is high, the output data driver is in a high impedance state. This OEB function is not intended for fast access to the data bus. Note that OEB refers to the digital output driver supply (DRVDD) and should not exceed this supply voltage.

When using the SPI interface, the data outputs for each channel can be independently represented as three by using the output enable bar bit (bit 4) in Register 0x14. Since the output data is interleaved, if only one of the two channels is disabled, the output data of the remaining channels repeats in the rising and falling output clock cycles.

opportunity

The AD9643 provides latched data with a pipeline delay of 10 input sample clock cycles. The data output is available one propagation delay (tPD) after the rising edge of the clock signal.

The length of the output data lines and load should be minimized to reduce transients within the AD9643. These transients degrade the dynamic performance of the converter.

The minimum typical conversion rate of the AD9643 is 40 MSPS. Dynamic performance may degrade when clock rates are below 40ms/sec.

Data Clock Out (DCO)

The AD9643 also provides a data clock output (DCO) for capturing data from external registers. Figure 2 shows a graphical timing diagram of the AD9643 output mode.

ADC overrange (or)

The ADC overrange indicator is asserted when overrange is detected at the ADC input. The overrange condition is determined at the output of the ADC pipeline and, therefore, is affected by a delay of 10 ADC clocks. An input overrange is indicated by this bit, 10 clock cycles after this bit occurs.

Channel/Chip Synchronization

The AD9643 has a synchronization input that allows the user flexible synchronization options to synchronize internal blocks. The synchronization function is very useful for guaranteeing synchronized operation between multiple ADCs. The input clock divider can be synchronized using the sync input. The divider can be synchronized on one or every occurrence of the sync signal by setting the appropriate bits in Register 0x3A.

The sync input is internally synchronized to the sample clock. However, to ensure that there is no timing uncertainty between the multiple parts, the synchronization input signal should be synchronized with the input clock signal. The sync input should be driven with a single-ended CMOS type signal.

Serial Port Interface (SPI)

The AD9643 serial port interface (SPI) allows the user to configure the converter for a specific function or operation through the structured register space provided within the ADC. SPI provides users with additional flexibility and customization, depending on the application. The address is accessed through the serial port and can be written or read through the port. Memory is organized into bytes, which can be further divided into fields. These fields are documented in the memory map section. For detailed operational information, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Configuration using SPI

Three pins define the SPI for this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 12). The SCLK (serial clock) pin is used to synchronize read and write data from the ADC. The SDIO (Serial Data Input/Output) pin is a dual purpose pin that allows data to be sent and read from the internal ADC memory mapped registers. The CSB (chip select bar) pin is an active low control that enables or disables read and write cycles.

The falling edge of CSB and the rising edge of SCLK together determine the start of the frame. Examples of sequence timing and its definitions can be found in Figure 58 and Table 5.

Other modes involving CSB are also available. CSB can be held low indefinitely, which will permanently enable the device; this is called streaming. CSB can be suspended high between bytes to allow for additional external timing. When CSB is tied high, the SPI function is put into high impedance mode. This mode enables any SPI pin auxiliary functions.

In the command phase, a 16-bit command is sent. The data follows the instruction phase and its length is determined by the W0 and W1 bits. All data consists of 8-bit words. The first bit of each byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pins to change the input direction to the output direction.

In addition to word length, the instruction stage determines whether the serial frame is a read or write operation, allowing the serial port to be used to program the chip and read the contents of on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pins to change from input to output at the appropriate point in the serial frame.

Data can be sent in MSB first mode or LSB first mode. MSB first is the default value at power-on and can be changed through the SPI port configuration registers. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

hardware interface

The pins described in Table 12 comprise the physical interface between the user programming device and the serial port of the AD9643. When using the SPI interface, the SCLK pin and the CSB pin are used as inputs. The SDIO pins are bidirectional and act as inputs during the write phase and as outputs during readback.

The SPI interface is flexible enough to be controlled by FPGAs or microcontrollers. One method of SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Bootstrap Circuits.

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9643 to prevent these signals from transitioning at the converter inputs during critical sampling.

SPI accessible functions

Table 13 briefly describes the general features accessible through the SPI. These features are described in detail in the AN-877 application note, which interfaces with high-speed ADCs via SPI. AD9643 part specific functions are described in the Memory Mapped Registers section.

memory map

Read Memory Mapped Register Table

Each row in the memory-mapped register table has eight bit positions. The memory map is roughly divided into three parts: chip configuration registers (Address 0x00 to Address 0x02); Channel Index and Transfer registers (Address 0x05 and Address 0xFF); and ADC function registers, including setup, control, and test (Address 0x08 to Address 0x3A) ).

The memory-mapped register table (see Table 14) records the default hex value for each hex address shown. Columns with header bit 7 (MSB) are the start of the given default hex value. For example, the hexadecimal default value for address 0x14 (the output mode register) is 0x05. This means that bit 0=1 and bit 2=1, the remaining bits are 0. This setting is the default output format value, which is two's complement. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI. This document details the functions controlled by register 0x00 to register 0x20. The remaining register 0x3A is documented in the Memory Mapped Register Description section.

Open and reserved locations

All addresses and bit positions not included in Table 14 are not currently supported by this device. Unused bits in valid address locations should be written with 0. These locations only need to be written if part of the address location is open (for example, address 0x18). If the entire address location is open (for example, address 0x13), this address location should not be written.

Defaults

After the AD9643 is reset, the key registers are loaded with default values. The default values for the registers are given in Table 14 of the Memory Mapped Registers.

logic level

Logic level terms are explained as follows:

• "Bit is set" is synonymous with "Bit is set to Logic 1", or "A logic 1 is being programmed for a bit."

• "Clear a bit" is synonymous with "bit is set to Logic 0", or "A logic 0 is being written to the bit."

transfer register map

Address 0x08 to Address 0x20 and Address 0x3A are hidden. Writing to these addresses does not affect part of the operation until a transfer command is issued by writing 0x01 to address 0xFF and setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place after the transfer bit is set, then the bit is automatically cleared.

channel-specific registers

Certain channel setup functions, such as signal monitor thresholds, can be programmed to different values for each channel. In these cases, the channel address location is repeated inside each channel. These registers and bits are designated as local in Table 14. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, subsequent writes affect the registers of both channels. During a read cycle, only channel A or channel B should be set to read one of the two registers. If these two bits are set during the SPI read cycle, the part returns the value of channel A. Registers and bits designated as global in Table 14 affect the entire component and channel characteristics, and independent settings between channels are not allowed. The settings in Register 0x05 do not affect global registers and bits.

Memory Mapped Register Table

All addresses and bit positions not included in Table 14 are not currently supported by this device.

Memory Mapped Register Description

For more information on the functions controlled in Register 0x00 through Register 0x20, see the AN-877 Application Note, Interfacing with High Speed ADCs via SPI.

Synchronization Control (Register 0x3A)

Bit 2 clock divider, next sync only

If the master sync buffer enable bit (Address 0x3A, Bit 0) and the clock distributor sync enable bit (Address 0x3A, Bit 1) are high, bit 2 allows the clock distributor to sync to the first sync pulse it receives and ignore the rest pulse. The clock divider synchronization enable bit (Address 0x3A, Bit 1) resets after synchronization.

Bit 1 Clock Splitter Sync Enable

Bit 1 gates the sync pulse to the clock divider. When bit 1 is high and bit 0 is high, the sync signal is enabled. This is continuous sync mode.

Bit 0 - Primary Sync Buffer Enable

Bit 0 must be set high to enable any synchronization functions. If synchronization is not used, this bit should be kept low to save power.

application information

Design Guidelines

Before beginning system-level design and layout for the AD9643, designers are advised to familiarize themselves with these guidelines, which discuss the special circuit connections and layout requirements required for specific pins.

Power and Grounding Recommendations

When connecting power supplies to the AD9643, it is recommended to use two separate 1.8V supplies: one supply for the analog (AVDD) and the other for the digital output (DRVDD). Designers can use several different decoupling capacitors to cover high and low frequencies. These capacitors should be located close to the entry point at the PC board level and close to the pins of parts with minimum trace lengths.

When using the AD9643, a single PCB ground plane should be sufficient. Optimum performance is easily achieved with proper decoupling and intelligent partitioning of the analog, digital and clock sections of the PCB.

Exposed Blade Hot Slug Recommendations

For best electrical and thermal performance, the exposed paddle on the bottom of the ADC must be connected to analog ground (AGND). A continuous, exposed (no solder mask) copper plane on the PCB should match the exposed paddle (pin 0) of the AD9643.

The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation through the bottom of the PCB. These vias should be filled or plugged with non-conductive epoxy.

To maximize coverage and adhesion between the ADC and the PCB, a silkscreen should be covered to divide the continuous plane on the PCB into several uniform sections.

This provides several connection points between the ADC and the PCB during reflow. Using a continuous plane with no partitions ensures that there is only one connection point between the ADC and the PCB. See the evaluation board for an example PCB layout. For more information on packaging and PCB layout for chip scale packages, see AN-772 Application Note, Design and Manufacturing Guidelines for Lead Frame Chip Scale Packages (LFCSP).

VCM

A 0.1µF capacitor should be used to separate the VCM pin from ground, as shown in Figure 48. For best channel-to-channel isolation, include 33Ω resistors between the AD9643 VCM pins and the channel a analog input network connection and between the AD9643 VCM pins and the channel B analog input network connection.

SPI port

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9643 to prevent these signals from transitioning at the converter input pins during critical sampling.

Dimensions