feature

Low Supply Current: 250 μA/amp max; High Slew Rate: 9V/μs; Bandwidth: 3.5 MHz typical; Low Offset Voltage: 1 mV max at 25°C; Low Input Bias Current: 20 max at 25°C Pa; CMRR: 90db typical fast settling time unity gain stable.

application

Mobile communications; low power industrial instrumentation; loop filters; active and precision filters; integrators; strain gage amplifiers; portable medical devices; power supply current monitoring.

General Instructions

The AD8682 and AD8684 are dual and quad low power, precision (1 mV) JFET amplifiers with excellent speed at low supply current. The slew rate is typically 9 V/µs when the supply current per amplifier is less than 250µA. The typical gain bandwidth of these unity-gain stabilized amplifiers is 3.5MHz. The JFET input stage ensures that the bias current is typically a few picoamps, with a maximum value below 125Pa , over the entire temperature operating range.

These devices are ideal for portable, low-power applications, especially those with high source impedance. These devices are unity-gain stable and can drive higher-capacity loads (G=1, non-rotating), an example of their good dynamic response over a wide range of conditions, providing DC precision performance at low quiescent current.

Typical performance characteristics

application information

The AD8682 and AD8684 are dual JFET and quad JFET op amps that operate at high speed at low power. This combination makes these amplifiers the best choice for battery-operated or low-power applications that require above-average performance. Applications that benefit from this combination of performance include telecommunications, geophysical exploration, portable medical equipment and navigation instruments.

High Side Signal Conditioning

In many applications, signals need to be sensed near the positive rail. The AD8682 and AD8684 are tested and guaranteed to be within the common-mode range including the positive supply (-11 V≤V≤+15 V).

The AD8682/AD8684 are typically used for sensing supply current and current sensing applications, such as the partial circuit shown in Figure 32. In this circuit, the voltage drop across a low value resistor (0.1Ω as shown in the figure) is amplified and compared to 7.5 V. The output can then be used for current limiting.

Phase inversion

Most JFET input amplifiers invert the phase of the input signal if either input exceeds the input common-mode range. For the AD8682/AD8684, a negative signal over 11v results in a phase reversal. This is due to the forward bias of the gate-drain diode due to saturation of the input stage. Phase reversal in the AD8682/AD8684 can be prevented by using Schottky diodes to clamp the input terminals to each other and to the power supply. In the simple buffer circuit below, D1 protects the op inverting amplifier. R1, D2, and D3 limit the input current when the input exceeds the supply rails. Resistors should be chosen to limit the input current below the absolute maximum ratings.

Active filter

The wide frequency band and high slew rate of the AD8682/AD8684 make both the best choice for many filter applications.

There are many active filter configurations, but the four most popular are: Butterworth, Ellipse, Bessel, and Chebyshev. Each type has a response optimized for a given characteristic, as shown in Table 4.

Programmable State Variable Filter

The circuit shown in Figure 35 can be used to precisely program the Q factor, cutoff frequency (f), and gain of a bipolar state variable filter. AD8684 has the advantages of high bandwidth, low power consumption, low noise, etc., and has been widely used in this design. Due to the quadruple configuration of op amps and digital-to-analog converters, the circuit can be constructed in only three packages.

The DAC shown is used in voltage mode; therefore, many values depend only on the accuracy of the DAC and not on the absolute value of the DAC resistance ladder. As a result, this makes the circuit extremely accurate for programmable filters.

Adjusting DAC 1 changes the signal amplitude of R1; therefore, DAC attenuation x R1 determines the amount of signal current that charges integrating capacitor C1.

The cutoff frequency can be expressed as:

where D1 is the digital code of the DAC.

DAC 3 is used to set the gain. The gain equation is:

DAC 2 is used to set the Q of the circuit. Adjusting this DAC controls the amount of feedback from the bandpass node to the input summing node. Note that the digital value of the DAC is in the numerator; therefore, the zero code is not a valid operating point.

Dimensions