Today I want to talk with you about the IO of FPGA

First let me tell you about my experience. There are not many laboratories with FPGA development conditions in domestic universities. Some of the students in the university did ARM, some did Linux, and very few did FPGA. At that time, learning FPGA was just because of very eager curiosity. Therefore, I bought a development board on Taobao and started my own FPGA road.

The content of most development boards is mainly to teach students how to write Verilog code, and they rarely give detailed explanations and interpretations of the FPGA chip architecture, so I encountered a very embarrassing thing during the interview that year. The interviewer was the first The question is: which FPGA is used and what is the core voltage? At that time, I was stunned. Although I have been working on FPGA for almost a year, I have not paid attention to the core voltage of the chip....

But in fact, it is very important to be familiar with the basic architecture of FPGA and understand the internal resources of FPGA chip!

Although many FPGA engineers write code, as a hardware programming engineer, if you are not familiar with the underlying resources and architecture of FPGA, it is difficult to write high-quality code - at least it is difficult to write high-quality code for complex logic, and it is also very difficult to write high-quality code. It is difficult to consider the chip selection and other issues at the system level. So familiar with the FPGA architecture, first and foremost, let's first understand the IO of the FPGA.

FPGA's IO naming. FPGA chip IO has too many naming methods and too many pins, which makes people feel very messy. This is how I felt back then, such as I would often hear: A13 , B14 ...BANK34, BANK12...MIO0, EMIO.... But this is indeed the characteristic of FPGA, FPGA can be compatible with a variety of different voltage standards, and also has abundant IO.

First of all, the IO physical naming rules of FPGA, that is, the naming when we make pin constraints, the chip is usually a cuboid or a cube, so the naming usually adopts a combination of letters and numbers, from top to bottom are letters (A, B, C , D``), from left to right are numbers (1, 2, 3``), so such as: A13 (see the figure below), which is the position marked in red on the figure, this is a schematic diagram of a chip of xilinx , FPGA chips from other manufacturers are similar.

The internal resources of the FPGA chip are very important, and special attention should be paid to the power supply of Serdes when designing

Secondly, the function naming rules of FPGA. Function naming rules Each manufacturer will have its own set of rules, but they are all similar. We will focus on the naming of xilinx (xilinx's documentation is the industry benchmark, and other FPGA manufacturers' materials will refer to xilinx to some extent). Usually the function naming format of xilinx is: IO_LXXY#/IO_XX. in:

(1) IO represents user IO;

(2) L stands for differential, XX stands for the unique identification number under the current BANK, Y=[P|N] stands for P or N of LVDS signal;

(3) # indicates the Bank number.

For example, there is an IO name in our schematic diagram: IO_L13P_T2_MRCC_12, then we can know through the function naming rules that this is a user IO, supports differential signals, and is the 13th pair of differential P ports of BANK12, and this It is also a global clock network input pin (MRCC is a global clock network).

Again, what is Bank. Bank is a general term for a group of IOs with similar physical locations and characteristics. The voltage reference of the same BANK is the same. Therefore, if we usually need voltages of different standards, we can achieve it by giving the voltage reference to the BANK in different ways. A variety of level standard input and output. Usually, the larger the package, the more banks, and the more voltage standards it can support. The following figure is an IO BANK distribution diagram of ZYNQ 7030 :

The internal resources of the FPGA chip are very important, and special attention should be paid to the power supply of Serdes when designing

In addition to the user IO of the FPGA, there are many other functional IOs, such as the download interface, the mode selection interface, and the MRCC, which is the global clock network and local clock network we mentioned earlier. Among them, the most noteworthy is the power supply pin of the FPGA. The ZYNQ device contains two completely independent power supply systems, one is the power supply (PS) of the embedded side, and the other is the power supply (PL) of the logic side. The two power supply systems are completely Independent, so there is no sequential power-on requirement. as follows:

The internal resources of the FPGA chip are very important, and special attention should be paid to the power supply of Serdes when designing

Voltages usually included are:

(1) Core voltage, Vccpint and Vccint are the core voltage of PS and the content voltage of PL respectively. The size of the core voltage is usually related to the process. For example, the core voltage of the 48nm XILINX device is 1.2v, and the core power supply of the 28nm ZYNQ device is 1.0 v (usually the voltage has a range, and the range is also related to the speed grade). Of course, the lower the voltage, the lower the corresponding power consumption will be under the same logic scale and main frequency.

(2) Vccpaux and Vccaux are the auxiliary voltages of PS and PL, respectively. 1.8v in ZYNQ devices.

(3) Vccpll is the power supply voltage for the internal phase-locked loop.

(4) Vcc_mio0 is the reference voltage of the MIO0 BANK of the PS, and VCCO_DDR is the voltage of the DDR at the PS end. This voltage is usually related to the selected DDR particles, such as (DDR3, LDDR3, etc. The corresponding values are different, in this part we all to be explained in more detail in the related video).

(5) Vccon This part is the Bank benchmark on the PL side we mentioned earlier.

For pure logic FPGA devices, since there is no PS side, there is no corresponding PS side power supply, only the PL side power supply, which is simpler to implement.

Finally, let's talk about powering up the FPGA. Like all devices, the power-on of the FPGA follows a certain power-on logic. Usually, the power-on time of the SRAM structure (XILINX, Altera, etc. belong to the SRAM structure) is longer than that of the FLASH structure (Microm, Actel, etc.). be long. In order to simplify the BOM cost (such as Anlu Semiconductor), some domestic FPGAs do not require users to pay special attention to the power-on sequence, use a single power supply to supply power, and the chip controls the power-on sequence internally. Although the unreasonable power-on sequence can sometimes make the FPGA work normally, the abnormal power-on or power-off process may cause excessive instantaneous current, which cannot guarantee that the FPGAIO will be tri-stated during the power-on period, or even damage the chip. Designers need to pay special attention to the power-on sequence. Power-up for XILINX FPGAs generally requires the following rules:

(1) On the PS side, Vccpint, Vccpaux, and Vccpll are powered up together, and then start the Vcco power supply (Vcco_mio0, Vcco_mio1, Vcco_ddr) of the PS, where PS_POR_B should remain low during power-on until the core, auxiliary voltage, PLL voltage and BANK voltage reaches the corresponding threshold. The power-off sequence is the same as the power-on sequence.

(2) On the PL side, the recommended power-on sequence is Vccint, Vccbram, Vccaux, Vccaux_io, Vcco. Among them, if Vccint and Vccbram are the same voltage, the same power supply can be used to supply power and start at the same time. If Vccaux, Vccaux_io and Vcco are the same voltage, the same power supply can also be used to start at the same time.

In addition, in designing the schematic diagram of the FPGA, special attention should be paid to the power supply of Serdes (different manufacturers, even different devices of the same manufacturer have different names for Serdes, such as: GTH, GTX, etc., but the essence is self-synchronization high-speed serial transceivers, the supported rates are different), if not used, it needs to be suspended or grounded accordingly.