PLD (Programmable Logic Device) has developed rapidly and attracted more and more attention due to its flexible operation, convenient use, rapid development and low investment risk. PLD is a logic device that can be programmed by users on the job site. It has developed from simple PAL and GAL to CPLD , EPLD, FPGA and FLEX series. They all have the characteristics of flexible architecture and logic unit, high integration and wide application range.

Compared with the previous PAL, GAL, etc., the scale of FPGA/CPLD is relatively large, and it is suitable for applications in logic circuits such as timing and combination. Programmable logic devices are easy to learn and use, simplify system design, reduce system scale, and improve system reliability. There are tens of thousands of gates available for a device, the inter-pin delay is only a few ns, and it is still developing rapidly in the direction of high density and high speed.

A computer bus is a common channel for information transmission between various components of a computer. In today's microcomputers, the PCI bus is mainly used, and the ISA and EISA buses are being phased out gradually. Therefore, it is very important for hardware designers to master the development technology of PCI bus boards. There are usually several design methods for boards: one is to do ASIC, which has a long development cycle; the other is to develop under a dedicated interface chip, but the use is not very flexible and the system scale is large; the latest method is to use PLD to develop design.

When designing the CPLD, the software used is Altera's MAX+PLUSII. Altera's MAX+PLUSII development system is a fully integrated, easy-to-learn, structure-independent programmable logic design environment that enables general-purpose series designers to easily perform design entry, rapid processing, and device programming using this software The design method is very flexible, can use hardware description language (PLD), circuit diagram, and even timing diagram. Different methods can be used according to different situations, and multiple methods can also be used in one design. The following takes a simple PCI slave device design as an example to illustrate the design idea and process.

In this example, the designed PCI card is used as a slave device, which can realize the function of plug and play, and there is 1MB of memory available on the card. In the design of PCI plug-and-play board, the core design has two parts: timing control and configuration space. Timing control ensures that the board can work according to the normal PCI timing, and the configuration space part ensures the plug-and-play function of the board.

In this example, these two parts are implemented by AHDL language (AHDL language is a hardware description language specially developed by Altera Corporation for its chip design). In the sequence control program, the state machine model is used to realize the conversion of different time sequences. This method saves resources and the program is simple and easy to understand.

The state machine in this example uses a total of seven states, which correspond to the timing of idle, memory read and write judgment, configuration read and write judgment, read, write, transition period, and bus busy period. After the board receives the reset signal, it resets the system, and then goes to the idle state. The bus is sampled in the idle state, and according to the change of the bus, it is determined which state the state machine will transfer to after the next rising edge of the clock. The signals used in these timings and programs are basic and necessary. Necessary states and signals can be added as needed during development. The program description is as follows:

subdesignstatesmachine,

(clk, rst, frame, ad[31..0], cbe[3..0], idsel, irdy, mem_bar[12..0]: input;

devsel, trdy, cfg_rd, cfg_wr, mem_rd, mem_wr: output;

cfg_addr[5..0], mem_addr[16..0]: output;)

//The above defines the input and output pins of the state machine module

VARIABLE

pci_state:MACHINE

WITHSTATES(idle, cmp_cfg, cmp_addr, read, write, turn_ar, bus_busy);

//Define state machine variables, there are seven states idle state idle, configuration space operation cmp_cfg, comparison address cmp_addr, read state read, write state write, transition cycle state turn_ar, bus busy state bus_busy. The transition of time sequence is realized through different states of the state machine, and different time sequence cycles are realized in each state.

BEGIN

Initialization: Initialize internal signals and various input and output pins, and set their connection relationships.

IFrst==b "0" THEN//Determine whether to reset

Implement the timing operation of reset.

ELSE

CASEpci_stateIS

WHENidle="//idle state

In this state, the changes of frame and idsel signals are judged every clock cycle. Once the frame is found to be valid, the next state is judged according to the idsel signal to move to cmp_cfg for configuration space operations or cmp_addr for comparison addresses to memory operations.

WHENcmp_cfg="//The status of the configuration space operation

In this state, it is judged whether it is an operation on the configuration space according to the lower two bits of the address line. If it is not transferred to the bus busy state bus_busy; Status read, write.

WHENcmp_addr="//Address comparison status

In this state, it is judged whether the high bits of the address to be read and written are the same as the address allocated in the configuration space. If they are different, transfer to the bus busy state bus_busy; The corresponding state read, write.

WHENread="//Read state

In this state, judge whether to configure read or store read according to the value of cbe, and then control the output signals mem_rd, cfg_rd, trdy, devsel to generate the corresponding read timing, and at the same time judge the frame and irdy signals in this cycle, if irdy becomes low and The frame becomes high, the read state ends, and the state turns to turn_ar.

WHENwrite="//write status

In this state, judge whether to configure write or store write according to the value of cbe, and then control the output signals mem_wr, cfg_wr, trdy, devsel to generate the corresponding write timing, and at the same time judge the frame and irdy signals in this cycle, if irdy becomes low and When the frame becomes high, the write state ends and the turn_ar state is turned.

WHENturn_ar=”//The transition period state of the signal

According to the PCI bus specification, the S/T/S signal must be in a high-level state for at least one clock cycle before changing from valid to floating. In this state, set all S/T/S signals to high.

WHENbus_busy="//bus busy status

The bus does not operate on this card, so it is determined when to leave this state by judging the frame signal.

WHENOTHERS=》

If you enter this state, you should immediately switch to bus_busy or idle as needed

ENDCASE;

ENDIF;

END;

The configuration space part also uses AHDL language to describe the implementation, and defines the function of the PCI card, the allocation of memory space, and the product number, ID number, etc. in the configuration space. Only by defining the configuration space can the plug-and-play function of the board be guaranteed. Described as follows:

Design and Development of PCI Bus Board Based on AHDL Language and CPLD Technology

Design and Development of PCI Bus Board Based on AHDL Language and CPLD Technology

Both parts are generated by software modules, and the interface part between the two modules can be easily realized through the connection of the circuit diagram. The two modules are shown in Fig.

Using CPLD technology to develop PCI boards has the following advantages:

1. The development cycle is short, the cost is low, the investment risk is small, the standard products do not need to be tested, the quality is stable, and the real-time online inspection is possible. After the design is completed using CPLD technology, real-time timing simulation can be performed. Validate improved design results without repeating hardware experiments. After the design is passed, it is written into the chip, and it can be put into use after passing the test. It is simpler to develop than using some dedicated PCI chips, and other development equipment is omitted, so the cost is also lower. Compared with ASIC development cycle is much shorter.

2. It is flexible and convenient to use. Because the developed board is directly based on the basic specification of the bus, without using some special chips, the development is more flexible and free, and it is subject to fewer restrictions. The scale of the entire hardware module is also small, and many of its own algorithms can be combined with Technology and PCI are combined to make products with higher technical content.

3. It is beneficial to the protection of intellectual property rights and the improvement of software performance. Using this technology, you can make your own algorithm, technology and some software into hardware and solidify it on the card, which not only improves the running speed, but also makes it difficult for pirates to copy.

This text combines an example to give the design scheme of using CPLD technology to design various boards on PCI bus, which is simple and practical, and has high application value.