6326 -ic/" title="ISL6326 Product Parameters, Documentation and Sourcing Information" target="_blank">ISL6326 controls the microprocessor core voltage regulation via in parallel. The multiphase buck converter architecture uses interleaved timing to multiply the channel ripple Frequency reduces input and output ripple current. Low ripple results in fewer components, lower component cost, lower power dissipation, small loss, and small implementation area. Microprocessor loads can generate extremely fast edge rates for load transients. ISL6326 utilizes Intersil Proprietary Active Pulse Positioning (APP) and Adaptive Phase Alignment (APA) modulation schemes enable extremely fast transient response with less output capacitance. Today's microprocessors require tightly controlled output voltage position versus load current (drop ).Island 6326 utilizes patented technology to continuously sense output current to measure DCR of dedicated current sense resistor or output inductor. Current sensing provides signal droop, channel current balance and overcurrent protection required for precision. Programmable integrated temperature compensation is effectively implemented Function compensates for the temperature coefficient sensing element of the current. The current limit function provides single-phase overcurrent protection. A unity gain differential amplifier is provided for remote voltage sensing. Any potential difference between remotes uses the remote amplifier. Eliminates ground differences to improve regulation and Protection accuracy. Threshold sensitive enable input can be used for precise coordination of starting the ISL6326 with any other voltage rail. Dynamic Video 8482 ; technology allows seamless real-time video changes. Offset pins allow precise voltage offsets independent of the settings of the video settings.

feature

Proprietary active pulse positioning and adaptive phase alignment modulation scheme

Precision Polyphase Core Voltage Regulation - Differential Remote Sensing Voltage - Over Life, Load, Line and

Temperature - Adjustable Accuracy Reference Voltage Offset

Precision Resistive or DCR Current Sensing - Accurate Load Line Programming - Accurate Channel Current Balancing - Differential Current Sensing

Microprocessor Voltage Recognition Input - Dynamic Video™ Technology - 8-bit video input with selectable VR11 code and extended VR10 code at 6.25 mV per bit

Thermal monitoring

Integrated programmable temperature compensation

Overcurrent Protection and Channel Current Limit

Over voltage protection

2, 3 or 4 phase operation

Adjustable switching frequency per phase up to 1MHz

Package Options - QFN Compliant with JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Area; Improved PCB Efficiency, Thinner Profile

Lead Free (RoHS Compliant)

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Absolute Maximum Ratings

Supply voltage (VCC). +6 volts

all pins. Ground -0.3V to VCC+0.3V

Electrostatic discharge rating

mannequin. 2 kV

machine type. 200 volts

Charger model. 1.5kV

operating conditions

Supply voltage (VCC). +5V±5%

ambient temperature

ISL6326CRZ. 0°C to +70°C

ISL6326IRZ. -40°C to +85°C

Hot information

Thermal Resistance (Note 1, 2) θJA (Celsius/Watt) θJC (Celsius/Watt)

40 Ld QFN package. 32 3.5

maximum junction temperature. + 150 degrees Celsius

Maximum storage temperature range. -65°C to +150°C lead-free reflow profile.

NOTE: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to these conditions may affect product reliability and

cause malfunctions not covered by the warranty.

notes:

1. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct connect" characteristics.

2. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Electrical Specifications Operating Conditions: VCC=5V, unless otherwise specified

Electrical Specifications Operating Conditions: VCC=5V, unless otherwise specified. (continued)

notes:

3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

4. Specification limits determined by characterization, not production tested.

5. During soft start, VDAC first rises from 0V to 1.1V, and then rises to the VID voltage after receiving a valid VID.

6. The soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at a rate of 6.25 mV/cycle.

Function pin description

The VCC company provides the power needed to operate the chip. This occurs when the voltage on this pin exceeds the rising POR threshold and the voltage on this pin falls below the falling POR threshold. Connect this pin directly to the +5V supply.

ground

Bias and reference ground for integrated circuits. GND of the bottom metal base 6326 island.

reactor

This pin is the controller. Synchronous power-on of the controller and MOSFETs to the IC is provided through appropriate resistor dividers. ISL6326 activation when EN_PWR drive voltage is higher than 0.875V depends on the state of EN_VTT internal POR and pending fault state. Driving the PWR below 0.745V will clear all fault conditions and initiate a soft start when the ISL6326 is re-enabled. This pin is the controller. It is usually connected to the VTT output of the VTT voltage regulator in the computer motherboard. when? Driving EN_VTT above 0.875V, the ISL6326 activates the fault state based on EN_PWR, internal POR and pending. Driving below 0.745V will clear all fault conditions and start the ISL6326 to soft-start re-enable under the following conditions. Use this pin to set the desired switching frequency. A resistor from FS to ground will set the switching frequency. The relationship between the resistor values and the switching frequency will be approximated by the equation. Use this pin to set the desired start-up oscillator frequency. A resistor soft-start ramp rate from SS to ground will be set. The relationship between the value of resistance and the soft-start ramp time is described by an approximate equation.

Video 7, Video 6, Video 5, Video 4, Video 3, Video 2, Video 1 and Video 0 are the reference voltages for generating output regulation. Connecting these pins turns on sinking outputs (with or without external pull-ups) with resistors or active pull-up outputs. All video pins have 40µA voltages above logic high. These inputs can be external voltages up to VCC+0.3V.

Fussell

Use this pin to select the internal video code. To ground when it is connected, select the extended VR10 code. When it is floated or pulled high, the VR11 code is selected. This input can be pulled up to VCC+0.3V. VDIFF, VSEN, and RGND VSEN and RGND form a precision differential telemetry amplifier. This amplifier converts the differential remote output to a single-ended voltage referenced to local ground. VDIFF is the output of the amplifier and the input to the conditioning and protection circuits. Connect VSEN and RGND to the remote's sense pins to load.

FB and COMP

Invert the input and output of the error amplifier, respectively. FB can be connected to VDIFF through a resistor. Proper selection of resistors between VDIFF and FB can set the load line (droop) when the IDROOP pin is tied to the FB pin. The sag factor is determined by the ISEN resistor and inductor DCR or dedicated current sense resistor. The compensation is connected to the FB compensation regulator through an external RC network.

DAC and REF

The DAC pin is the output reference for the precision internal DAC. The REF pin is the wrong positive input amp. In a typical application, a 1kΩ, 1% resistor is used to generate a precision offset voltage between the DAC and REF. This voltage is proportional to the offset current by OFS to ground or VCC. Voltage Smoothing™ operation in Dynamic Video Surveillance using a capacitor between REF and ground.

PWM1, PWM2, PWM3, PWM4 pulse width modulation output. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels consists of PWM3 and password 4. Connect PWM3 to VCC to configure 2-phase operation. Connect PWM4 to VCC to configure three-phase operation.

ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+, ISEN4+- ISEN+ and ISEN- pins are independent differential amplifiers. Use sense current for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have each current sense input left open (eg, ISEN4+ and ISEN4- open for three-phase operation). For DCR sensing, connect each ISEN-pin to a node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, rising. Voltage and inductor current across a sense capacitor. Therefore, the induced current is proportional to the inductor current and rises according to the inductor. To match the delay of the internal circuitry, capacitors are required between each ISEN+ pin and GND, as described in "Current Sensing", page 12.

Virtual Reality

VR_RDY indicates that the soft-start is complete and the output voltage is set within the regulation range around VID. It is an open-drain logic output. VR will be pulled low when OCP or OVP occurs. It will also be pulled low if the output voltage is below the undervoltage threshold. OFS The OFS pin can be used to program the DC offset current it will be at the reference voltage and the DAC pin. The offset current is passed through external resistors and a precision internal voltage reference. by connecting a resistor to ground or to VCC. For no offset, the OFS pin should be unterminated. TOPO temperature compensation scale input. The temperature sensed by the voltage on the TM pin is used to adjust the ldroop and overcurrent protection limits to effectively compensate for the current sense element. To implement comprehensive temperature compensation, the resistor divider circuit requires one resistor to be connected from TCOMP to VCC of the controller and another resistor being connected from TCOMP to GND. Changing the ratio value of the resistor will set the gain compensation of the integrated heat. When the function is not used when temperature compensation is integrated, please connect TCOMP to GND.

IDROOP is the current proportional to the load current at the output pin that senses the average channel. In applications that do not require a load line, this pin can be connected to GND through a resistor to generate a voltage signal that is proportional to the load current and resistance value. In applications that require a load line, connect this pin to FB so that the average current sensed will flow through the resistor between FB and VDIFF creating a voltage drop proportional to the load current. Tie this pin to ground when not in use. The trademark TM is the input pin for virtual reality temperature measurement. Connect this pin to GND and the controller's VCC resistor through an NTC thermistor. The voltage on this pin is inversely proportional to the VR temperature. The ISL6326 monitors the VR temperature pins according to the voltage at the TM and outputs VR_HOT and VR_FAN signals. The virtual reality heat VR_HOT is used as an indication that the VR temperature is high. It is an open-drain logic output. If the measured VR temperature is below a certain level, and when the measured VR temperature reaches a certain value, turn on the level. An external pull-up resistor is required.

virtual fan

VR_FAN is an output pin with an open-drain logic output. Yes, if the measured VR temperature is less than a certain level, turn on when the measured VR temperature reaches a certain level. External pull-up resistors are required. Operating Multiphase Power Conversion The microprocessor load current profile has been changed to state that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing single-phase converters are both cost-effective and thermally feasible, forcing a move to multi-phase cost-saving approaches. The ISL6326 controller helps to reduce the minimum output components by integrating important functions and requirements. The block diagrams on page 3, 4 and 5 provide a top-level view of the polyphase power conversion using the ISL6326 controller.

The switching of each channel in the interleaved polyphase converter is with each other channel. In a three-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the channel below. Therefore, the combined ripple frequency of the three-phase converter is greater than the ripple frequency of any one phase. In addition, the peak-to-peak amplitude of the combined inductor current is reduced proportionally to the number of phases (equations 1 and 2). Increasing the ripple frequency and reducing the ripple amplitude means that designers can use less inductance per channel and lower total output capacitance for any performance specification. Figure 1 illustrates the frequency of the multiplication effect of the output ripple. The three channel currents (IL1, IL2 and IL3) are combined to form the AC ripple current and the DC load current. The ripple frequency of the ripple component is the current of each channel. Each pulse width modulation terminates a 1/3 cycle phase after the previous cycle's pulse width modulation. The combination of the DC components of the inductor current powers the load.

To understand the ripple current amplitude in a polyphase circuit, examine the peak-to-peak inductor current representing a single channel.

The output capacitor conducts the inductor current. In the case of multiphase converters the capacitive current is per individual channel. Combine Equation 1 with the expression for the peak-to-peak current after summing N symmetrically phase-shifted inductor current Equation 2. The peak-to-peak ripple current is reduced by an amount proportional to the number of channels. The output voltage ripple is a function of capacitance, equivalent series resistance (ESR) and inductor ripple current. Reducing inductor ripple current allows designers to use fewer or less expensive output capacitors.

Another benefit of interleaving is reducing input ripple current. The input capacitor section is determined by the maximum input ripple current. Multiphase topologies can increase overall system cost and scale by reducing input ripple, enabling designers to reduce the cost of input capacitors.

The example in Figure 2 demonstrates the current total input ripple current into a three-phase converter. The converter shown in Figure 2 delivers 36A from a 12V input to a 1.5V load. The rms input capacitor current is 5.9A. Compare this to a single-phase converter for the same buck, which is 12V to 1.5V at 36A. Single Phase Converter 11.9ARMS Input Capacitor Current. Single-phase converters must use an input capacitor bank with twice the rms current capacity equivalent to three-phase converters. Figures 18, 19, and 20 in the Input Capacitor section on page 28 can be used to determine the input capacitor rms current period and channel number based on load current, duty cycle. They are used to help determine the best input capacitor solution. Figure 21 shows the single-phase input capacitor RMS comparison current.

PWM modulation scheme

The ISL6326 uses Intersil's proprietary Active Pulse Positioning (APP) modulation scheme for improved transient characteristics. Application Control is a unique dual-edge PWM modulation scheme with both PWM lead and lag. The edges move independently to provide the best response to transient loads. However, the PWM frequency is constant through the FS pin and ground. To further improve transient response the ISL6326 also implements Intersil's proprietary adaptive phase alignment technology. APA, sufficient and large load step current, can turn on each phase at the same time. Through application and APA control, the ISL6326 can achieve excellent transient performance with reduced impact on output capacitors. Under steady-state conditions, the operating PWM modulator of the ISL6326 appears to be a conventional tracking modulator edge modulator. Conventional analytical design methods can thus be used for steady-state and small-signal operation. The timing of PWM operation for each channel is set by the number of active channels. The default channel setting for the ISL6326 is 4. The switching period is defined as the time between two pulse width modulation pulse termination signals for each channel. The cycle time pulse signal is the inverse of the switching frequency setting through a resistor between the FS pin and ground. The pulse width modulated signal commands the MOSFET driver to turn on/off the channel MOSFET. For 4-channel operation, the channel trigger sequence is 4-3-2-1: PWM3 pulse occurs on PWM4, 1/4 cycle after PWM2 is output after 1/4 cycle after PWM3, and PWM1 is delayed after PWM2 1/4 cycle. For three-channel operation, the channel trigger sequence is 3-2-1. Connect PWM4 to VCC to select three-channel operation at pulse intervals of 1/3 cycle increments. If PWM3 is connected to VCC, PWM2 pulses are 1/2 cycle pulse width modulated when dual-channel operation is selected.

On-off level

The switching frequency is set by a frequency setting resistor, RT, connected to the ground pin from FS (see diagrams labeled "Typical Applications" on pages 4 and 5). Equation 3 is used to help select the correct resistor value.

where FSW is the switching frequency of each phase

Current sensing

The ISL6326 continuously senses current for fast response. The ISL6326 supports inductor DCR sensing or resistive sensing technology. The associated channel current sense amplifier uses the ISEN input to reproduce a signal proportional to the inductor current. The sensed current, ISEN, is proportional to the inductor current. The sensed current is used for current balancing, load line regulation, and overcurrent protection. The internal circuits shown in Figures 3 and 4 represent one channel of an N-channel converter. This circuit is repeated for each channel in the converter, but the pins cannot be activated based on the state of PWM3 and PWM4, as described in "Pulse Width Modulation Operation" on page 11. Inductive DCR Inductive inductor windings have resistance (direct current resistance) parameters measured by DCR. Think of the inductive DCR as a separate concentrated quantity, as shown in Figure 3. This channel current IL flowing through the inductor also passes through the DCR. Equation 4 shows the equivalent voltage across the s-domain inductance VL.

The DCR voltage is extracted through a simple RC network of inductors, as shown in Figure 3. The voltage across the capacitor, VC, can be shown to be proportional to the channel current IL, see Equation 5.

If the RC network components are chosen so that the RC time constant (=R*C) matches the inductor time constant (=L/DCR), the voltage across the capacitor VC is equal to the voltage drop across the DCR, which is the same as the channel current.

Internal low offset current amplifier, the capacitor voltage VC is replicated as the sense resistor rises. Therefore, the current of ISEN+pin (ISEN) is proportional to the inductor current. Because of the internal filter of the ISEN pin, a capacitor, CT, is required to match the ISEN and ISEN+ signals. Choose an appropriate CT hold time rise constant and CT (rise x CT) close to 27ns. Equation 6 shows that the channel current versus the sense current (ISEN) is driven by the sensed value for the DCR of the resistor and inductor.

Resistive sensing

For accurate current sensing, a dedicated current sense resistor RSENSE is used in series with each output inductor can as the current sense element (see Figure 4). This technique is more precise, but reduces the efficiency-sensing element of additional power loss in the overall converter current. The same capacitor CT is required to match the delay between the ISEN- and ISEN+ signals. Choose an appropriate time constant for CT to keep rising and CT (rising x CT) off to 27ns. Equation 7 shows the channel current versus the sensed current.

The DCR value of the sensor will increase as the temperature increases. Therefore, the induced current will increase with the temperature of the current sensing element. To neatly compensate for the effect of temperature on the sensed current signal, a positive temperature coefficient (PTC) resistor can be selected for sensing resistance rise, or the integrated temperature compensation function of the ISL6326 should be utilized. The integrated temperature compensation function is described in "Temperature Compensation" on page 22. Channel Current Balance The induced currents for each active channel are summed together and divided by the number of active channels. This resulting average current (IAVG) provides the total load current. Channel current balancing is an Intersil patented current balancing method by comparing the induced current of each channel with an average current appropriately adjusted for the pulse width modulated duty cycle of each channel. The thermal advantage of channel current balancing for multiphase operation. Good current balance, power loss across multiple devices and larger areas. Voltage Regulation The compensation network shown in Figure 5 ensures that the steady-state error in the output voltage is limited to the error of the reference voltage (the output of the DAC) OFS current source, telemetry, and error amplifier. Intersil specifies that ISL6326 includes each of these elements. Combine the output of the error amplifier (VCOMP) with a sawtooth wave that produces a pulse width modulated signal. This PWM signal controls the timing of the MOSFETs to drive and regulate the converter output to a specified reference voltage. Internal and external circuits control voltage regulation as shown in Figure 5.

The ISL6326 includes a telemetry amplifier in the feedback path of the internal differential. The amplifier eliminates the induced output voltage at the point of measurement of the output voltage relative to the local controller ground. Connect the microprocessor sensor pins to the non-inverting input (VSEN) and the inverting input (RGND) of the remote control amplifier. The remote sense output (VDIFF) is connected to the wrong inverting input and amplified by an external resistor. A digital-to-analog converter (DAC) generates a reference signal based on the voltage of the logic signal state on pin VID7 through Video 0. The DAC decodes one of eight 6-bit logic signals (VID) of discrete voltages shown in Table 1. Each VID input provides a 45µA pull-up to an internal 2.5V supply for open-drain outputs. The pull-up current is decremented to zero above the logic threshold to protect voltage-sensitive output devices. External pull-up resistors if the case leaks into the drive device is greater than 45µA.

Load line regulation

Some microprocessor manufacturers require precise control of the output resistance. This dependence of the load current on the output voltage is often referred to as a "droop" or "load line" regulation. By adding well-controlled output impedance, the output voltage can be effectively level-shifted to achieve the direction of loadline regulation these manufacturers require. In other cases, designers can determine that a cost-effective solution can be achieved by adding sag. Droop helps reduce output voltage spikes as a result of rapid load current demand changes. The magnitude of the peak is determined by ESR and ESL to determine the number of output capacitors selected. By positioning the no-load voltage level close to the upper specification limit, large negative spikes can continue to be limited without crossing below. By adding a well-controlled output impedance the output voltage under the load can be effectively level-shifted down so that the upper specification limit is not exceeded. As shown in Figure 5, the current is proportional to the average value of the current of all active channels (IAVG) flowing from FB through the load line regulation resistor RFB. The resulting voltage drop is proportional to the output current through RFB, effectively producing an output voltage drop with a steady state value defined as Equation 8:

The adjusted output voltage reduces the droop voltage Vidrup. Output voltage as a function of load current Defining Equation 8 with the appropriate current meaning of the example current expression used in Equation 9.

where VREF is the reference voltage, VOFS is the programming offset voltage, IOUT is the total output current in the converter, rising is connected to the ISEN+ pin, RFB is the feedback resistor, N is the active channel number, and RX is the DCR or RSENSE depending on sensing method. Therefore, the equivalent load line impedance, the droop impedance, is equal to Equation 10:

Output Voltage Offset Programming The ISL6326 allows designers to precisely adjust the offset voltage. When resistor ROFS is connected from OFS to VCC, its voltage is regulated to 1.6V so that the proportional current (IOFS) flows into OFS. If ROFS is grounded, the voltage on it is regulated to 0.4V, and IOF flows out of OFS. The resistor selects RREF between DAC and REF so that the product (IOFS x ROFS) equals the desired offset voltage. These functions are shown in Figure 6. Once the desired output offset voltage is determined, use Equations 11 and 12 to set ROF: For positive offset (connect ROFS to VCC):