feature

3.0 V to 5.5 V supply operation; 50MHz serial interface; 10 MHz multiplier bandwidth; ±10 V reference input; low fault energy <2 nV-s; extended temperature range –40°C to + 125 °C; 10-lead MSOP package; Pin-compatible 8-, 10-, and 12-bit current; output DAC; guaranteed monotonic; four-quadrant multiply; power-on reset with browser detection; daisy-chain mode; readback capability; 0.4 typical power consumption.

application

Portable battery-powered applications; waveform generators; analog processing; instrumentation applications; programmable amplifiers and attenuators; digitally controlled calibration; programmable filters and oscillators; composite video; ultrasound; gain, offset, and voltage trimming.

General Instructions

The AD5426 /AD5432/AD5443 are CMOS 8-bit, 10-bit, and 12-bit current output digital-to-analog converters, respectively.

These devices operate from 3.0V to 5.5V supplies, making them suitable for battery powered applications and many others.

These DACs utilize a double-buffered 3-wire serial interface compatible with SPI® and QSPI 8482 ; MicroWire™, as well as most digital signal processor interface standards. Additionally, the Serial Data Out pin (SDO) allows daisy chaining when using multiple packs. A data readback allows the user to read the contents of the DAC register through the SDO pin. At power-up, the internal shift registers and latches are filled with 0s, and the DAC output is zero-scale.

Manufactured on a CMOS sub-micron process, they offer excellent four-quadrant multiplication characteristics with a large-signal doubling bandwidth of 10 MHz.

The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and a full-scale voltage output combined with an external current-to-voltage precision amplifier.

The AD5426/AD5432/AD5443 DACs are available in small 10-lead MSOP packages.

Typical Performance Characteristics - AD5426/AD5432/AD5443

the term

relative accuracy

Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line through the endpoints of the DAC transfer function. Measured after adjustment to 0 and full scale, usually expressed in LSB or percentage of full scale reading.

Differential nonlinearity

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. Specified differential nonlinearity of -1 LSB max over the operating temperature range ensures monotonicity.

gain error

Gain error or full-scale error is a measure of the output error between the ideal DAC and the actual device output. For these DACs, the ideal maximum output is VREF – 1lsb. The gain error of the DAC can be adjusted to zero with external resistors.

output leakage current

The output leakage current is the current that flows into the DAC ladder switch when it is closed. For the IOUT1 terminal, this can be measured by loading all 0s to the DAC and measuring the IOUT1 current. When the DAC is loaded with all 1s, minimum current will flow in the IOUT2 line.

output capacitor

Capacitor from IOUT1 or IOUT2 to AGND.

Output current settling time

This is the time required for the output to settle to the specified level for a full-scale input change. For these devices, the specified ground resistance is 100Ω.

The set-time specification includes a digital delay from the rising edge of synchronization to full-scale output charge.

Digital-to-analog fault pulse

The amount of charge injected from the digital input to the analog output when the input changes state. This is usually designated as the fault area, in pA secs or nV secs, depending on whether the fault is measured as a current or voltage signal.

digital feedthrough

When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled through the device to appear as noise on the output pins and subsequently into the following circuit. This noise is digital feedthrough.

Multiply by the feedthrough error

This is an error caused by capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded into the DAC.

Total Harmonic Distortion (THD)

The DAC is driven by the ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is THD. Usually only low-order harmonics are included, such as the second to fifth order.

digital intermodulation distortion

Second-order intermodulation distortion (IMD) measurement refers to the relative magnitude of the fa and fb tones digitally produced by the DAC and second-order products at 2fa-fb and 2fb-fa.

Spurious Free Dynamic Range (SFDR)

It is the available dynamic range of the DAC before spurious noise interferes or distorts the fundamental signal. SFDR is a measure of the difference in magnitude between the fundamental and the largest harmonic or non-harmonic related spur from dc to Nyquist's full bandwidth (half the DAC sampling rate, or fS/2). Narrowband SFDR is a way to measure SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the dynamic range available to a DAC when a sine wave is digitally generated.

DAC segment

The AD5426, AD5432, and AD5443 are 8-, 10-, and 12-bit current output DACs that consist of a standard inverted R-2R ladder structure. A simplified diagram of the 8-bit AD54246 is shown in Figure 4. The value of the feedback resistor RFB is R. The value of R is typically 10 kΩ (8 kΩ minimum, 12 kΩ maximum). If IOUT1 and IOUT2 are kept at the same potential, a constant current will flow in each rung regardless of the digital input code. Therefore, the input resistance at VREF is always constant, nominally the R value. The DAC output (IOUT) is related to the code, producing various resistances and capacitances. The selection of the external amplifier should take into account the impedance change produced by the DAC at the inverting input node of the amplifier.

Providing access to the DAC's VREF, RFB, IOUT1, and IOUT2 terminals makes the device very versatile and allows it to be configured in several different modes of operation, for example, providing unipolar output, bipolar mode, or 4-quadrant multiplication in single-supply operation. Note that the matching switch is used in series with the internal RFB feedback resistor. If the user attempts to measure RFB, VDD must be powered for continuity.

serial interface

The AD5426/AD5432/AD5443 have an easy-to-use 3-wire interface compatible with SPI/QSPI/MICROWIRE and DSP interface standards. Data is written to the device in 16-bit words. This 16-bit word consists of 4 control bits and 8, 10 or 12 data bits, as shown in Figure 5. The AD5443 uses all 12-bit DAC data. The AD5432 uses 10 bits and ignores the 2 LSBs, while the AD5426 uses 8 bits and ignores the last 4 bits.

Low power serial interface

To minimize the power consumption of the device, the interface is only fully powered up when the device is being written to, i.e. on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC.

DAC Control Bits C3 to C0

Control bits C3 through C0 allow control of various functions of the DAC, as shown in Table 1. The default settings when the DAC is powered up are as follows:

Data enters the shift register on the falling clock edge; daisy-chain mode is enabled. The device is powered up with a zero-scale load on the DAC register and the IOUT line.

The DAC control bits allow the user to adjust certain functions at power-up, for example, if not in use, daisy chaining may be disabled, active clock edges may be changed to rising edges, and DAC outputs may be cleared to zero or midscale. The user can also initiate a readback of the DAC register contents for verification purposes.

Sync function

Sync is an edge-triggered input used as a frame sync signal and chip enable. Data can be transferred to the device only when sync is low. To start serial data transfer, sync should be set low and observe the minimum setup time t4 for sync falling to the falling edge of SCLK.

Daisy Chain Mode

Daisy chaining is the default power-on mode. To disable the daisychain function, write 1001 to the control word. In daisy-chain mode, the internal strobe on SCLK is disabled. When sync is low, SCLK is continuously applied to the input shift register. If more than 16 clock pulses are applied, the data will fluctuate out of the shift register and appear on the SDO line. This data is clocked on the rising edge of SCLK (this is the default, use the control word to change the active edge) and is valid for the next device on the falling edge (the default). By connecting this wire to the DIN input on the next device in the chain, a multi-device interface is constructed. Each device in the system requires 16 clock pulses. Therefore, the total number of clock cycles must equal 16N, where N is the total number of devices in the chain. See the timing diagram in Figure 3.

Sync should be set high when the serial transfer to all devices is complete. This prevents any further data from being recorded into the input shift register. It is possible to use a burst clock that contains the exact number of clock cycles, with high synchronization after a period of time. After the rising edge of synchronization, data is automatically transferred from each device's input shift register to the addressing DAC.

When control bit = 0000, the device is in non-operational mode. In a daisy chain application, this can be useful if the user does not want to change the settings of a specific DAC in the chain. Simply write 0000 to the control bits of this DAC and the following data bits will be ignored.

solo mode

After power up, write 1001 control word to disable daisy chain mode. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift register. A rising edge of synchronization during a write causes the write cycle to abort.

Data is automatically transferred from the input shift register to the DAC after the falling edge of the 16th SCLK pulse. To make another serial transfer, the counter must be reset with a synchronous falling edge.

The circuit works in unipolar mode

Using a single op amp, these devices can be easily configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 6.

When the output amplifier is connected in unipolar mode the output voltage is given by:

where D is the fractional representation of the digital word loaded into the DAC and n is the number of bits.

D=0 to 255 (8-bit AD5426)

= 0 to 1023 (10-bit AD5432)

=0 to 4095 (12-bit AD5443)

Note that the output voltage polarity is opposite to VREF, these DACs are designed to operate with either a negative or positive reference voltage. The VDD supply pin is only used by internal digital logic to drive the "on" and "off" states of the DAC switches.

These digital-to-analog converters are also designed to accommodate AC reference input signals in the -10V to +10V range.

With a fixed 10V reference voltage, the circuit shown in Figure 6 will provide a unipolar 0V to -10V output voltage swing. When the VIN is an AC signal, the circuit performs 2-quadrant multiplication.

Table 2 shows the relationship between the digital code and the expected output voltage for unipolar operation (AD5426, 8-bit device).

Bipolar Operation

In some applications, it may be necessary to generate a full four-quadrant multiply operation or a bipolar output swing. This can be achieved by using another external amplifier and some external resistors as shown in Figure 7. In this circuit, the second amplifier A2 provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage enables full four-quadrant multiplication. The transfer function of this circuit shows that positive and negative output voltages are produced when the input data (D) is incremented from code 0 (VOUT=-VREF) to mid-scale (VOUT=0v) to full-scale (VOUT=+VREF).

where D is the fractional representation of the digital word loaded into the DAC and n is the resolution of the DAC.

D=0 to 255 (8-bit AD5426)

= 0 to 1023 (10-bit AD5432)

=0 to 4095 (12-bit AD5443)

When the VIN is an AC signal, the circuit performs four-quadrant multiplication.

Table 3 shows the relationship between the digital code and the expected output voltage for bipolar operation (AD5426, 8-bit device).

stability

In an I-to-V configuration, the output of the DAC and the inverting node of the op amp must be connected together as closely as possible, and proper PCB layout techniques must be employed. Since each code change corresponds to a step function, gain peaking can occur if the op amp has finite GBP and excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole in the open-loop response, which can cause ringing or instability in closed-loop applications.

An optional compensation capacitor C1 can be used with the stability RFB shown in Figures 6 and 7. A value of C1 that is too small will cause ringing at the output, while a value that is too large will adversely affect the settling time. C1 should be determined empirically, but 1-2 pF is usually sufficient to compensate.

Current Mode Operation for Single Supply Applications

These DACs are specified and tested to ensure operation in single-supply applications. Figure 8 shows a typical 3.0V to 5V supply operation circuit. In the current mode circuit of Figure 8, the amounts IOUT2 and IOUT1 are applied to VBIAS are biased positive.

In this configuration, the output voltage is given by:

Because D varies from 0 to 255 (AD5426), 1023 (AD5432), or 4095 (AD5443), the output voltage varies from:

VBIAS should be a low impedance source capable of sinking and sourcing all possible current variations on the IOUT2 terminal without any problems.

It is important to note that the Vehicle Identification Number (VIN) is limited to low voltages since the switches in the DAC ladder no longer have the same source and drain drive voltages. Therefore, their on-resistance is different, which reduces the linearity of the DAC. See TPCs 10 to 15.

Voltage switching operating mode

Figure 9 shows these DACs operating in voltage switching mode. The reference voltage VIN is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage produces a positive output voltage, enabling single-supply operation. The output from the DAC is a constant impedance (DAC ladder) voltage, so an op-amp is required to buffer the output voltage. The reference input is no longer a constant input impedance, but an input impedance that varies with code. Therefore, the voltage input should be driven by a low impedance source.

Also, the negative value of the vehicle identification number (VIN) must not exceed 0.3v, otherwise the internal diode will turn on and exceed the maximum rating of the device. In this type of application, the full multiplication capability of the DAC is lost.

Positive output voltage

Note that the output voltage polarity is opposite to the VREF polarity of the DC reference voltage. To obtain a positive voltage output, applying a negative reference to the input of the DAC is preferred over inversion of the output through an inverting amplifier due to resistor tolerance errors. To generate a negative reference, the reference can be level shifted by an op amp so that the VOUT and GND pins of the reference become virtual ground and -2.5v, respectively, as shown in Figure 10.

increase gain

In applications that require an output voltage greater than VIN, additional external amplifiers can be used to increase the gain, or the gain can be implemented in a single stage. It is very important to consider the effect of the temperature coefficient of the DAC thin film resistance. Simply placing the resistor in series with the RFB resistor will result in a mismatch in the tempco, resulting in a larger gain tempco error. Instead, the circuit of Figure 11 is the recommended way to increase the gain of the circuit. R1, R2, and R3 should all have similar temperature coefficients, but they do not need to match the temperature coefficient of the DAC. This approach is recommended in circuits that require gains greater than 1.

Use as a frequency divider or programmable gain element

Current control DACs are very flexible and suitable for many different applications. If this type of DAC is connected as the feedback element of the op amp and RFB is used as the input resistor, as shown in Figure 12, the output voltage is inversely proportional to the digital input fraction D.

For D=1–2n, the output voltage is:

When D decreases, the output voltage increases. For fractional numbers, D, it is important to ensure that the amplifier does not saturate and that the required accuracy is met. For example, in the circuit of Figure 12, an 8-bit DAC (i.e. 16-bit decimal) driven with binary code 0x10 (00010000) should result in an output voltage of 16 VIN. However, if the DAC has a linear specification of ±0.5lsb, then D can actually be weighted anywhere in the range of 15.5/256 to 16.5/256 so that the possible output voltage will be in the range of 15.5vin to 16.5vin with an error of + 3%, even though the DAC itself has a maximum error of 0.2%.

DAC leakage current is also a potential source of error in the voltage divider circuit. The leakage current must be balanced by the reverse current provided by the op amp through the DAC. Since only a fraction of the current going into the VREF terminal, D, is routed to the IOUT1 terminal, the output voltage must be changed as follows:

where R is the DAC resistance on the VREF terminal. For 10na, R=10kΩ DAC leakage current and a gain of 16 (ie 1/D), the error voltage is 1.6mv.

Reference selection

When selecting a reference for use with the AD5426 family of current output DACs, pay attention to the reference output voltage temperature coefficient specification. This parameter affects not only full-scale error, but also linearity (INL and DNL) performance. The reference temperature coefficient should meet the system accuracy specification. For example, over the temperature range of 0°C to 50°C, an 8-bit system needs to keep its overall specification within 1LSB, which requires the system to have a maximum temperature drift of less than 78ppm/°C. A 12-bit system with the same overall specification requires a maximum drift of 10ppm/°C accuracy reference over a temperature range of 2LSB, a low output temperature coefficient, and a small source of error. Table IV presents some references available from analog devices suitable for use with this range of current output DACs.

Amplifier selection

The main requirement for current steering mode is an amplifier with low input bias current and low input bias voltage. The op amp's input bias voltage is multiplied by the circuit's variable gain (due to the DAC's code-dependent output resistance). Changes in noise gain between two adjacent digital sections cause a step change in the output voltage due to the amplifier's input offset voltage. This output voltage change is superimposed on the desired output change between the two codes and creates a differential linearity error that, if the error is large enough, can cause the DAC to be non-monotonic. In general, the input offset voltage should be a fraction of the LSB (~<1/4) to ensure behavior when single stepping through the code.

The input bias current of the op amp is also biased at the voltage output by the bias current in the feedback resistor RFB. The input bias current of most op amps is low enough to prevent any major errors in 12-bit applications.

The common-mode rejection of an op amp is very important in voltage switching circuits because it produces a code-dependent error at the voltage output of the circuit. Most op amps have sufficient common-mode rejection for 8-, 10-, and 12-bit resolutions.

If the DAC switches are driven from a true broadband low impedance source (VIN and AGND), they settle down quickly. Therefore, the slew rate and settling time of a voltage-switched DAC circuit are highly dependent on the output op amp. In order to obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF node of the DAC (the voltage output node in this application). This is accomplished by using a low input capacitance buffer amplifier and careful board design.

Most single-supply circuits include ground as part of the analog signal range, which in turn requires an amplifier capable of handling rail-to-rail signals, and there are plenty of single-supply amplifiers available in analog equipment.

Microprocessor interface

The microprocessor interfaces with this series of DACs through a serial bus that uses standard protocols compatible with microcontrollers and DSP processors. The communication channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5426/AD5432/AD5443 require a 16-bit word, the default is data valid on the falling edge of SCLK, but this can be changed with control bits in the data word.

ADSP-21xx to AD5426/AD5432/AD5443 interface

The ADSP-21xx family of DSPs easily interface with this family of DACs without the need for additional glue logic. Figure 13 shows an example of the SPI interface between the DAC and the ADSP-2191M. The SCK of the digital signal processor drives the serial data line. Sync is driven from a port row, in this case SPIxSEL.

The serial interface between the DAC and DSPSORT is shown in Figure 14. In this interface example, SPORT0 is used to transfer data to the DAC shift register. After enabling motion, a transfer is initiated by writing a word to the Tx register. During the write sequence, data is clocked into the DAC input shift register on every rising edge of the DSPs serial clock and on the falling edge of its SCLK. Updates to the DAC output occur on the rising edge of the sync signal.

Communication between two devices at a given clock speed is possible when the following specifications are compatible: Frame Sync Delay and Frame Sync Set and Hold, Data Delay and Data Set and Hold, and SCLK Width. The DAC interface expects t4 (sync falling edge to SCLK falling edge setup time) to be a minimum of 13 ns. Refer to the ADSP-21xx User Manual for information on the clock and frame sync frequencies for the motion registers.

The settings of the motion control registers are as follows:

TFSW=1, alternate frames

INVTFS=1, valid low frame signal

DTYPE=00, right-aligned data

ISCLK=1, internal serial clock

TFSR=1, frame per word

ITFS=1, internal frame signal SLEN=1111, 16-bit data word

80C51/80L51 to AD5426/AD5432/AD5443 interface

The serial interface between the DAC and the 8051 is shown in Figure 15. The 8051's TxD drives the SCLK of the DAC serial interface, while the RxD drives the serial data line DIN. P3.3 is a bit programmable pin on the serial port to drive sync. When data is transferred to the switch, P3.3 is taken low. The 80C51/80L51 only transmits data in 8-bit bytes; therefore, only 8 falling clock edges occur during the transmit cycle. To properly load the data into the DAC, P3.3 is held low after the first 8 bits have been sent and a second write cycle is initiated to send the second byte of data. Data on RxD is clocked by the microcontroller on the rising edge of TxD and valid on the falling edge. Therefore, no glue logic is required between the DAC and microcontroller interface. P3.3 rises after this cycle is completed. The 8051 provides the LSB of its SBUF register as the first bit in the data stream. The DAC input register requires its data to be received as the first bit MSB. The transfer program should take this into account.

68HC11 product parameters, documentation and source information" target="_blank">MC68HC11 interface to AD5426/AD5432/AD5443 interface

Figure 16 shows an example of the serial interface between the DAC and the MC68HC11 microcontroller. The Serial Peripheral Interface (SPI) on the MC68HC11 is configured in master mode (MSTR=1), clock polarity bit (CPOL)=0 and clock phase bit (CPHA)=1. SPI is configured by writing to the SPI Control Register (SPCR) - see the 68HC11 User Manual. The SCK of the 68HC11 drives the SCLK of the DAC interface, and the MOSI output drives the serial data line (DIN) of the AD5516. The sync signal comes from the port line (PC7). When data is sent to the AD5516, the sync line is taken low (PC7). Data displayed on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11 is transmitted in 8-bit bytes, with only 8 falling clock edges during the transmission cycle. The data MSB is transferred first. To load data into the DAC, after the first 8 bits have been transferred, PC7 is held low and a second serial write is performed to the DAC. At the end of this routine, PC7 is set to a high value.

If the user wants to verify the data previously written to the input shift register, the SDO line can be connected to the MISO of the MC68HC11, and with sync low, the shift register will clock the data out on the rising edge of SCLK.

Microwire to AD5426/AD5432/AD5443 Interface

Figure 17 shows the interface between the DAC and any Microwire compatible device. Serial data is shifted on the falling edge of serial clock SK and clocked into the DAC input shift register on the rising edge of SK, which corresponds to the falling edge of DACs SCLK.

PIC16C6x/7x to AD5426/AD5432/AD5443

The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI master with Clock Polarity Bit (CKP) = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See the PIC16/17 Microcontroller User's Manual. In this example, I/O port RA1 is used to provide the sync signal and the DAC-enabled serial port. The microcontroller transfers only 8 bits of data during each serial transfer operation; therefore, two consecutive write operations are required. Figure 18 shows the connection diagram.

PCB Layout and Power Supply Decoupling

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5426/AD5432/AD5443 is mounted should be designed to keep the analog and digital sections separate and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND to DGND connection, it should only be connected at one point. The star ground point should be as close as possible to the device.

These DACs should have adequate supply bypass, 10 F in parallel with 0.1 F on the power supply, which should be as close to the package as possible, ideally right across the device. 0.1f capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as a common ceramic type that provides a high frequency, low impedance path to ground to handle transient currents caused by internal logic switching. Low ESR 1 F to 10f tantalum or electrolytic capacitors should also be applied to the power supply to minimize transients and filter low frequency ripple.

Fast switching signals such as clocks should use a digital ground shield to avoid radiating noise to other parts of the board and must not run near the reference input.

Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Microstrip technology is by far the best, but not always possible with double sided. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.

It is a good practice to design a printed circuit board layout with a compact, minimum lead length. The wires to the input should be kept as short as possible to minimize IR drop and stray inductance.

The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-To-V amplifier should be as close to the device as possible.

AD5426/AD5432/AD5443 Family of DAC Evaluation Boards

The board consists of a 12-bit AD5443 and a current-voltage amplifier AD8065. A 10 V reference ADR01 is included on the evaluation board. External references can also be applied via SMB import.

The evaluation kit includes a CD-ROM with self-installing PC software for controlling the DAC. The software only allows the user to write code to the device.

Operating the Evaluation Board Power Supply

The board requires ±12 V and +5 V supplies. The +12v of VDD and VSS is used to power the output amplifier, while the +5v is used to power the DAC (VDD1) and the transceiver (VCC).

Both supplies are separated from their respective ground planes with 10f tantalum and 0.1f ceramic capacitors.

Link1 (LK1) is provided to allow selection between an on-board reference (ADR01) or an external reference applied via J2. For the AD5426/AD5432/AD5443, use Link2 in the SDO position.

Dimensions: Dimensions are in millimeters